ICB2FL01GXUMA2_技术文档

Datasheet V1.2 May 2010

ICB2FL01G

Smart Ballast Control IC for

Fluorescent Lamp Ballasts

Published by Infineon Technologies AG

http://www.infineon.com

IFAG IMM API SPI AC TM

N e v e r s t o p t h i n k i n g

2^ndGeneration FL-Controller for FL-Ballasts

ICB2FL01G

Revision History

Datasheet ICB2FL01G

Actual Release: V1.2 Date: 05.05.2010

Previous Release: 18.02.2009

Page of

Subjects changed since last release

actual Rel. prev. Rel.

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Figure 1 Update

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LVS1 Text Update

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Figure 3 Update

Capter 2.4.2.1 Text Update and Figure 15 Update

PFC ON Time versus i_ZCDSignal

Update of Figure 26 and Text

Update 3.3 State Diagram

Update Protection Function Matrix HS Fil. Detection @ LVS1

BOM Update deleted Partnumbers of MOSFETs

Figure 42 Schematic of a serial Lamp Ballast Design

Figure 42 rename in Figure 43 and shift one page

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Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

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conditions or characteristics. With respect to any examples or hints given herein, any typical

values stated herein and/or any information regarding the application of the device,

Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind,

including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

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For further information on technology, delivery terms and conditions and prices, please

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Due to technical requirements, components may contain dangerous substances. For information

on the types in question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with

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reasonably be expected to cause the failure of that life-support device or system or to affect

the safety or effectiveness of that device or system. Life support devices or systems are

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and/or protect human life. If they fail, it is reasonable to assume that the health of the user

or other persons may be endangered.

Datasheet

Page 2 from 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

^2ndGeneration FL-Controller for

Fluorescent Lamp Ballasts

Product Highlights

Lowest Count of external Components

900V-Half-Bridge driver with coreless Transformer Technology

Supports Customer In-Circuit Test Mode for reduced Tester Time

Supports Multi-Lamp Designs

Integrated digital Timers up to 40 seconds

Numerous Monitoring and Protection Features for highest Reliability

All Parameter are valid over a wide Temperature Range of T_J= - 25°C until + 125°C

Features PFC

Discontinuous Mode PFC for Load Range 0 to 100%

Integrated digital Compensation of PFC Control Loop

Improved Compensation for low THD of AC Input Current also in DCM Operation

Adjustable PFC Current Limitation

Features Lamp Ballast Inverter

Adjustable Detection of Overload and Rectifier Effect (EOL)

Detection of Capacitive Load operation

Improved Ignition Control allows Operation close to the magnetic Saturation of the lamp Inductors

Restart with skipped Preheating at short interruptions of Line Voltage (for Emergency Lighting)

Parameters adjustable by Resistors only

Pb-free Lead Plating; RoHS compliant

Figure 1: Typical Application Circuit of Ballast for a single Fluorescent Lamp

Description

The FL-Controller ICB2FL01G is designed to control fluorescent lamp ballast including a

discontinuous mode Power Factor Correction (PFC), a lamp inverter control and a high voltage level

shift half-bridge driver.

The control concept covers requirements for T5 lamp ballasts for single and multi-lamp designs.

ICB2FL01G is based on the 1^stGeneration FL-Controller Technology, is easy to use and simply to

design in. Therefore a basis for a cost effective solution for fluorescent lamp ballasts of high reliability.

Figure 1 shows a typical application circuits of ballast for a single fluorescent T8 lamp with current

mode preheat.

Datasheet

Page 3 from 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Table of Contents

1

Pin Configuration and Description............................................................................................... 6

1.1

1.2

Pin Configuration....................................................................................................................... 6

Pin Description.......................................................................................................................... 6

2

Functional Description ................................................................................................................ 11

2.1

2.2

Typical Application Circutry..................................................................................................... 11

Normal Start Up ...................................................................................................................... 12

2.2.1 Operating Levels from UVLO to Soft Start............................................................................ 13

2.2.2 Operating Levels from Soft Start to Run Mode..................................................................... 15

2.3

Filament Detection during Start Up and Run Mode................................................................ 17

2.3.1 Start Up with broken Low Side Filament............................................................................... 17

2.3.2 Low Side Filament Detection during Run Mode.................................................................... 18

2.3.3 Start Up with broken High Side Filament.............................................................................. 19

2.4

PFC Pre Converter.................................................................................................................. 20

2.4.1 Discontinuous Conduction and Critical Conduction Mode Operation................................... 20

2.4.2 PFC Bus Voltage Sensing..................................................................................................... 21

2.4.2.1

2.4.2.2

Bus Over Voltage and PFC Open Loop ................................................................... 21

Bus Voltage 95% and 75% Sensing......................................................................... 21

2.4.3 PFC Structure of Mixed Signal.............................................................................................. 22

2.4.4 THD Correction via ZCD Signal ............................................................................................ 23

2.4.5 Optional THD Correction dedicated for DCM Operation....................................................... 24

2.5

Detection of End-of-Life and Rectifier Effect........................................................................... 25

2.5.1 Detection of End of Life 1 (EOL1) – Lamp Overvoltage........................................................ 25

2.5.2 Detection of End-of-Life (EOL2) – Rectifier Effect ................................................................ 26

2.6

Detection of Capacitive Load.................................................................................................. 27

2.6.1 Capacitive Load 1 (Idling Detection – Current Mode Preheating) ........................................ 28

2.6.2 Capacitive Load 2 (Over Current / Operation below Resonance) ........................................ 28

2.6.3 Adjustable self adapting Dead Time ..................................................................................... 29

2.7

Emergency Lighting ................................................................................................................ 30

2.7.1 Short Term PFC Bus Under Voltage..................................................................................... 31

2.7.2 Long Term PFC Bus Under Voltage ..................................................................................... 32

2.8

Built in Customer Test Mode Operation.................................................................................. 33

2.8.1 Pre Heating Test Mode ......................................................................................................... 33

2.8.1.1

2.8.1.2

Skip the Pre Heating Phase – Set RTPH Pin to GND.............................................. 33

IC remains in Pre Heating Phase ............................................................................. 34

2.8.2 Deactivation of the Filament Detection ................................................................................. 35

2.8.3 Built in Customer Test Mode (Clock Acceleration) ............................................................... 36

2.8.3.1

2.8.3.2

Enabling of the Clock Acceleration........................................................................... 36

Starting the Chip with accelerated Clock.................................................................. 36

3

4

State Diagram ............................................................................................................................... 37

3.1

Features during different operating modes............................................................................. 37

Operating Flow of the Start UP Procedure into the Run Mode............................................... 38

Auto Restart and Latched Fault Condition Mode.................................................................... 39

3.2

3.3

Protection Functions Matrix........................................................................................................ 40

Datasheet

Page 4 from 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

5

Electrical Characteristics ............................................................................................................ 41

5.1

Absolute Maximum Ratings .................................................................................................... 41

Operating Range..................................................................................................................... 43

Characteristics ........................................................................................................................ 44

5.2

5.3

5.3.1 Power Supply Section........................................................................................................... 44

5.3.2 PFC Section .......................................................................................................................... 45

5.3.2.1

5.3.2.2

5.3.2.3

5.3.2.4

5.3.2.5

5.3.2.6

PFC Current Sense (PFCCS)................................................................................... 45

PFC Zero Current Detection (PFCZCD)................................................................... 45

PFC Bus Voltage Sense (PFCVS) ........................................................................... 45

PFC PWM Generation.............................................................................................. 46

PFC Gate Drive (PFCGD) ........................................................................................ 46

Auxiliary (AUX) ......................................................................................................... 46

5.3.3 Inverter Section ..................................................................................................................... 47

5.3.3.1

5.3.3.2

5.3.3.3

5.3.3.4

5.3.3.5

5.3.3.6

5.3.3.7

5.3.3.8

5.3.3.9

Low Side Current Sense (LSCS).............................................................................. 47

Low Side Gate Drive (LSGD) ................................................................................... 48

Inverter Control Run (RFRUN)................................................................................. 49

Inverter Control Preheating (RFPH, RTPH) ............................................................. 49

Restart after Lamp Removal (RES).......................................................................... 50

Lamp Voltage Sense (LVS1, LVS2)......................................................................... 50

High Side Gate Drive (HSGD).................................................................................. 51

Timer Section ........................................................................................................... 51

Built in Customer Test Mode .................................................................................... 51

6

7

Application Example.................................................................................................................... 52

6.1

Schematic Ballast 54W T5 Single Lamp................................................................................. 52

Bill of Material.......................................................................................................................... 53

Multi Lamp Ballast Topologies................................................................................................ 54

6.2

6.3

Package Outlines ......................................................................................................................... 56

Datasheet

Page 5 from 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

1

Pin Configuration and Description

1.1 Pin Configuration

Pin Symbol Function

1.2 Pin Description

LSCS (Low-side current sense, Pin 1)

This pin is directly connected to the shunt

resistor which is located between the Source

terminal of the low-side MOSFET of the inverter

and ground.

1

2

3

4

5

6

7

8

9

LSCS

LSGD

V_CC

GND

PFCGD

PFCCS

Low side current sense (inverter)

Low side Gate drive (inverter)

Supply voltage

Low side Ground

PFC Gate drive

Internal clamping structures and filtering

measures allow for sensing the Source current

of the low side inverter MOSFET without

additional filter components.

PFC current sense

There is a first threshold of 0.8V. If this

threshold is exceeded for longer than 500ns

during preheat or run mode, an inverter over

current is detected and causes a latched shut

down of the IC. The ignition control is activated

if the sensed slope at the LSCS pin reaches

typically 205 mV/µs ± 25 mV/µs and exceeds

the 0.8V threshold. This stops the decreasing of

the frequency and waits for ignition. The ignition

control is now continuously monitored by the

LSCS PIN. The Ignition control is designed to

handle a choke operation in saturation while

ignition in order to reduce the choke size.

PFCZCD PFC zero current detector

PFCVS

RFRUN

PFC voltage sense

Set R for run frequency

Set R for preheat frequency

Set R for preheating time

Restart after lamp removal

Lamp voltage sense 1

Lamp voltage sense 2

Auxiliary output

10 RFPH

11 RTPH

12 RES

13 LVS1

14 LVS2

15 AUX

16

Creepage distance

17 HSGND High side ground

If the sensed current signal exceeds a second

threshold of 1.6V for longer than 500ns during

start-up, soft start, ignition mode and pre-run,

the IC changes over into a latched shut down.

There are further thresholds active at this pin

during run mode that detects a capacitive mode

operation. A first threshold at 100mV needs to

sense a positive current during the second 50%

on-time of the low-side MOSFET for proper

operation (Capload 1). A second threshold of -

100mV senses the current before the high-side

MOSFET is turned on. A voltage level below of

this threshold indicates a faulty operation

(Capload 2). Finally a third threshold at 2.0 V

senses even short overcurrent during turn-on of

the high-side MOSFET such as they are typical

for reverse recovery currents of a diode

(Capload 2). If one of these three comparator

thresholds indicate wrong operating conditions

for longer than 620µs (Capload 2) or 2500ms

(Capload 1) in run mode, the IC turns off the

Gates and changes into fault mode due to

detected capacitive mode operation (non-zero

voltage switching).

18 HSVCC

19 HSGD

20

High side supply voltage

High side Gate drive (inverter)

Not connected

The threshold of -100mV is also used to adjust

the dead time between turn-off and turn-on of

the half-bridge drivers in a range of 1.25µs to

2.5µs during all operating modes.

Figure 2: Package PG-DSO-19-1

Datasheet

Page 6 from 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

The fall time of the Gate voltage is less than

LSGD (Low-side Gate drive, Pin 2)

50ns in order to turn off quickly.

The Gate of the low-side MOSFET in a half-

bridge inverter topology is controlled by this pin.

There is an active L-level during UVLO (under

voltage lockout) and a limitation of the max H-

level at 11.0 V during normal operation. In order

to turn-on the MOSFET softly (with a reduced

di_DRAIN/dt); the Gate voltage rises within 220ns

typically from L-level to H-level. The fall time of

the Gate voltage is less than 50ns in order to

turn off quickly. This measure produces

different switching speeds during turn-on and

turn-off as it is usually achieved with a diode

parallel to a resistor in the Gate drive loop. It is

recommended to use a resistor of typically 10Ω

between drive pin and Gate in order to avoid

oscillations and in order to shift the power

dissipation of discharging the Gate capacitance

into this resistor. The dead time between LSGD

signal and HSGD signal is self adapting

between 1.25µs and 2.5µs.

A resistor of typically 10Ω between drive pin

and Gate in order to avoid oscillations and in

order to shift the power dissipation of

discharging the Gate capacitance into this

resistor is recommended.

The PFC section of the IC controls a boost

converter as

discontinuous

a

PFC preconverter in

conduction

mode

(DCM).

Typically the control starts with Gate drive

pulses with a fixed on-time of typically 4.0µs at

V_ACIN= 230V increasing up to 22.7µs and with

an off-time of 47µs. As soon as sufficient zero

current detector (ZCD) signals are available,

the operation mode changes from a fixed

frequent operation to an operation with variable

frequency. The PFC works in

a

critical

conduction mode operation (CritCM) when

rated and / or medium load conditions are

present. That means triangular shaped currents

in the boost converter choke without gaps and

variable operating frequency. During low load

(detected by an internal compensator) we get

an operation with discontinuous conduction

mode (DCM) that means triangular shaped

currents in the boost converter choke with gaps

when reaching the zero current level and

variable operating frequency in order to avoid

steps in the consumed line current.

Vcc

(Supply voltage, Pin 3)

This pin provides the power supply of the

ground related section of the IC. There is a

turn-on threshold at 14.1V and an UVLO

threshold at 10.6V. Upper supply voltage level

is 17.5V. There is an internal zener diode

clamping V_CCat 16.3V (at I_VCC=2mA typically).

The maximum zener current is internally limited

to 5mA. For higher current levels an external

zener diode is required. Current consumption

during UVLO and during fault mode is less than

170µA. A ceramic capacitor close to the supply

and GND pin is required in order to act as a

low-impedance power source for Gate drive

and logic signal currents. In order to use a

skipped preheating after short interruptions of

mains supply it is necessary to feed the start-up

current (160µA) from the bus voltage. Note: for

external V_CCsupply see notes in flowchart

chapter 3.3.

PFCCS (PFC current sense, Pin 6)

The voltage drop across a shunt resistor

located between Source of the PFC MOSFET

and GND is sensed with this pin. If the level

exceeds a threshold of 1.0 V for longer than

200ns the PFC Gate drive is turned off as long

as the zero current detector (ZCD) enables a

new cycle. If there is no ZCD signal available

within 52µs after turn-off of the PFC Gate drive,

a new cycle is initiated from an internal start-up

timer.

PFCZCD (PFC zero current detector, Pin 7)

This pin senses the point of time when the

current through boost inductor becomes zero

during off-time of the PFC MOSFET in order to

initiate a new cycle.

GND (Ground, Pin 4)

This pin is connected to ground and represents

the ground level of the IC for supply voltage,

Gate drive and sense signals.

The moment of interest appears when the

voltage of the separate ZCD winding changes

from positive to negative level which represents

a voltage of zero at the inductor windings and

therefore the end of current flow from lower

input voltage level to higher output voltage

level. There is a threshold with hysteresis, for

increasing level 1.5V, for decreasing level 0.5V,

which detects the change of inductor voltage.

PFCGD (PFC Gate drive, Pin 5)

The Gate of the MOSFET in the PFC

preconverter designed in boost topology is

controlled by this pin. There is an active L-level

during UVLO and a limitation of the max H-level

at 11.0 V during normal operation. In order to

turn-on the MOSFET softly (with a reduced

di_DRAIN/dt), the Gate drive voltage rises within

220ns

from

L-level

to

H-level.

Datasheet

Page 7 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

A resistor, connected between ZCD winding

RFRUN (Set R for run frequency, Pin 9)

A resistor from this pin to ground sets the

operating frequency of the inverter during run

mode. Typical run frequency range is 20 kHz to

120 kHz. The set resistor R_RFRUN can be

calculated based on the run frequency f_RUN

according to the equation:

and PIN 7, limits the sink and source current of

the sense pin when the voltage of the ZCD

winding exceeds the internal clamping levels

(6.3V and -2.9V typically @ 5mA) of the IC.

If the sensed voltage level of the ZCD winding

is not sufficient (e.g. during start-up), an internal

start-up timer will initiate a new cycle every

52µs after turn-off of the PFC Gate drive. The

source current out of this pin during the on-time

of the PFC-MOSFET indicates the voltage level

of the AC supply voltage. During low input

voltage levels the on-time of the PFC-MOSFET

is enlarged in order to minimize gaps in the line

current during zero crossing of the line voltage

and improve the THD (Total Harmonic

Distortion) of the line current. An optimization of

the THD is possible by trimming of the resistor

between this pin and the ZCD-winding.

5 10⁸ΩHz

R_FRUN

=

f_RUN

RFPH (Set R for preheat frequency, Pin 10)

A resistor from this pin to ground sets together

with the resistor at pin 9 the operating

frequency of the inverter during preheat mode.

Typical preheat frequency range is run

frequency (as a minimum) to 150 kHz. The set

resistor R_RFPH can be calculated based on

the preheat frequency f_PHand the resistor

PFCVS (PFC voltage sense, Pin 8)

R

_RFRUNaccording to the equation:

The intermediate circuit voltage (bus voltage) at

the smoothing capacitor is sensed by a resistive

divider at this pin. The internal reference

voltage for rated bus voltage is 2.5V. There are

further thresholds at 0.3125V (12.5% of rated

bus voltage) for the detection of open control

loop and at 1.875V (75% of rated bus voltage)

for the detection of an under voltage and at

2.725V (109% of rated bus voltage) for the

detection of an overvoltage. The overvoltage

threshold operates with a hysteresis of 100mV

(4% of rated bus voltage). For the detection of a

successful start-up the bus voltage is sensed at

95% (2.375V). It is recommended to use a

small capacitor between this pin and GND as a

spike suppression filter.

R_RFRUN

R_RFPH

=

f_PHR_RFRUN

−1

5 10⁸Ω

Hz

RTPH (Set R for preheating time, Pin 11)

A resistor from this pin to ground sets the

preheating time of the inverter during preheat

mode. A set resistor range from zero to 25kΩ

corresponds to a range of preheating time from

zero to 2500ms subdivided in 127 steps.

t_{Pr eHeating}

R_RTPH

=

ms

100

kΩ

In run mode, a PFC overvoltage stops the PFC

Gate drive within 5µs. As soon as the bus

voltage is less than 105% of rated level, the

Gate drives are enabled again. If the

overvoltage lasts for longer than 625ms, an

inverter overvoltage is detected and turns off

the inverter the gate drives also. This causes a

power down and a power up when V_BUS<109%.

RES (Restart, Pin 12)

A source current out of this pin via resistor and

filament to ground monitors the existence of the

low-side filament of the fluorescent lamp for

restart after lamp removal. A capacitor from this

directly

to

ground

eliminates

a

superimposed AC voltage that is generated as

a voltage drop across the low-side filament.

With a second sense resistor the filament of a

paralleled lamp can be included into the lamp

removal sense. Note: during start up, the chip

supply voltage Vcc has to be below 14.1V

before V_RESreaches the filament detection

level.

A

bus under- (V_BUS>75%) or inverter

overvoltage during run mode is handled as fault

U. In this situation the IC changes into power

down mode and generates a delay of 100ms by

an internal timer. Then start-up conditions are

checked and if valid, a further start-up is

initiated. If start-up conditions are not valid, a

further delay of 100ms is generated.

This procedure is repeated maximum seven

times. If a start-up is successful within these

seven cycles, the situation is interpreted as a

short interruption of mains supply and the

preheating is skipped. Any further start-up

attempt is initiated including the preheating.

Datasheet

Page 8 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

During typical start-up with connected filaments

During run mode the lamp voltage is monitored

with this pin by sensing a current proportional to

the lamp voltage via resistors. An overload is

indicated by an excessive lamp voltage. If the

peak to peak lamp voltage effects a peak to

peak current above a threshold of 21.3µA_PPfor

longer than 620µs, a fault EOL1 (end-of-life) is

assumed. If the DC current at the LVS pin

exceeds a threshold of ±42µA for longer than

2500ms, a fault EOL2 (rectifier effect) is

assumed. The levels of AC sense current and

DC sense current can be set separately by

external RC network. Note, in case of a

deactivation of the LVS1/2 PIN, a reactivation

starts, when the current out the LVS1/2 PIN

exceeds V_LVSEnable1in RUN Mode.

of the lamp a current source I_RES3(-21.3 µA) is

active as long as V_CC> 10.6V and V_RES< V_RES1

(1.6V). An open low-side filament is detected,

when V_RES> V_RES1. Such a condition will

prevent the start-up of the IC. In addition the

comparator threshold is set to V_RES2(1.3V) and

the current source changes to I_RES4(-17.7 µA).

Now the system is waiting for a voltage level

lower than V_RES2at the RES pin that indicates a

connected low-side filament, which will enable

the start-up of the IC.

An open high-side filament is detected when

there is no sink current I_LVSSINK(>18 µA) into

both of the LVS pins before the V_CCStart-up

threshold is reached. Under these conditions

the current source at the RES pin is I_RES1(-

42.6µA) as long as V_CC> 10.6V and V_RES

<

LVS2 (Lamp voltage sense 2, Pin 14)

LVS2 has the same functionality as pin LVS1

for monitoring in parallel an additional lamp

circuitry.

V_RES1(1.6V) and the current source is I_RES2(-

35.4 µA) when the threshold has changed to

V_RES2(1.3V). In this way the detection of the

high-side filament is mirrored to the levels on

the RES pin.

AUX (Auxiliary output, Pin 15)

There is a further threshold of 3.2V active at the

RES pin during run mode. If the voltage level

rises above this threshold for longer than

620µs, the IC changes over into latched fault

mode.

This pin provides a control current for a NPN

bipolar transistor during DCM operating mode

of the PFC section. There is a source current of

-450µA plus the current which is fed into pin

PFCZCD from the detector winding available

only during the enlarged off-time. That differ the

discontinuous conduction mode (DCM) from the

critical conduction mode (CritCM). With this

transistor a resistor for damping oscillations can

be switched to the ZCD winding in order to

minimize the line current harmonics during

DCM operating mode. If this function is not

used, this pin has to be not connected.

In any case of fault detection with different

reaction times the IC turns-off the Gate drives

and changes into power down mode with a

current consumption of 170µA max. An internal

timer generates a delay time of 200ms, before

start-up conditions are checked again. As soon

as start-up conditions are valid, a second start-

up attempt is initiated. If this second attempt

fails, the IC remains in latched fault mode until

a reset is generated by UVLO or lamp removal.

The RES PIN can be deactivated via set the

PIN to GND (durable).

Pin 16 Not Existing

PIN 16 does not exist, in order to provide a

wider creepage distance to the high-side gate

driver. Please pay attention to relevant

standards.

LVS1 (Lamp voltage sense 1, Pin 13)

Before start-up this pin senses a current fed

from the rectified line voltage via resistors

through the high-side filaments of the lamp for

the detection of an inserted lamp.

HSGND (High-side ground, Pin 17)

This pin is connected to the Source terminal of

the high-side MOSFET which is also the node

of high-side and low-side MOSFET. This pin

represents the floating ground level of the high-

side driver and the high-side supply.

The sensed current fed into the LVS pin has to

exceed 12 µA typically at a voltage level of 6.0

V at the LVS pin. The reaction on the high side

filament detection is mirrored to the RES pin

(see pin 12). In addition the detection of

available mains supply after an interruption is

sensed by this pin. Together with pin LVS2 and

pin RES the IC can monitor the lamp removal of

totally four lamps. If the functionality of this pin

is not required, e.g. for single lamp designs, it

can be disabled by connecting this pin to

ground.

Datasheet

Page 9 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

limitation of the max H-level at 11.0 V during

HSVCC (High-side supply voltage, Pin 18)

normal operation. The switching characteristics

are the same as described for LSGD (pin 2). It

is recommended to use a resistor of about 10 Ω

between drive pin and Gate in order to avoid

oscillations and in order to shift the power

dissipation of discharging the Gate capacitance

into this resistor. The dead time between LSGD

signal and HSGD signal is self adapting

between 1.25µs and 2.5µs (typically).

This pin provides the power supply of the high-

side ground related section of the IC. An

external capacitor between pin 17 and pin 18

acts like a floating battery which has to be

recharged cycle by cycle via high voltage diode

from low-side supply voltage during on-time of

the low-side MOSFET. There is an UVLO

threshold with hysteresis that enables high-side

section at 10.1V and disables it at 8.4V.

Not connected (Pin 20)

HSGD (High-side Gate drive, Pin 19)

This pin is internally not connected.

The Gate of the high-side MOSFET in a half-

bridge inverter topology is controlled by this pin.

There is an active L-level during UVLO and a

Datasheet

Page 10 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2

Functional Description

2.1 Typical Application Circutry

Figure 3: Application Circuit of Ballast for a single Fluorescent Lamp (FL)

The schematic in Figure 3 shows a typical application for a T5 single fluorescence lamp. It is designed

for universal input voltage from 90 V_ACuntil 270 V_AC. The following chapters are explaining the

components and referring to this schematic.

Datasheet

Page 11 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.2 Normal Start Up

This chapter describes the basic operation flow (8 phases) from the UVLO (Under Voltage Lock Out)

into Run Mode without any error detection. For detailed infromation see the following chapters 2.2.1

and 2.2.2. Figure 4 shows the 8 different phases during a typical start form UVLO (phase 1 Figure 4)

to Run Mode (phase 8 Figure 4) into normal Operation (no failure detected).

In case the AC line input is switched ON, the V_CCvoltage rises to the UVLO threshold V_CC= 10.6 V (no

IC activities during UVLO). If V_CCexceeds the first threshold of V_CC= 10.6 V, the IC starts the first level

of detection activity, the high and low side filament detection during the Start Up Hysteresis (phase 2

Figure 4).

Frequency /

Lamp Voltage

135 kHz

Frequency

100 kHz

6

1

2

3

4

5

7

8

50 kHz

42 kHz

Lamp Voltage

60ms

35ms

80ms

625ms

11ms

0 - 2500ms

40 - 237ms

Mode /

Time

0 kHz

Rated BUS

Voltage V_BUS

100 %

95 %

Rated BUS Voltage

30 %

Mode /

Time

Chip Supply

Voltage V_CC

V_CC= 17.5 V

Chip Supply Voltage

V_CC= 14.1 V

V_CC= 10.6 V

V_CC= 0 V

Mode /

Time

Run Mode

UVLO

Monitoring Start UpSoft Start Preheating

Pre-Run

Ignition

into normal Operation

Figure 4: Typical Start Up Procedure in Run Mode (in normal Operation)

Followed by the end of the Start Up Hysteresis (phase 2 Figure 4) V_CC> 14.1 V and before phase 3 is

active, a second level of detection activity senses for 80 µs (propagation delay of the IC) whether the

rated bus voltage is below 12.5 % or above 105 %. If the previous bus voltage conditions are fulfilled

and the filaments are detected, the IC starts the operation with an internally fixed startup frequency of

typically 135 kHz (all gates are active). In case the bus voltage reaches a level of 95% of the rated bus

voltage within latest 80ms (phase 3 Figure 4), the IC enters the Soft Start. During the Soft Start (phase

4 Figure 4), the Start Up frequency shifts from 135 kHz down to the set preheating frequency (chapter

2.2.2). In the Soft Start phase, the lamp voltage rises and the chip supply voltage reaches its working

level from 10.6 V < V_CC< 17.5 V. After finish the Soft Start, the IC enters the Preheating mode (phase

5 Figure 4) for preheating the filaments (adjustable time) in order to extend the life cycle of the FL

filaments. By finishing the preheating, the controller starts the Ignition (phase 6 Figure 4). During the

Ignition phase, the frequency decreases from the set preheating frequency down to the set operation

frequency (adjustable see chapter 2.2.2). If the Ignition is successful, the IC enters the Pre – Run

mode (phase 7 Figure 4).

Datasheet

Page 12 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

This mode is in order to prevent a malfunction of the IC due to an instable system e.g. the lamp

parameters are not in a steady state condition. After finish the 625 ms Pre Run phase, the IC switches

over to the Run mode (phase 8 Figure 4) with a complete monitoring.

2.2.1 Operating Levels from UVLO to Soft Start

This chapter describes the operating flow from phase 1 (UVLO) until phase 4 (Soft Start) in detail. The

control of the ballast is able to start the operation within less than 100 ms (IC in active Mode). This is

achieved by a small Start Up capacitor (about 1µF C12 and C13 – fed by start up resistors R11 and

R12 in Figure 3) and the low current consumption during the UVLO (I_VCC= 130 µA – phase 1 Figure 5)

and Start Up Hysteresis (I_VCC= 160 µA – defines the start up resistors – phase 2 Figure 5) phases.

The chip supply stage of the IC is protected against over voltage via an internal Zener clamping

network which clamps the voltage at 16.3 V and allows a current of 2.5 mA. For clamping currents

above 2.5 mA, an external Zener diode (D9 Figure 3) is required.¹

Figure 5: Progress of Level during a typical Start – UP

¹I_Gatedepends on MOSFET

Datasheet

Page 13 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

In case of V_CCexceeds the 10.6 V level and stays below 14.1 V (Start up Hysteresis – phase 2 Figure

5), the IC checks whether the lamps are assembled by detecting a current across the filaments.

The low side filaments are checked from a source current of typical I_RES3= - 21.3 µA out of PIN 12

RES

(Figure 5 I_RES). This current produces a voltage drop of V_RES< 1.6 V (filament is ok) at the low side

filament sense resistor (R 36 in Figure 3), connected to GND (via low side filament). An open low side

filament is detected (see chapter 2.3.2), when the voltage at the RES PIN exceeds the V_RES> 1.6V

threshold (Figure 5 V_RES).

The high side filaments are checked by a current of I_LVS> 12 µA typically via resistors R41, R42 and

R43 (Figure 3) into the LVS1 PIN 13 (for a single lamp operation) and LVS2 PIN 14 for a multi lamp

operation. Note: in case of a single lamp operation, the unused LVS PIN has to be disabled via

connection to GND. An open high side filament is detected (see 2.3.3) when there is no sink current

into the LVS PIN. This causes a higher source current out of the RES PIN (typical 42.6 µA / 35.4 µA)

in order to exceed V_RES> 1.6 V. In case of defect filaments, the IC keeps monitoring until there is an

adequate current from the RES or the LVS PIN present (e.g. in case of removal a defect lamp).

When V_CCexceeds the 14.1 V threshold - by the end of the start up hysteresis in phase 2 Figure 5 -

the IC waits for 80µs and senses the bus voltage. When the rated bus voltage is in the corridor of

12.5% < V_BUSrated< 105% the IC powers up the system and enters phase 3 (Figure 5 V_BUSrated> 95 %

sensing) when not, the IC initiates an UVLO when the chip supply voltage is below V_CC< 10.6 V. As

soon as the condition for a power up is fulfilled, the IC starts the inverter gate operation with an

internal fixed Start Up frequency of 135 kHz. The PFC gate drive starts with a delay of app. 300µs.

Now, the bus voltage will be checked for a rated level above 95 % for a duration of 80 ms (phase 3

Figure 5). When leaving phase 3, the IC enters the Soft Start phase and shifts the frequency from the

internal fixed Start Up frequency of 135 kHz down to the set Preheating frequency e.g. f_RFPH= 100

kHz.

Datasheet

Page 14 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.2.2 Operating Levels from Soft Start to Run Mode

This chapter describes the operating flow from phase 5 (Preheating mode) until phase 8 (Run mode)

in detail. In order to extend the life time of the filaments, the controller enters - after the Soft Start

Phase - the Preheating mode (phase 5 Figure 6). The preheating frequency is set by resistors R22

PIN RFPH to GND in combination with R21 (Figure 3) typ. 100 kHz e.g. R22 = 8.2 kꢀ in parallel to

R21 = 11.0 kꢀ see Figure 3 at theR_FRUN- PIN). The preheating time can be selected by the

programming resistor (R23 in Figure 3) at PIN RTPH from 0 ms up to 2500 ms (phase 5 Figure 6).

Figure 6: Typical Variation of Operating Frequency during Start Up

During Ignition (phase 6 Figure 6), the operating frequency of the inverter is shifted downward in t_typ

40 ms (t_max= 237 ms) to the run frequency set by a resistor (R21 in Figure 3) at PIN RFRUN to GND

(typical 45 kHz with 11.0 kꢀ resistor). During this frequency shifting, the voltage and current in the

resonant circuit will rise when the operation is close to the resonant frequency with increasing voltage

across the lamp. The ignition control is activated if the sensed slope at the LSCS pin reaches typically

205 mV/µs ± 25 mV/µs and exceeds the 0.8V threshold. This stops the decreasing of the frequency

and waits for ignition. The ignition control is now continuously monitored by the LSCS PIN. The

maximum duration of the Ignition procedure is limited to 237 ms. Is there no Ignition within this time

frame, the ignition control is disabled and the IC changes over into the latched fault mode.

Furthermore, in order to reduce the lamp choke, the ignition control is designed to operate with a lamp

choke in magnetic saturation during ignition. For an operation in magnetic saturation during ignition;

the voltage at the shunt at the LSCS pin 1 has to be V_LSCS= 0.75V when ingition voltage is reached. If

the ignition is successful, the IC enters the Pre – Run mode (phase 7 Figure 6). The Pre Run mode is

a safety mode in order to prevent a malfunction of the IC due to an instable system e.g. the lamp

parameters are not in a steady state condition. After 625 ms Pre Run mode, the IC changes into the

Run Mode (phase 8 Figure 6). The Run mode monitors the complete system regarding bus over- and

under voltage, open loop, over current of PFC and / or Inverter, lamp over voltage (EOL1) and rectifier

effect (EOL2) see chapter 2.5) and capacitive load 1 and 2 (see chapter 2.6).

=

Datasheet

Page 15 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

Figure 7 shows the lamp voltage versus the frequency during the different phases from Preheating to

the Run Mode. The lamp voltage rises by the end of the Preheating phase with a decreasing

frequency (e.g. 100 kHz to 50 kHz) up to 700 V during Ignition. After Ignition, the lamp voltage drops

down to its working level with continuo decreasing the frequency (Figure 7) down to its working level

e.g. 45 kHz (set by a resistor at the R_FRUNpin to ground). After stops the decreasing of the frequency,

the IC enters the Pre Run mode.

Lamp Voltage vs Frequency @ different Modes

1000

900

800

700

600

500

400

300

200

100

0

1000

900

800

700

600

500

400

300

200

100

0

10000

100000

Frequency [Hz]

After Ignition

Before Ignition

Figure 7: Lamp Voltage versus Frequency during the different Start up Phases

Datasheet

Page 16 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.3 Filament Detection during Start Up and Run Mode

The low and high side filament detection is sensed via the RES and the LVS pins. The low side

filament detection during start up and run mode is detected via the RES pin only. An open high side

filament during start up will be sensed via the LVS and the RES pins.

2.3.1 Start Up with broken Low Side Filament

A source current of I_RES3= - 21.3 µA out of the RES pin (12) monitors during a start up (also in Run

mode) the existence of a low side filament. In case of an open low side filament during the start up

hysteresis (10.6V < V_CC< 14.1V) a capacitor (C19 in Figure 3) will be charged up via I_RES3= - 21.3 µA.

When the voltage at the RES pin (12) exceeds V_RES1= 1.6 V, the controller prevents a power up and

clamps the RES voltage internally at V_RES= 5.0 V. The gate drives of the PFC and inverter stage do

not start working.

Figure 8: Startup with open Low Side

Filament

Figure 9: Restart from open Low Side

Filament

The IC comparators are set now to a threshold of V_RES1= 1.3V and to I_RES4= - 17.7µA, the controller

waits until the voltage at the RES pin drops below V_RES1= 1.3V.When a filament is present (Figure 9

section 2), the voltage drops below 1.3V and the value of the source current out of the RES pin is set

from I_RES4= - 17.7 µA up to I_RES3= - 21.3 µA. Now the controller powers up the system including Soft

Start and Preheating into the Run mode.

Datasheet

Page 17 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.3.2 Low Side Filament Detection during Run Mode

In case of an open low side filament during Run mode, the current out of the RES pin I_RES3= - 21.3 µA

charges up the capacitor C19 in Figure 3. If the voltage at the RES pin exceeds the V_RES3= 3.2V

threshold, the controller detects an open low side filament and stops the gate drives after a delay of t =

620µs of an internal timer.

Figure 10: Open Low Side Filament Run Mode

Figure 11: Restart from open LS Filament

A restart is initiated when a filament is detected e.g. in case of a lamp removal. In case of a filament is

present (Figure 11 section 2), the voltage drops below 1.3V and the value of the source current out of

the RES pin is set from I_RES4= - 17.7 µA up to I_RES3= - 21.3 µA. The controller powers up the system

including Soft Start and Preheating into the Run mode (Figure 11 section 3).

Datasheet

Page 18 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.3.3 Start Up with broken High Side Filament

An open high side filament during the start up hysteresis (10.6V < V_CC< 14.1V) is detected, when the

current into the LVS pin 13 or 14 is below I_LVS= 12 µA (typically). In that case, the current out of the

RES pin 12 rises up to I_RES1= - 42.6 µA. That causes a voltage at the RES pin crosses V_RES1= 1.6V.

The source current is now set to I_RES2= - 35.4 µA and another threshold of V_RES2= 1.3V is active. The

controller prevents a power up (see Figure 12), the gate drives of the PFC and inverter stage do not

start working.

V_CC

17.5 V

16.0 V

Restart from open HIGH Side Filament

V_CC

17.5 V

16.0 V

Start UP with OPEN HIGH Side Filament

Chip Supply Voltage

14.1 V

10.6 V

Time

Start Up

Hysteresis

V_RES

2.0 V

V_RES

UVLO

No Power Up

2.0 V

1.6 V

1.3 V

1.6 V

Power UP (into RUN Mode)

1.3 V

No Power UP

I_RES

Time

I_RES

42.6µA

35.4µA

21.3µA

17.7µA

42.6µA

35.4µA

21.3µA

17.7µA

I_RES

Time

I_LVS

12µA

V_Lamp

I_LVS

Time

V_Lamp

Time

Figure 13: Restart from open high Side

Filament

Figure 12: Start Up with open high Side

Filament

When the high side filament is present, e.g. insert a lamp, the current of the active LVS pins exceeds

I

_LVS> 12 µA (typically), the res current drops from I_RES2= - 35.4 µA down to I_RES4= - 17.7 µA (Figure

13). Now the controller senses the low side filament. When a low side filament is also present, and the

controller drops (after a short delay due to a capacitor at the res pin) below V_RES2= 1.3V, the res

current is set to I_RES3= - 21.3 µA, the controller powers up the system.

Datasheet

Page 19 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.4 PFC Pre Converter

2.4.1 Discontinuous Conduction and Critical Conduction Mode Operation

The digital controlled PFC pre converter starts with an internally fixed ON time of typical t_ON= 4.0µs

and variable frequency. The ON – time is enlarged every 280 µs (typical) up to a maximum ON – time

of 22.7 µs. The control switches quite immediately from the discontinuous conduction mode (DCM)

over into critical conduction mode (CritCM) as soon as a sufficient ZCD signal is available. The

frequency range in CritCM is 22 kHz until 500 kHz, depending on the power (Figure 14) with a

variation of the ON time from 22.7 µs > t_ON> 0.5µs.

Discontinuous Conduction Mode (DCM) <> Critical Condution Mode (CritCM)

1000,00

100,00

10,00

1,00

100,00

10,00

1,00

0,10

0,01

0,10

100,00

0,01

0,10

1,00

10,00

Normalized Output Power [%]

Frequency DCM

Frequency CritCM

Ton DCM

Ton CritCM

Figure 14: Operating Frequency and ON Time versus Power in DCM and CritCM Operation

For lower loads (P_OUTNorm< 8 % from the normalized load²) the control operates in discontinuous

conduction mode (DCM) with an ON – time from 4.0µs and increasing OFF – time. The frequency

during DCM is variable in a range from 144 kHz down to typically 22 kHz @ 0.1 % Load (Figure 14).

With this control method, the PFC converter enables a stable operation from 100 % load down to 0.1

%. Figure 14 shows the ON time range in DCM and CritCM (Critical Conduction Mode) operation. In

the overlapping area of CritCM and DCM is a hysteresis of the ON time which causes a negligible

frequency change.

²Normalized Power @ Low Line Input Voltage and maximum Load

Datasheet

Page 20 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.4.2 PFC Bus Voltage Sensing

Over voltage, open loop, bus 95 % and under voltage states (Figure 15) of the PFC bus voltage are

sensed at the PFCVS pin via the network R14, R15, R20 and C11 Figure 3 (C11 acts as a spike

suppression filter).

2.4.2.1

Bus Over Voltage and PFC Open Loop

The bus voltage loop control is completely integrated (Figure 16) and provided by an 8 Bit sigma –

delta A/D – converter with a typical sampling rate of 280 µs and a resolution of 4 mV/Bit. After leaving

phase 2 (monitoring), the IC starts the power up (VCC > 14.1V). After power up, the IC senses for

80µs – 130µs the bus voltage below 12.5% (open loop) or above 105% (bus over voltage). In case of

a bus over voltage (V_BUSrated> 109 %) or open loop (V_BUSrated< 12.5 %) in phases 3 until 8 the IC shuts

off the gate drives of the PFC within 5µs respective in 1µs. In this case, the PFC restarts automatically

when the bus voltage is within the corridor (12.5% < V_BUSrated< 105 %) again. Is the bus voltage after

the 80µs – 130µs valid, the bus voltage sensing is set to 12.5% < V_BUSrated< 109 %. In case leaving

these thresholds for longer than 1µ (open loop) or 5µs (overvoltage) the PFC gate drive stops working

until the voltage drops below 105% or exceeds the 12.5% level. If the bus over voltage (> 109%) lasts

for longer than 625ms in run mode, the inverter gates also shut off and a power down with complete

restart is attempt (Figure 15).

Figure 15: PFC Bus Voltage Operating Level and Error Detection

2.4.2.2

Bus Voltage 95% and 75% Sensing

When the rated bus voltage is in the corridor of 12.5% < V_BUSrated< 109 %, the IC will check whether

the bus voltage exceeds the 95 % threshold (Figure 15 phase 3) within 80 ms before entering the soft

start phase 4. Another threshold is activated when the IC enters the run mode (phase 8). When the

rated bus voltage drops below 75% for longer than 84 µs, a power down with a complete restart is

attempted when a counter exceeds 800 ms. In case of a short term bus under voltage (the bus voltage

reaches its working level in run mode before exceeding typically 800 ms (min. 500ms) the IC skips

phases 1 until 5 and starts with ignition (condition for emergency lighting see 2.7.1). The internal

reference level of the bus voltage sense V_PFCVSis 2.5 V (100 % of the rated bus voltage) with a high

accuracy. A surge protection is activated in case of a rated bus voltage of V_BUS> 109% and a low side

current sense voltage of V_LSCS> 0.8V for longer as 500ns in PRE RUN and RUN Mode.

Datasheet

Page 21 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.4.3 PFC Structure of Mixed Signal

A digital NOTCH filter eliminates the input voltage ripple - independent from the mains frequency. A

subsequent error amplifier with PI characteristic cares for a stable operation of the PFC pre converter

(Figure 16).

Over Voltage

109%

Open Loop

12.5%

PFCGD

PFCCS

PFCVS

Σ∆-ADC

Notch Filter

Gate Drive

PI Loop Control

PWM

Under Voltage

75%

Over Current

1V ± 5.0%

ZCD Start Up

1.5V / 0.5V

Bus Voltage

95%

PFCZCD

THD

Correction

Int. Reference

V_PFCVS= 2.5 V

Clock 870 kHz

Figure 16: Structure of the mixed digital and analog control of the PFC pre converter

The zero current detection (ZCD) is sensed by the PFCZCD pin via R13 (Figure 3). The information of

finished current flow during demagnetization is required in CritCM and in DCM as well. The input is

equipped with a special filtering including a blanking of typically 500 ns and a large hysteresis of

typically 0.5 V and 1.5 V V_PFCZCD(Figure 16).

Datasheet

Page 22 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.4.4 THD Correction via ZCD Signal

An additional feature is the THD correction (Figure 16). In order to optimize the improved THD

(especially in the zones A shown in Figure 17 ZCD @ AC Input Voltage), there is a possibility to

extend pulse width of the gate signal (blue part of the PFC gate signal in Figure 17) via variable PFC

ZCD resistor (see Resistor R13 in Figure 3) in addition to the gate signal controlled by the V_PFCVS

signal (gray part of the PFC gate signal in Figure 17).

ZCD @ AC Input Voltage

ZCD @ DC Input Voltage

Rectified

DC Input Voltage

AC Input Voltage

A

B

A

0

Voltage at

ZCD-Winding

PFC Gate

Drive Voltage

0

PFC gate signal (gray) controlled by the V_PFCVS

PFC gate signal (blue) controlled by the ZCD

Figure 17: THD Optimization using adjustable Pulse Width Extension

In case of DC input voltage (see DC Input Voltage in Figure 17), the pulse width gate signal is fixed as

a combination of the gate signal controlled by the V_PFCVSpin (gray) and the additional pulse width

signal controlled by the ZCD pin (blue) shown in Figure 17 ZCD @ DC Input Voltage.

The PFC current limitation at pin PFCCS interrupts the ON – time of the PFC MOSFET if the voltage

drop at the shunt resistors R18 (Figure 3) exceeds the V_PFCCS= 1.0 V (Figure 16). This interrupt will

restart after the next sufficient signal from ZCD is available (Auto Restart). The first value of the

resistor can be calculated by the ratio of the PFC mains choke and ZCD winding the bus voltage and a

current of typically 1.5 mA (see equation below). An adjustment of the ZCD resistor causes an

optimized THD.

N_ZCD

*V_BUS

N_PFC

R_ZCD

=

1.5mA

Equation 1: R_ZCDa good pratical Value

Datasheet

Page 23 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

The relationship between the extended PFC pulse width and the zero crossing detection current is

shown in Figure 19.

2.4.5 Optional THD Correction dedicated for DCM Operation

For applications with a wide input voltage range and / or for applications using a wide variation of the

power e.g. dimming, the application might work in the DCM (Discontinuous Conduction Mode). In

order to minimize the high order harmonics during DCM, the detection of the DCM should be as close

as possible at the point of inflection of the PFC drain source voltage shown in Figure 18. This can be

realized with an optional damping network (R4, D10 and Q4 from the AUX pin to the ZCD resistor

R13.

PFC Drain Source

Voltage

DCM

Detection

CritCM

Detection

0

t

Voltage at PFC

ZCD winding

with damping

Output current

at Pin AUX in DCM

0

t

PFC Gate Source

Voltage

t

0

Figure 18: Signal Shapes with optional damping

of oscillations during DCM operation of PFC

Figure 19: PFC ON Time Extension versus Zero

Crossing Current Signal

Figure 20: Optional Circuit for attenuating oscillations during DCM operation of PFC.

Datasheet

Page 24 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.5 Detection of End-of-Life and Rectifier Effect

Two effects are present by End of Life (EOL): lamp over voltage (EOL1) and a rectifier effect (EOL2).

After Ignition (see 1 in Figure 21), the lamp voltage breaks down to its run voltage level with

decreasing frequency. By reaching the run frequency, the IC enters the Pre Run Mode for 625 ms.

During this period, the EOL detection is still disabled. In the subsequent RUN Mode (2 in Figure 21)

the detection of EOL1 (lamp over voltage see 3 Figure 21) and EOL2 (rectifier effect see 4 Figure 21)

is complete enabled.

Figure 21: End of Life and Rectifier Effect

2.5.1 Detection of End of Life 1 (EOL1) – Lamp Overvoltage

The event of EOL1 is detected by measuring the positive and negative peak level of the lamp voltage

via an AC current fed into the LVS pin (Figure 22). This AC current is fed into the LVS pins (LVS1 for

single lamp and LVS2 for multi lamp applications) via Network R41, R42, R43 and the low pass filter

C40 and R45 see Figure 3. If the sensed AC current exceeds 210 µA_PPfor longer than 620 µs, the

status of end-of-life (EOL1) is detected (lamp overvoltage / overload see Figure 22 LVSAC Current).

The EOL1 fault results in a latched power down mode (after trying a single restart) the controller is

continuously monitoring the status until EOL1 status changes e.g. a new lamp is inserted.

Figure 22: End of Life (EOL1) Detection, Lamp Voltage versus AC LVS Current

Datasheet

Page 25 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.5.2 Detection of End-of-Life (EOL2) – Rectifier Effect

The rectifier effect (EOL2) is detected by measuring the positive and negative DC level of the lamp

voltage via a current fed into the LVS pin (Figure 23). This current is fed into the LVS pins (LVS1 for

single lamp and LVS2 for multi lamp applications) via Network R41, R42 and R43 (see Figure 3). If the

sensed DC current exceeds ± 42 µA (Figure 23 LVSDC Current) for longer than 2500 ms, the status of

end-of-life (EOL2) is detected. The EOL2 fault results in a latched power down mode (after trying a

single restart) the controller is continuously monitoring. Only the insert of a new lamp resets the status

of the IC.

Figure 23: End of Life (EOL2) Detection, Lamp Voltage versus DC LVS Current

Datasheet

Page 26 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.6 Detection of Capacitive Load

In order to prevent a malfunction in the area of Capacitive Load (see Figure 24) during Run Mode due

to certain deviations from the normal load (e.g. harmed lamp, sudden break of the lamp tube …), the

IC has three integrated thresholds – sensed only via the LSCS (pin 1). The controller distinguish

between two different states of capacitive load, the detection of working without load (idling detection,

CapLoad 1) and working with short over current (CapLoad 2). This state (CapLoad 2) is affecting an

operation below the resonance in the capacitive load area (Figure 24). In both cases, the IC results in

a latched power down mode after a single restart. After latching the power down mode, the controller

is continuously monitoring the status of the fault and restarts after the fault disappears e.g. in case of

inserting a new lamp.

Lamp Voltage vs Frequency @ different Modes

1000

900

800

700

600

500

400

300

200

100

0

1000

900

800

700

600

500

400

300

200

100

Area of Inductive

Load Behavior

IGNITION

Area of Capacitive

Load Behavior

Load

PRE Run

and

RUN Mode

After

Pre Heating

IGNITION

0

10000

100000

Frequency [Hz]

After Ignition

Before Ignition

Figure 24: Capacitive and Inductive Operation

Datasheet

Page 27 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.6.1 Capacitive Load 1 (Idling Detection – Current Mode Preheating)

A capacitive load 1 operation (idling) is detected when the voltage at the LSCS pin is below + 100 mV

during the second 50% ON – time of the low side MOSFET (see Capacitive Load 1 (Idling) in Figure

25). If this status is present for longer than 2500 ms, the controller results a latched power down mode

after trying a single restart. The controller is keep monitoring continuously the status until an adequate

load is present (e.g. lamp removal), than the IC changes into a normal operation.

Figure 25: Capacitive Mode 1 Operation without load during Run Mode

2.6.2 Capacitive Load 2 (Over Current / Operation below Resonance)

A capacitive load 2 operation is detected if the voltage at the LSCS pin drops below a second

threshold of V_LSCS= – 100 mV directly before the high side MOSFET is turned on or exceeds a third

threshold of V_LSCS= 2.0 V during ON switching of the high side MOSFET. If this over current is present

for longer than 620 µs, the IC results a latched power down mode after trying a single restart. The

controller keeps monitoring continuously the status until an adequate load is present e.g. a new lamp

is inserted, then the IC changes into a normal operation.

Normal Operation

Capacitive Load 2 (Over Current)

V_DSLS

I_DSLS

V_GateHS

V_GateLS

V_LSCS

+ 2.0 V

V_LSCS

+ 2.0 V

- 100 mV

t_{CAPLOAD 1}

Figure 26: Capacitive Mode 2 – Operation with Over Current

Datasheet Page 28 of 56

t_{CAPLOAD 2}

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.6.3 Adjustable self adapting Dead Time

The dead time between the turn OFF and turn ON of the half – bridge drivers is adjustable (C16 see

Figure 3) and detected via a second threshold (– 100 mV) of the LSCS voltage. The range of the dead

time adjustment is 1.25 µs up to 2.5 µs during all operating modes. Start of the dead time

measurement is the OFF switching of the high side MOSFET. The finish of the dead time

measurement is, when V_LSCSdrops for longer than typical 280ns (internal fixed propagation delay)

below -100mV. This time will be stored (stored dead time) and the low side gate driver switches ON.

The high side gate driver turns ON again after OFF switching of the low side switch and the stored

dead time.

Normal Operation in RUN Mode

V_DSLS

V_LSCS

V_LSCS= -100mV

END of Dead Time

Measurement

Gate LS

Gate HS

Dead Time

START of Dead Time

Measurement

280 ns

Propagation Delay

Stored Dead Time

Figure 27: Dead Time of ON and OFF of the Half Bridge Drivers

Datasheet

Page 29 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.7 Emergency Lighting

Line interruptions (bus voltage drops) are detected by the PFCVS. If the rated PFC bus voltage drops

below V_BUSRated< 75 % during run mode, the controller detects a PFC bus under voltage. In order to

meets the emergency lighting standards, the controller distinguishes two different states of a PFC bus

under voltage, a short and a long term PFC bus under voltage. A timer increases the time as long as a

bus under voltage is present. A short term bus under voltage is detected if the timer value stays below

t < 800ms typically (500ms min.) after the bus voltage reaches the nominal level again. These causes

a restart without preheating (emergency standard of VDE0108) see Figure 28. When the timer

exceeds t > 800 ms, the controller forces a complete restart of the system due to a long term bus

under voltage (Figure 29).

Datasheet

Page 30 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.7.1 Short Term PFC Bus Under Voltage

A short term PFC bus under voltage (Figure 28) is detected if the duration of the under voltage does

not exceed 800 ms (timer stays below t < 800ms see Figure 28). In that case, the PFC and inverter

drivers are immediately switched off and the controller is continuously monitoring the status of the bus

voltage in a latched power down mode (I_CC< 170 µA). If the signal at the LVS PIN exceeds 18µA and

the rated bus voltage is above 12.5% within the timer is below t < 800 ms, the controller restarts from

power up without preheating. The timer resets to 0 when entering the Run Mode.

Bus Voltage Drop for t < 800 ms

Restart without Preheating

Interrupt for

V_BUSRated

t < 800 ms

100%

75%

Power Down

RUN Mode

Pre Run

Run Mode

Mode

V_CC

16V

I_CC

< 6 mA +

I_QGate

< 6 mA + I_QGate

< 160 µA

Timer

t = 800ms

I_Preheating

V_Lamp

Figure 28: BUS Voltage Drop below 75% (rated Bus Voltage) for t < 800 ms during RUN Mode

Datasheet

Page 31 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.7.2 Long Term PFC Bus Under Voltage

If the duration of the bus under voltage exceeds t > 800ms see Figure 29, the controller forces an

under voltage lock out (UVLO). The chip supply voltage drops below V_CC= 10.6 V and the chip supply

current is below I_CC< 130µA. When the Vcc voltage exceeds the 10.6V threshold again, the IC current

consumption is below I_CC< 160µA. In that case, the controller resets the timer and restarts with the full

start up procedure including Monitoring, Power Up, Start Up, Soft Start, Preheating, Ignition, Pre Run

and Run Mode as shown in Figure 29.

Bus Voltage Drop for t > 800 ms

Restart with full Start Procedure

V_BUSRated

Interrupt for t > 800 ms

95%

75%

RUN Mode

Power Down Mode

Run Mode

V_CC

16V

UVLO @ 10.6V

I_CC

< 6 mA +

I_Gate

< 6 mA + I_Gate

< 160 µA

t = 800ms

<160 µA

Timer

I_Preheating

V_Lamp

Figure 29: BUS Voltage Drop below 75% (rated Bus Voltage) for t > 800 ms during RUN Mode

Datasheet

Page 32 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.8 Built in Customer Test Mode Operation

In order to decrease the final ballast testing time for customers, the 2^ndgeneration of ballast IC

supports an integrated built in Customer Test Mode and several functions to disable some features

and states of the IC.

2.8.1 Pre Heating Test Mode

This feature forces the IC to stay in the pre heating mode (see chapter 2.8.1.2) or to starts the ignition

immediately without any preheating (see chapter 2.8.1.1 skip pre heating). A resistor at this pin

defines the duration of the pre heating phase. Normally, the pre heating phase is in a range of 0ms up

to 2500ms set via a resistor R_RTPH= 0ꢀ up to 25kꢀ from the RTPH pin to GND. The pre heating phase

is skipped when the RTHP pin is set to GND. If the signal at this pin is V_RTPH> 5.0 V, the IC remains in

the pre heating mode.

2.8.1.1

Skip the Pre Heating Phase – Set RTPH Pin to GND

The Pre Heating phase can be skipped in set the RTPH pin 11 to GND. Figure 30 shows a standard

start up with a set pre heating time via resistor at the RTPH pin 11 to GND (e.g. 8.2 kꢀ this is equal to

a pre heating phase of app. 820ms). The pre heating phase can be skipped in setting the RTPH pin 11

directly to GND. In that case, the ignition is directly after the soft start phase.

Figure 31: Start UP WITHOUT Pre Heating

Figure 30: Start UP WITH Pre Heating

Datasheet

Page 33 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.8.1.2

IC remains in Pre Heating Phase

This feature gives the customer the flexibility to align the pre heating frequency to the filament power

in the pre heating phase. Figure 32 shows a standard start up with the set preheating time of e.g.

820ms with an 8.2 kꢀ resistor at the RTPH pin 11. To force the IC remains in pre heating, the voltage

level at the RTPH pin 11 has to set to 5.0 V. The duration of this 5.0 V signal defines the time of the

pre heating see I_PreHeatin figure below.

V_CC

17.5 V

16.0 V

14.1 V

Chip Supply Voltage

10.6 V

Time

Start Up

Hysteresis

UVLO

V_RTPH

5.0 V

2.5 V

Duration is set by

Resistor only

Time

I_PreHeat

Preheating

t = 820 ms when using

RRTPH = 8.2kOhm

V_Lamp

IGNITION

Time

Figure 32: Start UP with Pre Heating

Figure 33: Start UP REMAINS in Pre Heating

Datasheet

Page 34 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.8.2 Deactivation of the Filament Detection

In order to deactivate the filament detection of the low or high side filament, set the RES pin 12 or the

LVS1 / LVS2 pin 13 / 14 to GND. In that case, the IC starts up into normal operation without checking

the filaments e.g. when using an equivalent lamp resistive load instead of a load.

V_CC

17.5 V

16.0 V

14.1 V

Chip Supply Voltage

10.6 V

Time

Start Up

UVLO

Hysteresis

V_RES

5.0 V

LVS1 or LVS2 PIN set to GND

1.6 V

1.3 V

V_LSGD

10V

V_Lamp

Figure 34: Deactivation via RES PIN

Figure 35: Deactivation via LVS1 / LVS2 PIN

Figure 34 shows the deactivation of the low and high side filament via set the RES pin 12 to GND.

Figure 35 shows the deactivation of the high side filament detection via set the LVS1 or LVS2 pin to

GND.

Note

In case using just one path of a ballast design (single or dual lamp in series) one of the not used LVS

pins has to be set to GND.

Datasheet

Page 35 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Functional Description

2.8.3 Built in Customer Test Mode (Clock Acceleration)

The built in customer test mode, supported by this IC, saves testing time for customers in terms of

ballast end test. In that mode, the IC accelerates the internal clock in order to reduce the time of the 4

different procedures by the following factors (see Table 1).

Phase

Duration for Test [ms]

Acceleration Factor Nominal Duration [ms]

Preheating

Time Out Ignition

Pre Run Mode

EOL2

625

118.5

41.7

4

2

2500 (max)

237

15

60

625

2500

Table 1: Specified Acceleration Factors

2.8.3.1

Enabling of the Clock Acceleration

The clock acceleration (Built in Customer Test Mode) is activated when the chip supply voltage

exceeds V_CC> 14.1V and the voltages at the Run Frequency and Preheating Frequency pin are set to

V

_RFRUN= V_RFPH= 5.0 V (± 5 %) see Figure 35 “Enabling of Clock Acceleration”. A RES pin voltage of

_RES> 3.5 V up to 5.0 V (± 5 %) prevents a power up of the IC, the IC remains in a mode before

V

powering up. This status is hold as long as the voltage at the RES pin is at V_RES> 3.5 V up to 5.0 V (±

5 %) – no power up. Note: after the activation of the clock acceleration mode, the voltage level of 5.0V

at the Run Frequency and Preheating Frequency pin (V_RFRUN= V_RFPH) can be released.

2.8.3.2

Starting the Chip with accelerated Clock

In order to start the IC with an accelerated clock, set the voltage at the RES pin to GND (V_RES= 0 V).

Figure 36 “Starting the Chip with an accelerated Clock”. The IC powers up the system and starts

working with an accelerated clock. Now the duration of the different modes are accelerated by Factors

shown in Table 1

Figure 36: Clock Acceleration (Built in Customer Test Mode)

Datasheet

Page 36 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

State Diagram

3

State Diagram

3.1 Features during different operating modes

Figure 37: Monitoring Features during different operating Modes

Datasheet

Page 37 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

State Diagram

3.2 Operating Flow of the Start UP Procedure into the Run Mode

UVLO

Vcc < 10.6V

Icc < 130µA

Vcc > 10.6V

Monitoring

Vcc > 10.6V

Icc < 160µA

Vcc > Vccon(14.1V)

& Filament detected

Power-up

See

V

_BUS< 12,5%

Timing and Handling of

Fault Conditions

Gate Drives off

14.1V < Vcc

or V_BUS> 105%

Icc approx 6.0mA

after 130µs

& V_BUS> 12,5%

& V_BUS< 105%

Start-up

See

Protection

Functions

Inverter Gates on

PFC Gate on

17.5V> Vcc >10.6V

f_Inv = f_START

Fault

V_BUS> 95%

within 80ms

17.5V> Vcc >10.6V

Icc < 170µA

Gate Drives off

Softstart

17.5V> Vcc >10.6V

f_START=> f_PH

after 10ms

& Flag Skip Preheat

= Reset

& Flag Skip Preheat = Set

// Reset Flag

Skip Preheat

Preheat

& Counter Skip PH //

17.5V> Vcc >10.6V

f = f_PH

after t_PH= 0...2500ms

Time set by R_TPH

Ignition*

Timeout 237ms

17.5V> Vcc >10.6V

f_PH => f_RUN

f_Inv= f_RUN within

t_IGN= 40...237ms

Pre-Run

17,5V> Vcc >10.6V

f = f_RUN

Reduced Monitoring

after

t_PRERUN=

Ru⁶n^25ms

17.5V> Vcc >10.6V

f = f_RUN

* NOTE:

Ignition will reset the

Flag Skip Preheating

Complete Monitoring

Figure 38: Operating Flow during Start-up Procedure

Datasheet Page 38 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

State Diagram

3.3 Auto Restart and Latched Fault Condition Mode

Fault U

Fault A

Auto Restart

Fault F

Fault, single Restart

BUS Voltage

BUS Undervoltage

(VBUS < 75%

Open Filament LS;

Inverter Overcurrent;

Capacitive Load 1;

Capacitive Load 2;

Timeout Ignition;

Surge;

Time OUT Start Up

(VBUS < 95% for t >

80 ms)

during Run Mode

for t > 84µs);

BUS Overvoltage

(VBUS > 109%

for t > 625ms);

EOL 1 (Overload);

EOL 2 (Rectifier Effect);

Increment

NOTE

Fault Counter

Set Flag

to Set Flag Skip Preheat:

When using external Vcc

Supply, no reset of Set Flag

Skip Preheat. 1st Restart

without Preheating while

Vcc > UVLO. When LVS

deactivated or not from Line.

Skip Preheat

INVERTER and PFC Gate OFF

Only at Inverter Over current PFC Gate

OFF appr. 150µs Delayed

Gate drives off

Power down

Icc < 160µA

Power down Icc < 160µA

Wait 200ms

Wait 100ms

Delay Timer A

Increment

Fault Counter

Counter Skip PH

< 2

Y

N

Counter

Skip Preheat

>7?

Reset

Fault Counter

Y

N

Wait for

Lamp Removal

Start

Gate drives off

IC remains

Start-up

in active mode

Lamp removed

for min 100ms

Inverter Gates on

PFC Gate on

NOTE

17.5V> Vcc >10.6V

f_Inv = f_START

For external Vcc

Supply, set Vcc

below UVLO.

Lamp Inserted?

Or

N

Wait for

Lamp

Lamp inserted

inserted?

V

_BUS< 75%

N

Y

Lamp inserted

for min 100ms

Y

Wait for

UVLO

N

t > 80ms?

N

V_BUS> 95%?

from Power-Up

Reset

Vcc > 14.1V?

Flag Skip Preheat

& Counter Skip PH

Vcc < 10.6V?

Y

N

Fault A

Timeout 80ms

Start-up

Y

End

Note:

Start-up

Fault Counter reset

after 40s in Run Mode

Reset of Flag Skip

Power-up

UVLO

Gate Drives off

Reset all Latches

Preheat after Ignition

Figure 39: Operating Process during Start-up Mode and Handling of Fault Conditions

Datasheet

Page 39 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

4

Protection Functions Matrix

Description of Fault

Characteristics of fault

Operating Mode Detection is active

Consequence

Supply voltage Vcc < 14.1V

before power up

Below start-

up threshold

Below UVLO

threshold

S

F

1µs

Prevents power up

X

Supply voltage Vcc < 10.6V

after power up

5µs

Power down,

X

Reset failure latch

Prevents power up

Current into LVS1 pin < 18µA open

100µs

620µs

1µs

before power up

filament HS

Current into LVS2 pin < 18µA open

Prevents power up

before power up

filament HS

Voltage at RES pin > 1.6V

before power up

open

filament LS

open

Voltage at RES pin > 3.2V

Power down,latched

Fault Mode, 1 Restart

Keep Gate drives off, re-

start after Vcc hysteresis

Stops PFC FET until

VBUS > 12.5%

filament LS

Bus voltage < 12.5% of rated Open Loop

S

N

U

level 10µs after power up

Bus voltage < 12.5%

of rated level

detection

Open Loop

detection

Shut down

option

1µs

X

Bus voltage < 12.5%

of rated level

625ms

84µs

Power down, restart

when VBUS> 12.5%

Power down, 100ms

delay, restart, skip pre-

heating max 7 times

Bus voltage < 75%

of rated level

Under-

X

voltage

add. shut down delay 120µs

Bus voltage < 95% of rated

level during start-up

Timeout max

start-up time

A

S

N

U

F

N

F

A

80ms

Power down, 200ms

delay, restart

X

Keep Gate drives off, re-

start after Vcc hysteresis

Bus voltage > 105% of rated Over-

5µs

X

level 10µs after power up

voltage

Bus voltage > 109% of rated PFC

5µs

Stops PFC FET until

VBUS< 105%

X

level in active operation

Overvoltage

Bus voltage > 109% of rated Inverter

625ms

620µs

2500ms

620µs

237ms

200ns

500ns

Power down, restart

when VBUS<105%

Power down,latched

Fault Mode, 1 Restart

Power down,latched

Fault Mode, 1 Restart

Power down,latched

Fault Mode, 1 Restart

Power down,latched

Fault Mode, 1 Restart

Power down,latched

Fault Mode, 1 Restart

Stops on-time of PFC

FET immediately

level in active operation

Overvoltage

+/- peak level of lamp voltage EOL 1

at Pin LVS above threshold

DC level of lamp voltage

above +/- threshold

Overvoltage

EOL 2

Rect. Effect

Cap Load 1

Idling

Capacitive Load 1

Capacitive Load 2,

operation below resonance

Run frequency cannot be

achieved

Cap.Load 2

Overload

Timeout

Ignition

X

Voltage at PFCCS pin > 1.0V PFC

X

Overcurrent

Voltage at LSCS pin > 0.8V

Voltage at LSCS pin > 1.6V

Inverter

Activates

current lim

Inverter

Ignition control

Power down,latched

Fault Mode, 1 Restart

Power down,latched

Fault Mode, 1 Restart

Power down, restart

when VBUS<109%

overcurrent

Inverter

X

overcurrent

Inverter

Voltage at LSCS pin > 0.8V

& VBUS > 109% (Surge)

overcurrent

After jump into latched fault mode F wait

Reset of failure latch in run mode after

200ms A single restart attempt after delay of internal timer

40s Reset of failure latch by UVLO or 40s in run mode

A = Auto-Restart , U = Undervoltage

S = Start-up condition,

N = No Fault,

F = Fault with a single Restart, a second F leads to a latched fault / Note: all values @ typical 50 Hz mains frequency

Datasheet

Page 40 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Electrical Characteristics

5

Electrical Characteristics

Note: All voltages without the high side signals are measured with respect to ground (pin 4). The high side

voltages are measured with respect to pin17. The voltage levels are valid if other ratings are not

violated.

Absolute Maximum Ratings

5.1 Absolute Maximum Ratings

Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to

destruction of the integrated circuit. For the same reason make sure, that any capacitor that will be

connected to pin 3 (VCC) and pin 18 (HSVCC) is discharged before assembling the application

circuit.

Parameter

Symbol

Limit Values

Unit

Remarks

min.

max.

LSCS Voltage

LSCS Current

LSGD Voltage

V_LSCS

I_LSCS

V_LSGD

- 5

- 3

6

3

V

mA

V

mA

V

mA

V

mA

V

- 0.3

- 75

- 50

- 0.3

- 5

- 0.3

- 150

- 100

- 5

V_cc+0.3

Internally clamped to 11V

< 500ns

< 100ns

LSGD Peak Source Current

LSGD Peak Sink Current

VCC Voltage

VCC Zener Clamp Current

PFCGD Voltage

PFCGD Peak Source Current

PFCGD Peak Sink Current

PFCCS Voltage

I_LSGDsomax

I_LSGDsimax

V_VCC

I_VCCzener

V_PFCGD

I_PFCGDsomax

I_PFCGDsimax

V_PFCCS

I_PFCCS

V_PFCZCD

I_PFCZCD

V_PFCVS

V_RFRUN

V_RFPH

5

400

18.0

5

V_cc+0.3

5

IC in Power Down Mode

< 500ns

< 100ns

700

6

PFCCS Current

- 3

- 5

- 0.3

- 6

3

6

5

5.3

7

mA

V

mA

V

PFCZCD Voltage

PFCZCD Current

PFCVS Voltage

RFRUN Voltage

RFPH Voltage

RTPH Voltage

RES Voltage

LVS1 Voltage

V_RTPH

V_RES

V_LVS1

V

LVS1 Current1

LVS1 Current2

LVS2 Voltage

I_{LVS1_1}

I_{LVS1_2}

V_LVS2

- 1

- 3

- 6

1

3

7

mA

V

IC in Power Down Mode

IC in active Mode

LVS2 Current1

LVS2 Current2

I_{LVS2_1}

I_{LVS2_2}

- 1

- 3

1

3

mA

IC in Power Down Mode

IC in active Mode

Datasheet

Page 41 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Absolute Maximum Ratings

Parameter

AUX Voltage

HSGND Voltage

HSGND Voltage Transient

HSVCC Voltage

Symbol

Limit Values

Unit

Remarks

min.

max.

V_AUX

V_HSGND

dV_HSGND/dt

V_HSVCC

V_HSGD

I_HSGDsomax

I_HSGDsimax

T_J

- 0.3

- 900

- 40

- 0.3

- 75

0

- 25

- 55

—

5.3

900

40

V

V/ns

V

Referring to GND

18.0

_HSVCC+0.3

0

400

150

2

Referring to HSGND

Internally clamped to 11V

< 500ns

HSGD Voltage

V

HSGD Peak Source Current

HSGD Peak Sink Current

Junction Temperature

Storage Temperature

mA

°C

< 100ns

T_S

°C

Maximum Power Dissipation

Thermal Resistance (2 Chips)

Thermal Resistance (HS Chip)

Thermal Resistance (LS Chip)

Soldering Temperature

ESD Capability

P_TOT

R_thJA

R_thJAHS

R_thJALS

W

PG_DSO-19-1 T_amb=25°C

PG_DSO-19-1

Wave Soldoldering¹⁾

Human Body Model²⁾

—

60

K/W

°C

kV

mm

V

—

120

260

2

V_ESD

Creepage Distance HS vs. LS

Rated Bus Voltage (95%)

1.9

2.33

2.0

2.43

V_PFCVS95

¹⁾According to JESD22A111

²⁾According to EIA/JESD22-A114-B (discharging an 100 pF Capacitor through an 1.5kꢀ series Resistor)

Datasheet

Page 42 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Operating Range

5.2 Operating Range

Parameter

Symbol

Limit Values

Unit

Remarks

min.

Max.

17.5

900

17.5

18.0

5

HSVCC Supply Voltage

HSGND Voltage

VCC Voltage @ 25°C

V_HSVCC

V_HSGND

V_VCC

V_HSVCCOff

- 900

V_VCCOff

- 4

V

Referring to HSGND

Referring to GND

T_J= 25°C

VCC Voltage @ 125°C

LSCS Voltage Range

V_VCC

V_LSCS

V

T_J= 125°C

In active Mode

PFCVS Voltage Range

PFCCS Voltage Range

PFZCD Current Range

LVS1, LVS2 Voltage Range

LVS1, LVS2 Current Range

RFPH Frequency

RFPH Source Current Range

RTPH Voltage Range

Junction Temperature

Adjustable Preheating Freq.

Adjustable Run Frequency

Adjustable Preheating Time

Set Resistor for Run Feq.

Set Resistor for Preheat Feq.

Set Resistor for Preheat Time

Mains Frequency

V_PFCVS

V_PFCCS

I_PFCZCD

V_LVS1,LVS2

I_LVS1,LVS2

F_RFPHrange

I_RFPH

V_RTPH

T_j

F_RFPH

F_RFRUN

t_RTPH

R_RFRUN

R_RFPH

0

- 4

- 3

4

5

3

V

mA

V

In active Mode

- 6

6 ¹⁾

210

2.5

150

0

2)

µA

mA

kHz

µA

V

°C

kHz

ms

kꢀ

Hz

IC Power Down Mode

IC active Mode

- 2.5

F_RUN

- 500

0

- 25

F_RFRUN

20

@ V_RFPH= 2.5V

2.5

125

150

120

2500

25

Range set by RFPH

Range set by RFRUN

Range set by RTPH

0

4

0

—

25

65

R_RFRUNparallel to R_RFPH

R_RTPH

f_Mains

45

NOTCH Filter Operation

¹⁾Limited by Maximum of Current Range at LVS1, LVS2

²⁾Limited by Minimum of Voltage Range at LVS1, LVS2

Datasheet

Page 43 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Electrical Characteristics

5.3 Characteristics

5.3.1 Power Supply Section

Note: The electrical Characteristics involve the spread of values given within the specified supply voltage

and junction temperature range T_Jfrom -25 °C to 125 °C. Typical values represent the median

values, which are related to 25 °C. If not otherwise stated, a supply voltage of 15V and V_HSVCC= 15V

is assumed and the IC operates in active mode. Furthermore, all voltages are referring to GND if not

otherwise mentioned.

Limit Values

Parameter

Symbol

Unit

Test Condition

min.

—

typ. max.

VCC Quiescent Current1

VCC Quiescent Current2

VCC Supply Current ²⁾

I_VCCqu1

I_VCCqu2

I_VCCSupply

90

120

4.2

130

160

6.0

µA

mA

V

_VCC= V_VCCOff– 0.5V

_VCC= V_VCCOn– 0.5V

_PFCVS> 2.725V

—

VCC Supply Current in

I_VCCLatch

—

110

170

µA

V

_RES= 5V

Latched Fault Mode

LSVCC Turn-On Threshold

LSVCC Turn-Off Threshold

LSVCC Turn-On/Off Hyst.

V_VCCOn

V_VCCOff

V_VCCHys

V_VCCClamp

I_VCCZener

13.6

10.0

3.2

15.5

2.5

—

14.1

10.6

3.6

16.3

—

0.01

170

0.65

14.6

11.0

4.0

V

Hysteresis

I_VCC= 2mA/V_RES= 5V

_VCC= 17.5V/V_RES= 5V

_HSGND= 800V, V_GND=0V

_HSVCC= V_HSVCCOn– 0.5V

_HSVCC> V_HSVCCOn

VCC Zener Clamp Voltage

VCC Zener Clamp Current

High Side Leakage Current

HSVCC Quiescent Current

HSVCC Quiescent Current²⁾

HSVCC Turn-On Threshold

HSVCC Turn-Off Threshold

HSVCC Turn-On/Off Hyst.

16.9

V

5

2

250

1.2

mA

µA

mA

V

I_HSGNDleak

1)

I_HSVCCqu1

I_HSVCCqu2

—

1)

0.3

V_HSVCCOn

9.6

7.9

1.4

10.1

10.7

9.1

1)

V_HSVCCOff

8.4

1)

V_HSVCCHy

1.7

2.0

Hysteresis

Low Side Ground

GND

¹⁾Referring to High Side Ground (HSGND)

²⁾With inactive Gate

Datasheet

Page 44 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Electrical Characteristics

5.3.2 PFC Section

5.3.2.1

PFC Current Sense (PFCCS)

Limit Values

min. typ. max.

Parameter

Symbol

Unit

Test Condition

Turn – Off Threshold

V_PFCCSOff

t_PFCCSOff

0.95

1.0

1.05

V

Over Current Blanking +

140

200

260

ns

Propagation Delay ¹⁾

Pulse Width when

Leading Edge Blanking

t_Blanking

180

250

—

310

0.5

ns

V

_PFCCS> 1.0V

PFCCS Bias Current

I_PFCCSBias

- 0.5

µA

V_PFCCS= 1.5V

¹⁾Propagation Delay = 50ns

5.3.2.2

PFC Zero Current Detection (PFCZCD)

Limit Values

Parameter

Symbol

Unit

Test Condition

min.

1.4

0.4

typ. max.

Zero Crossing upper Thr. ¹⁾

Zero Crossing lower Thr. ²⁾

Zero Crossing Hysteresis

Clamping of pos. Voltages

Clamping of neg. Voltages

PFCZCD Bias Current

V_PFCZCDUp

V_PFCZCDLow

V_PFCZCDHys

V_PFCZCDpclp

V_PFCZCDnclp

I_PFCZCDBias

1.5

0.5

1.0

4.6

- 1.4

—

1.6

0.6

—

V

µA

ns

—

I_PFCZCDSink= 2mA

I_PFCZCDSource= - 2mA

4.1

5.1

- 1.0

5.0

0.5

650

- 1.7

- 0.5

350

V

_PFCZCD= 1.5V

_PFCZCD= 0.5V

PFCZCD Bias Current

—

PFCZCD Ringing Su.³⁾Time t_Ringsup

500

Limit Value for ON Time

_∆t x I_ZCD

500

700

900

pAxs

Extension

¹⁾Turn OFF Threshold

²⁾Turn ON Threshold

³⁾Ringing Suppression Time

5.3.2.3

PFC Bus Voltage Sense (PFCVS)

Limit Values

Parameter

Symbol

Unit

Test Condition

min.

2.47

2.68

2.57

70

Typ. max.

Trimmed Reference Voltage

Overvoltage turn Off (109%)

Overvoltage turn On (105%)

Overvoltage Hysteresis

Under voltage (75%)

Under voltage (12.5%)

Rated Bus Voltage (95%)

PFCVS Bias Current

V_PFCVSRef

V_PFCVSRUp

V_PFCVSLow

V_PFCVSHys

V_PFCVSUV

V_PFCVS95

I_PFCVSBias

2.50

2.73

2.63

100

1.88

0.31

2.38

—

2.53

2.78

2.68

130

V

mV

V

± 1.2 %

4 % rated Bus Voltage

1.835

0.237

2.325

- 1.0

1.915

0.387

2.425

1.0

V

µA

V_PFCVS= 2.5V

Datasheet

Page 45 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Electrical Characteristics

5.3.2.4

PFC PWM Generation

Limit Values

min. Typ. max.

Parameter

Symbol

Unit

Test Condition

_PFCZCD= 0V

0.45V < V_PFCVS< 2.45V

Initial ON – Time ¹⁾

Max. ON – Time ²⁾

t_{PFCON_initial}

t_{PFCON_max}

—

4.0

—

µs

V

18

22.7

26

Switch Threshold from

t_{PFCON_min}

160

270

370

ns

CritCM into DCM

Repetition Time ¹⁾

Off Time

t_PFCRep

t_PFCOff

47

42

52

47

57

52

µs

V_PFCZCD= 0V

¹⁾When missing Zero Crossing Signal

²⁾At the Maxima of the AC Line Input Voltage

5.3.2.5

PFC Gate Drive (PFCGD)

Limit Values

Typ. max.

Parameter

Symbol

Unit

Test Condition

min.

0.4

- 0.2

10.0

9.0

8.5

0.4

0.3

—

0.7

0.75

0.3

11.0

—

0.9

1.1

0.6

11.6

—

V

mA

I

_PFCGD= 5mA

_PFCGD= 20mA

PFCGD Low Voltage

PFCGD High Voltage

V_PFCGDLow

_PFCGD= -20mA

_PFCGD= -1mA / V_VCC

_PFCGD= -5mA / V_VCC

1)

V_PFCGDHigh

—

PFCGD active Shut Down

PFCGD UVLO Shut Down

PFCGD Peak Source Current

PFCGD Peak Sink Current

V_PFCGASD

V_PFCGDuvlo

I_PFCGDSouce

I_PFCGDSink

0.75

1.0

- 100

500

1.1

1.5

—

_PFCGD= 20mA V_VCC=5V

_PFCGD= 5mA V_VCC=2V

2) + 3)

—

PFCGD Voltage during sink

V_PFCGDHigh

11.0

11.7

12.3

V

I_PFCGDSinkH= 3mA

Current

PFC Rise Time

PFC Fall Time

V_PFCGDRise

V_PFCGDFall

80

20

220

45

380

70

ns

2V > VLSGD > 8V ²⁾

8V > VLSGD > 2V ²⁾

1)

V

= V_VCCOff+ 0.3V

VCC

2)

R

Load

= 4ꢀ and C_Load= 3.3nF

³⁾The Parameter is not Subject to Production Test – verified by Design / Characterization

5.3.2.6

Auxiliary (AUX)

Limit Values

min. typ. max.

Parameter

Symbol

Unit

Test Condition

AUX Voltage OFF Level

AUX Voltage ON Level 1

AUX Voltage ON Level 2

AUX Current

V_AUXOff

V_AUXOn1

V_AUXOn2

I_AUX

—

1.7

1.8

—

2.6

0.24

3.1

V

I_AUX= 1mA

I_p= 0A ¹⁾

I_p= 1mA ¹⁾

V_AUX= 1V / I_P= 0A

- 0.60 -0.45 - 0.3

mA

¹⁾I_P= the positive Current into PIN ZCD

Datasheet

Page 46 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Electrical Characteristics

5.3.3 Inverter Section

5.3.3.1

Low Side Current Sense (LSCS)

Limit Values

min. typ. max.

Parameter

Symbol

Unit

Test Condition

1)

2)

Overcurrent Shut Down Volt.

Duration of Overcurrent

Capacitive Mode Det. Level 1

Capacitive Mode Duration 1

Capacitive Mode Det. Level 2

Capacitive Mode Duration 2

Capacitive Mode Det. Level 3

Capacitive Mode Duration 3

LSCS Bias Current

V_LSCSOvC1

V_LSCSOvC2

t_LSCSOvC

V_LSCSCap1

t_LSCSCap1

V_LSCSCap2

t_LSCSCap2

V_LSCSCap3

t_LSCSCap3

I_LSCSBias

1.5

0.75

450

80

—

1.8

—

1.6

0.8

600

100

280

2.0

1.7

0.85

700

123

—

V

ns

mV

ns

V

ns

mV

ns

µA

During Run Mode

3)

2.2

—

During Run Mode

4)

50

- 120

—

-1.0

- 100

280

—

- 77

—

1.0

5)

@ V_LSCS= 1.5V

¹⁾Overcurrent Voltage Threshold active during: Start Up, Soft start, Ignition and Pre Run Mode

²⁾Overcurrent Voltage Threshold active during: Preheating and Run Mode

³⁾Active during 2^nd50% Duty Cycle of LSGD in Run Mode

⁴⁾Active during Turn ON of the HSGD in Run Mode

⁵⁾Active before Turn ON of the HSGD in Run Mode

Datasheet

Page 47 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Electrical Characteristics

5.3.3.2

Low Side Gate Drive (LSGD)

Limit Values

min. typ. max.

Parameter

Symbol

Unit

Test Condition

0.4

- 0.3

10.0

9.0

8.5

0.4

0.3

—

0.7

0.8

0.2

10.8

—

1.0

1.2

0.5

11.6

—

V

mA

V

ns

I

_LSGD= 5mA⁵⁾

LSGD Low Voltage

LSGD High Voltage

V_LSGDLow

_LSGD= 20mA⁵⁾

_LSGD= - 20mA (Source)

1)

2)

3)

V_LSGDHigh

—

LSGD active Shut Down

LSGD UVLO Shut Down

LSGD Peak Source Current

LSGD Peak Sink Current

LSGD Voltage during ⁵⁾

LSGD Rise Time

V_LSGDASD

V_LSGDUVLO

I_LSGDSource

I_LSGDSink

V_LSGDHigh

t_LSGDRise

t_LSGDFall

0.75

1.0

- 50

300

11.7

220

35

1.1

1.5

—

V_CC=5V / I_LSGD= 20mA⁵⁾

V_CC=2V / I_LSGD= 5mA⁵⁾

4) + 6)

—

I_LSGDsinkH= 3mA

2V < V_LSGD< 8V⁴⁾

8V > V_LSGD> 2V⁴⁾

80

20

380

60

LSGD Fall Time

¹⁾I_LSGD= - 20mA Source Current

²⁾V_CCOFF+ 0.3V and I_LSGD= - 1mA Source Current

³⁾V_CCOFF+ 0.3V and I_LSGD= - 5mA Source Current

⁴⁾Load: R_Load= 10ꢀ and C_Load= 1nF

⁵⁾Sink Current

⁶⁾The Parameter is not Subject to Production Test – verified by Design / Characterization

Datasheet

Page 48 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Electrical Characteristics

5.3.3.3

Inverter Control Run (RFRUN)

Limit Values

min. typ. max.

Parameter

Symbol

Unit

Test Condition

Fixed Start – Up Frequency

Duration of Soft Start

RFRUN Voltage in Run Mode

Run Frequency

F_StartUp

t_SoftStart

V_RFRUN

F_RFRUN

F_RFRUN1

F_RFRUN2

F_RFRUN3

I_RFRUNmax

121.5

9

—

49

—

135

11

2.5

50

20

40

148.5

13.5

—

51

—

kHz

ms

V

1)

@ 100µA<I_RFRUN<600µA

kHz R_RFRUN= 10kꢀ

kHz _RFRUN= - 100 µA

kHz I_RFRUN= - 200 µA

kHz I_RFRUN= - 500 µA

I

Adjustable Run Frequency

—

100

RFRUN max. Current Range

-1000 - 650

µA

@ V_RFRUN= 0V

¹⁾Shift Start Up Frequency to Preheating Frequency

5.3.3.4

Inverter Control Preheating (RFPH, RTPH)

Limit Values

Parameter

Symbol

Unit

Test Condition

_RFPH= 0V in Run Mode

min.

—

typ. max.

2.5

RFPH Voltage Preheating

Preheating Frequency

RFPH max. Current Range

Current for set Preh. Time

V_RFPH

F_RFPH1

I_RFPHmax

I_RTPH

t_RTPH1

t_RTPH2

t_RTPH3

t_RTPH4

t_RTPH5

—

103

V

97

—

100

kHz

µA

ms

R

_RFPH= R_RFRUN= 10kꢀ

-1000 - 550

- 100

1000 1050

100

500

@ V_RFPH= 0V

—

950

50

—

R_RTPH1= 10kꢀ

150

—

R

_RTPH2= 1kꢀ

R_RTPH3= 5kꢀ

_RTPH4= 20kꢀ

R_RTPH5= 25kꢀ

Preheating Time

—

2000

2500

R

—

Datasheet

Page 49 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Electrical Characteristics

5.3.3.5

Restart after Lamp Removal (RES)

Limit Values

min. typ. max.

Parameter

Symbol

Unit

Test Condition

V_RES1

V_RES2

V_RES3

1.55

1.25

—

1.60

1.30

3.2

1.65

1.35

—

V

UVLO, V_CC< V_CCON

High Side Filament In Det.

RES Current Source

Run Mode

V_RES= 1V ;

I_RES1

I_RES2

I_RES3

I_RES4

- 53.2

-44.2

- 26.6

-42.6 -32.0

-35.4 -26.6

-21.3 - 16.0

µA

LVS1 = 5µA

V

_RES= 2V ;

LVS1 = 5µA

V_RES= 1V ;

LVS1 = 30µA

V

_RES= 2V ;

- 22.1 -17.7 -13.3

LVS1 = 30µA

5.3.3.6

Lamp Voltage Sense (LVS1, LVS2)

Limit Values

Parameter

Symbol

Unit

Test Condition

_LVS= 0V

min.

- 5.0

350

8.0

typ. max.

Source Current before Startup

Enable Lamp Monitoring

Sink Current for Lamp Det.

Positive Clamping Voltage

AC EOLCurrent Threshold

Positive EOL Current Thr.

Negative EOL Current Thr.

I_LVSSource

V_LVSEnable1

I_LVSSink

V_LVSClamp

I_LVSSourceAC

I_LVSDCPos

I_LVSDCNeg

- 3.0

530

12.0

6.5

- 2.0

750

18.0

—

µA

mV

µA

V

1)

V_LVS> V_LVSClamp

—

@ I_LVS= 300µA

190

34

210

42

230

50

- 34

µApp I_LVS> I_LVSEOLppEOL 1

µA

I_LVS> I_LVSDCPosEOL 2

I_LVS> I_LVSDCNegEOL 2

- 50

- 42

¹⁾If V_LVS< V_LVS1Enable1Monitoring is disabled

Datasheet

Page 50 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

5.3.3.7

High Side Gate Drive (HSGD)

Limit Values

Min. typ. max.

Parameter

Symbol

Unit

Test Condition

0.02

0.5

- 0.4

0.05

1.1

- 0.2 - 0.05

0.1

2.5

V

I

_HSGD= 5mA (sink)

_HSGD= 100mA (sink)

_LSGD= - 20mA (source)

V

HSGD Low Voltage

V_HSGDLow

_CCHS=15V

_HSGD= - 20mA (source)

_CCHSOFF+ 0.3V

_HSGD= - 1mA (source)

_CCHS=5V

9.7

7.8

10.5

—

11.2

—

V

I

HSGD High Voltage

V_HSGDHigh

V

I

V

HSGD active Shut Down

V_HSGDASD

I_HSGDSource

I_HSGDSink

T_HSGDRise

T_HSGDFall

0.05

0.22

0.5

I

_HSGD= 20mA (sink)

R

_Load= 10ꢀ+C_Load= 1nF ¹⁾

HSGD Peak Source Current

HSGD Peak Sink Current

—

- 50

300

—

mA

R

2V < V_LSGD< 8V

_Load= 10ꢀ+C_Load= 1nF

8V > V_LSGD> 2V

_Load= 10ꢀ+C_Load= 1nF

HSGD Rise Time

HSGD Fall Time

140

20

220

35

300

70

ns

R

¹⁾The Parameter is not Subject to Production Test – verified by Design / Characterization

5.3.3.8

Timer Section

For Lamp Detection

For V_BUS> 95%

Delay Timer 1

t_TIMER1

70

100

160

ms

Delay Timer 2

Inverter Time

t_TIMER2

t_Inv

74

100

84

130

94

160

ms

µs

Inverter Dead Time Max

Inverter Dead Time Min

∆ Inverter Dead Time Max

∆ Inverter Dead Time Min

t_DeadMax

t_DeadMin

t_DeadMax

t_DeadMin

2.25

1.0

- 200

2.5

1.25

—

2.75

1.5

200

µs

ns

—

Min. Duration of Ignition

Max. Duration of Ignition

Duration of Pre – Run

t_Ignition

t_NOIgnition

t_PRERUN

34

197

565

40

—

625

48

236

685

ms

5.3.3.9

Built in Customer Test Mode

Preheating Time = 0ms (Skipped Preheating)

Voltage at RTPH Pin

V_RTPH

0

V

V ¹⁾

V

Voltage at RTPH Pin

Voltage at LVS1 / LVS2 Pin

V_RTPH

V_LVS1,2

5.0

0

IC remains in Preheating

Disables Lamp Voltage Sense

Voltage at RES Pin

Voltage at RFPH Pin

Voltage at RFRUN Pin

Voltage at V_CCPin

Voltage at RES Pin

V_RES

V_RFPH

V_RFRUN

V_CC

0

5.0

> 14.1

0

V

V ¹⁾

V

Disable the Filament Detection

Built in Customer Test Mode - Clock

Acceleration. Decreasing Time for the

following Procedures.

Preheating by Factor 4

Timeout Ignition by Factor 2

Pre RUN by Factor 15

V_RES

V

EOL by 60

1) Tolerance for this voltage is: ± 5%

Datasheet

Page 51 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Application Example

6

Application Example

6.1 Schematic Ballast 54W T5 Single Lamp

Figure 40: Application Circuit of Ballast for single Fluorescent Lamp Voltage Mode Preheating

Datasheet

Page 52 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Application Example

6.2 Bill of Material

090402-1-L-54W-T5-FL2-VM

BOM

Gen-2

54W T5, single Lamp, Voltage Mode Preheat

Input Voltage 180VAC...270V AC

ICB2FL01G

V_BUS= 412V

Package

F1

Fuse 1A fast

Fuse Holder

AC Input

Wickmann

Typ 370

R1

R2

470kꢀ

not assembled

.1206

K1/1

K1/2

K1/3

K2/1

K2/2

K2/3

K3/1

K3/2

K3/3

IC1

R3

B-Nr: 250-203

AC Input

R4

R402

R403

PE

not connected

High Side Filament

Low Side Filament

not connected

ICB2FL01G

SPD03N60C3

not assembled

S1M

R11

R12

R13

R14

R15

R16

R18

R19

R20

R21

R22

R23

R24

R25

R26

R27

R30

R34

R35

R36

R36A

R61

470kꢀ

.1206

.0805

.1206

.0805

.1206

.0805

.1206

B-Nr: 250-203

>GE834

33kꢀ

820kꢀ

Infineon

Fairchild

ON Semi

Philips

SO-20

D-Pack

SOT-223

DO-214AC

SMB

SOD124

DO214

SOD110

820kꢀ

Q1

22ꢀ

1ꢀ

Q2

Q3

not assembled

10kꢀ

11kꢀ (45,5kHz!)

8,2kꢀ (106,4kHz!)

10kꢀ (1000ms!)

0,68ꢀ

Q4

D1…4

D5

(1000V/1A/2µs)

(600V/1A/75ns)

(600V/1A/30ns)

(200V/1A/25ns)

MURS160T3

BYG26J

BYG22D

BZX284C16

not assembled

110kꢀ

not assembled

2x68mH/0,6A

1,58mH

D6

D7

Philips

D8

Philips

0,68ꢀ (Σ 0,34ꢀ)

22ꢀ

D9

D10

D11

DR12

D13

D61

L101

L1 PFC

22ꢀ

33ꢀ

150kꢀ

Philips

Epcos

2 pcs

Epcos

2 pcs

Epcos

SOD110

56kꢀ

B82732F2601B001

0ꢀ

105turns/10turns EFD25/13/9

total gap= 1.1mm

1,46mH

B78326P7373A005

182turns

T1904

EFD25/13/9

T1905

RM5

RM15

RM10

RM10/15

RM15

RM5

connect LVS2 (pin14) to GND

L 2

total gap= 2mm

100µH

B78326P7374A005

B82144B1104J000

B32922C3224M000

B32521N8333K000

B32021A3332

L 21

L 22

L 23

C1

R41

R42

R43

R44

R45

68kꢀ

6,8kꢀ

.1206

100µH

not assembled

220nF/X2/305V

33nF/630V/MKT

3,3nF/Y2-RM10

220nF/X2/305V

not assembled

10µF/450V

C2

C3

C4

B32922C3224M000

B32529C8102K000

C5

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C40

B43888A5106M000 single ended

2,2nF/50V

100nF/50V

.0805

RM5

.0805

RM10

RM5

RM15

RM7,5

.0805

RM15

1µF/63V/MKT

68nF/50V

33nF/630V/MKT

1nF/630V/MKT

100nF/630V

not assembled

22nF/50V

4,7nF/1600V/MKP

22nF/400V/MKT

not assembled

220nF/25V

Epcos

B32529C0105K000

B32521N8333K000

B32529C8102K000

B32612A6104K008

R61

0ꢀ

.0805

EOL1 threshold

167Vpeak x 1.5=250V peak

5W

Epcos

B32612-J1472J008

B32620A4223J000 RM7,5/10

Epcos

B32612-J1472J008

RM15

RM7,5

.0805

Roederstein

Datasheet

Page 53 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Application Example

6.3 Multi Lamp Ballast Topologies

Figure 41: Parallel 2 Lamp Ballast Circuit with Current Mode Preheating

Figure 42: Serial 2 Lamp Ballast Circuit with Voltage Mode Preheating

Datasheet

Page 54 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Figure 43: 4 Lamp Ballast Circuit with Voltage Mode Preheating

Datasheet

Page 55 of 56

ICB2FL01G

V1.2

2^ndGeneration FL-Controller for FL-Ballasts

Application Example

7

Package Outlines

Figure 44: Package Outline with Creepage Distance

Datasheet

Page 56 of 56

ICB2FL01G

V1.2


型号：	ICB2FL01GXUMA2
厂家：	Infineon
描述：	Power Supply Support Circuit, Adjustable, 1 Channel, PDSO19, 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOP-20/19 光电二极管
文件：	总56页 (文件大小：998K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICB2FL01GXUMA2 [INFINEON]

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