ICE1QS01 [INFINEON]

Controller for Switch Mode Power Supplies Supporting Low Power Standby and Power Factor Correction (PFC); 控制器的开关电源支持低功耗待机和功率因数校正（ PFC ）


型号：	ICE1QS01
厂家：	Infineon
描述：	Controller for Switch Mode Power Supplies Supporting Low Power Standby and Power Factor Correction (PFC) 控制器的开关电源支持低功耗待机和功率因数校正（ PFC ）稳压器开关式稳压器或控制器电源电路开关式控制器功率因数校正光电二极管
文件：	总21页 (文件大小：479K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Datasheet, V1.4, 27 April 2004

ICE 1QS01

Controller for Quasiresonant

Switch Mode Power Supplies

Supporting Low Power Standby

and Power Factor Correction

Power Management & Supply

N e v e r s t o p t h i n k i n g .

ICE1QS01

Revision

History: Current

Version: 2004-

04-27

Version: 2003-

11-28

Page13 (in

Page 13 (in

Diagram mains undervoltage lockout curent added

previous version) current version)

Page 16-18 (in Page 16-18 (in Min.- max.- values added, typ. values adapted, according to measuring results.

previous version) current version)

Page 20 (in Page 20 (in

Application circuit changed to new 250 W demo board with PFC current pump.

previous version) current version)

Edition 2004-04-27

Published by Infineon Technologies AG,

St.-Martin-Strasse 53,

D-81541 München

Attention please!

The information herein is given to describe certain components and shall not be considered as warranted char-

acteristics.

Terms of delivery and rights to technical change reserved.

We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding

circuits, descriptions and charts stated herein.

Infineon Technologies is an approved CECC manufacturer.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest In-

fineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address

list).

Warnings

Due to technical requirements components may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies Office.

Infineon Technologies Components may only be used in life-support devices or systems with the express written

approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the fail-

ure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life sup-

port devices or systems are intended to be implanted in the human body, or to support and/or maintain and sus-

tain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons

ICE1QS01

Controller for Switch Mode Power Supplies

Supporting Low Power Standby and

Power Factor Correction (PFC)

P-DIP-8-4

Features

• Quasiresonant Operation

• Primary and Secondary Regulation

• Primary Current Simulation

• Standby Input Power < 1 W

• Low Power Consumption

P-DSO-8-3

• Very Low Start-up Current

• Soft-Start for noiseless Start-up

• Standby Burst Mode with and without Control Signal for lowered Output

Voltages

P-DSO-8-3

• Digital Frequency Reduction in small Steps at Decreasing Load

• Over- and Undervoltage Lockout

• Switch Off at Mains Undervoltage

• Mains Voltage Dependent Fold Back Point Correction

• Ringing Suppression Time Controlled from Output Voltage

• Free usable Fault Comparator

Functional Description

The ICE1QS01 is optimized to control free running flyback converters with and without Power Factor Correction

(with PFC Charge Pump).

The switching frequency is reduced in small steps with decreasing load towards a minimum of 20 kHz in

standby mode. This function is performed by a digital circuit to avoid any jitter also with periodically pulsed

loads. To provide extremely low power consumption at light loads, this device can be switched into Standby

Burst Mode. This is also possible without standby control signal (for adapter application).

Additionally, the start up current is very low. To avoid switching stresses of the power devices, the power

transistor is always switched on at minimum voltage. The device has several protection functions: V_CCover-

and undervoltage, mains undervoltage and current limiting. Regulation can be done by using the internal error

amplifier or an opto coupler feedback. The output driver is ideally suited for driving a power MOSFET.

The ICE1QS01 is suited for TV-sets, DVD- sets, SAT- receivers and other consumer applications in the power

range from 0 to app. 300 W.

Type

ICE1QS01

ICE1QS01G

Ordering Code

Q67040-S4558

Q67040-S4559

Package

P-DIP-8

P-DSO-8

Version 1.4

27 Apr 2004

ICE1QS01

Block Diagram

VCC

Overvoltage

Protection

20V

Foldback

Point Corr.

UVLO

PCS

Burst-Mode

1.5V

Reference

Voltage and

Current

SRC

Ringing

4.8V

4.5V

3.5V

Suppression

Time

20k

Start

50µs Timer

50ms Timer

Latch

Primary

50mV

Regulation

Digital Processing

RZI

ZC-Counter

UP/DO-Counter

5.7V

Power

Driver

S ^SET

OUT

CLR

OFC

SET

CLR

GND

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ICE1QS01

Pinning

Symbol

Function

N.C.

PCS

RZI

SRC

OFC

GND

OUT

VCC

Primary Current Simulation

Regulation and Zero Crossing Input

Soft-Start and Regulation Capacitor

Overvoltage Fault Comparator

Ground

Output

Supply Voltage

Pin Configuration (top view)

N.C.

PCS

RZI

VCC

OUT

GND

OFC

OUT

GND

OFC

PCS

RZI

SRC

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ICE1QS01

Functional Description

Start up

An internal start up diode is connected between pin PCS and pin V . Start up current is provided

via this diode if V

is higher than V + V (V = Base-Emitter-Voltage).

PCS

CC BE BE

During start up the internal reference of the IC is shut off and current consumption is about 60 µA.

There is only the start up circuitry working which determines the V

threshold. Gate driver OUT

CCon

is switched to low. An active shut down circuitry ensures that OUT is held below the MOS gate

threshold when the IC is in start up mode.

Block Diagram: Start Up

VCC

PCS

UVLO

OUT

ICE1QS01

Version 1.4

27 Apr 2004

ICE1QS01

Soft start

The internal reference of the IC is switched on when V

exceeds the V

threshold. The IC

CCon

begins to work with soft start mode. Soft start is realized with an internal soft start resistor, an inter-

nal current sink, a current source and the external feedback capacitor connected at pin SRC. The

internal resistor is connected between the internal voltage reference and pin SRC. The current sink

is connected between pin SRC and GND. The value of the current is set with a timer. Immediately

after the IC is switched on the capacitor C

is charged with a current source up to 2.5V. This cur-

SRC

rent source is switched off 12 µsec after beginning of soft start. The current value of the current sink

is set with a timer. Every three msec the current of the current sink is reduced and so V

can

SRC

increase stepwise. The soft start is finished 24 msec after the IC is switched on. At the end of the

soft start the current sink is switched off.

Figure: Soft Start

2.5V

VCC

ICE1QS01

500

timer

t=12us

VCCon

20k

timer

tp=3ms

timer

t=24ms

current

sink

down

D/A

counter

VSRC

pin SRC

VSRC2

VSRC1

ton

tp1

tp2

PCS (primary current simulation)

A voltage proportional to the current of the power transistor is generated at Pin PCS by the RC-com-

bination R2, C2. The voltage at Pin PCS is forced to 1.5V when the power transistor is switched off

and during its switch on time C2 is charged by R2 from the rectified mains. The relation of V

and

PCS

Version 1.4

27 Apr 2004

ICE1QS01

the current in the power transistor (Iprimary) is:

Lprimary × Iprimary

VPCS = 1, 5V + -------------------------------------------------------

R2 × C2

Lprimary: Primary inductance of the transformer

The advantage of primary current simulation is the elimination of the leading edge spike, which is

generated when the power transistor is switched on.

RZI (zero crossing input and primary regulation)

Zero current counter

Every time when the falling voltage ramp of V

crosses the 50 mV threshold a pulse is sent to the

RZI

zero-current-counter and increases the counter by one. If zero-current-counter and up-down-coun-

ter are equal the gate drive OUT is switched to high. Up-down counter is influenced via SRC voltage

as described below. If V

is greater than 50 mV gate drive OUT is always switched low.

RZI

Figure: Zero Crossing Switching Behaviour

VSRC

VPCS

1.5V

VRZI

status up-down

counter = 0010:

switch on at second

zero crossing

status up-down

counter = 0001:

switchonat first

OUT

zerocrossing

ton toff

ton

toff

Version 1.4

27 Apr 2004

ICE1QS01

Ringing suppression

When V reaches the feedback voltage V

the gate drive OUT is set to low and the ringing

SRC

PCS

suppression timer is started. This timer ensures that the gate drive cannot be switched on until this

ringing suppression time is passed. Duration of ringing suppression time depends on the V

volt-

RZI

age. Suppression time is 3 µsec if V

> 1V and it is 30 µsec if V

< 1V.

RZI

Figure: Ringing Suppression

up-down-counter

VRZI

VSRC

VPCS

1.5V

OUT

ringing

suppression

time

3 µs

30 us

Version 1.4

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ICE1QS01

Primary regulation

Primary regulation is achieved by activating the internal current sink. The current sink is connected

between pin SRC and ground. If V exceeds the 5V threshold the current sink is switched on. It is

RZI

switched off when V

falls below 5V. The current sink discharges the C

capacitor. C

SRC

RZI

SRC

charged via the internal 20k resistor. If V

exceeds the 4.4V threshold a flip-flop is set and the

RZI

resistor is switched off when V

ing slope of gate drive OUT.

falls below 50 mV. The resistor is switched on again with the fall-

RZI

Diagram Primary Regulation

zero current counter = 0010

VRZI

4.5V

OUT

20K

start R Q

stop S Q

R Q

S Q

0.05 V

20k

resistor

R Q

S Q

SRC

4.5 V

RZI

off

5 V

current

sink

current

sink

ICE1QS01

off

VSRC

Version 1.4

27 Apr 2004

ICE1QS01

SRC (Regulation and soft start capacitor)

The feedback capacitor is connected to pin SRC. The feedback voltage V

has two main func-

SRC

tions.

Function I (MOS FET on time): V

provides the switch off reference voltage. If V

(which con-

PCS

SRC

tains the primary current information) exceeds the V

switched off.

voltage the external MOS transistor is

SRC

Function II (MOS FET off time for frequency reduction): At low load the frequency is reduced by

ignoring zero crossing signals after the transformer demagnetization. V determines the action of

SRC

the 4-bit up-down-counter which contains the number of zero crossings to be ignored. The content

of the up-down-counter is compared with the number of zero-current crossings of V If the

RZI.

number of zero-current crossings in each period after the transformer demagnetization is equal to

the up-down-counter content the MOS is switched on. At low load conditions when V is below

SRC

3.5V the counter is increased by one every 50 msec. The result is that the MOS transistor off-time

increases and duty cycle decreases. At high load conditions when V

is higher than 4.4V the

SRC

counter content is reduced by one every 50msec. So MOS transistor off-time will be reduced. With

this off-time regulation switching jitter can be eliminated.

The up-down-counter is immediately set to 0001 if a load jump occurs and V

This ensures that full power can be provided instantaneously.

exceeds 4.8 V.

SRC

The following table shows the SRC voltage range and the corresponding up-down counter action.

SRC voltage range

1: VSRC< 3.5V

2: 3.5<VSRC<4.4

3: VSRC>4.4

up-down-counter action

count forward

stop count

count backward

4: VSRC> 4.8

set up-down-counter to1

The information provided by V

is stored in two independent flip flops. An internal timer creates a

SRC

trigger pulse with a period of 50 msec. Every time the pulse occures the up-down counter checks

the status flip flops and acts depending on the flip flop information. After this pulse the flip flops are

reset. So change of voltage range is noticed by the logic only once during the 50 ms period. In the

diagram below the behaviour of the up-down counter is depicted in more detail.

D iagram 1

tim er pulse tp

50 m sec

V S R C

4.5 V

3.5 V

status of

up-dow n

counter

n + 1

n - 1

n - 2

n - 3

Version 1.4

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ICE1QS01

Burst mode

12 µsec after beginning of softstart the burst mode comparator is activated. If V

falls below 2V

CCoff

SRC

after activating the comparator the gate drive OUT is switched to low and the V

threshold is

changed to 14.5 V. V decreases because gate drive is held low. If V reaches the V thresh-

CCoff

old the IC is going into start-up mode. At V

threshold the IC is switched on again starting with

CCon

soft start modus. V

threshold is set to the normal 9V.

CCoff

Figure: Burst Mode

Secondary

load

high

low

V_SRC

OUT

Vcc

15V

14.5V

VCCOFF

Vsec

normal mode

burst mode

soft start

Version 1.4

27 Apr 2004

ICE1QS01

Restart timer

If voltage V

is lower than 50 mV and gate drive OUT is low an internally created restart pulse will

RZI

switch gate drive OUT high every 50 µs and the minimum switching frequency is about 20 kHz.

Restart pulse is inhibited if V

is higher than 50 mV. So the MOS transistor cannot be switched on

RZI

until the transformer is discharged.

VCC overvoltage protection

If V

exceeds the V

threshold a latch is set and the gate is disabled. Reset of latch occurs

CCD

when V is falling below V

- V

CCBHY.

CCon

Overvoltage fault comparator (OFC)

With an external sense resistor connected to pin OFC primary current can be sensed directly. If the

sensed current exceeds the internal V

threshold a latch is set and gate is disabled. Reset of

CCon

OFC

latch occurs when V is falling below V

- V

CCBHY

Notice: If this comparator is not used pin OFC has to be connected to ground.

Mains undervoltage

Power supplies must be shut down when mains voltage is below a certain limit to avoid too long on-

time of MOS-FET switch, which would lead to a switching frequency in audible spheres. Mains und-

ervoltage is sensed during the off-time of the MOS-FET switch. If the current flowing into pin PCS is

smaller than 100 uA, then the output is latched and cannot be switched to high state.

Diagram Mains Undervoltage Lockout Current

130

120

Ipcs/µA

110

100

-40 -30 -20 -10

90 100 110 120 130 140 150

Temp./°C

Version 1.4

27 Apr 2004

ICE1QS01

Fold back point correction

With increasing mains voltage the switch on time becomes shorter and so the frequency becomes

higher. With higher frequency also the maximal possible output power becomes higher. With higher

power the danger in case of failure increases.

To avoid this, the foldback point correction circuit senses main voltage to reduce the on-time of the

switch. Mains voltage is sensed at the supply coil of V voltage via a resistor connected to pin RZI.

During on-time of the MOS-FET switch current is pulled out from pin RZI. When this current is

higher than 500 µA, one fifth of the current higher than this threshold is driven into pin PCS to

increase the voltage slope charging the capacitor connected to this pin.

IRZI – 0, 5mA

--------------------------------

IPCSFO =

,(IRZI > 500uA)

Figure: Fold Back Point Correction

Vpcs with fold back point correction

Vpcs at high mains voltage

Pmax without fold back point correction

Vpcs

Pmax

Vpcs at low mains

voltage

Pmax with fold back point correction

Vmains

Version 1.4

27 Apr 2004

ICE1QS01

Absolute Maximum Ratings

Parameter

Symbol Min

Max

Unit Remark

Charge Current into Pin2

Voltage at Pin 2

500

During start up

PCS

-0.3

PCS

Current into Pin 3

RZI RZICH

RZI

-10

RZI RZICL

=100 µA

Voltage at Pin 4

Voltage at Pin 5

Current into Pin 7

Voltage at Pin 8

-0.3

-500

-0.3

SRC

OFC

OUT

SRCCL

500

t<1ms

ESD Protection

4000

MIL STD 883C method

3015.6, 100pF,1500Ω

Storage Temperature

-50

-25

150

°C

stg

Operating Junction Temper-

ature

Thermal Resistance

Junction-Ambient

100

K/W

P-DIP-8

thJA

Version 1.4

27 Apr 2004

ICE1QS01

Characteristics (Unless otherwise stated, -25°C<Tj <150 °C, VCC = 16V)

Parameter

Symbol min. typ.

max. Unit Test Condition

VCC start-up circuit

Start-up supply current

Operating supply current

100

12.5

15.5

9.5

µA

-0.5V

CCL

CC CCon

Output low

CCH

Turn-On threshold

Turn-Off threshold

Hysteresis

14.1

8.5

5.4

0.2

CC ON

CC OFF

CCHY

CCBHY

CCD

6.5

Burst Hysteresis

Overvoltage

0.4

0.6

SRC soft start mode

Start Voltage

2.40

2.65

360

2.85

=0 µA

SRC1

SRCST

SRCSTR

optocoupler

Digital voltage step

Step pulse rate

µs

optocoupler

Soft start time

Current source rise time

=0.2V to 2.0V

=10nF

STRT

SRC

Current source on time

SRC normal mode

Source resistor

µs

STOT

kOhm

SRC

Clamping threshold volt-

age

4.95

5.1

5.25

PCS SRC

, OUT switches

=100µA

SRCCL

to Low, I

SRC

Reset counter to one

4.75

150

4.3

4.9

200

4.5

5.05

250

4.7

SRCR

SRCH

SRCD

Distance clamping to reset

Threshold downward

count

Threshold upward count

3.4

1.9

3.5

3.7

2.2

SRCSU

SRCB

Burst mode latch threshold

voltage

2.05

: OUT=Low

SRCB

SRC

Counter time

msec

µA

COUNT

Sink current prim reg

mode

400

500

550

> 5V

RZI

SRCS

1) The parameter is not subject to production test - verified by design/characterization

Version 1.4

27 Apr 2004

ICE1QS01

Parameter

Symbol min. typ.

max. Unit Test Condition

RZI (regulation and zero crossing input)

Zero crossing threshold

voltage

: Out=High

RZIT1

RZI RZIT1

Time delay switch on

Leakage current

350

-1

440

550

110

-0.2

nsec

µA

don

=5V

RZIB

RZI

Clamping voltage low

state

-0.5

-0.3

= -1mA

RZICL

RZICH

RZIDC

RZICC

RZIT2

RZI

Clamping voltage high

state

5.5

6.0

5.1

4.4

1.0

6.4

= 5mA

RZI

Primary regulation thresh-

old for discharge current

4.95

4.2

5.25

4.65

1.1

Primary regulation thresh-

old for charge current

Ringing suppression

threshold voltage

0.9

Ringing suppression time

1.5

2.5

3.2

µsec

> V

< V

RZIPS

RZIPL

RZI

RZIT2

Foldback point correction

current threshold

250

400

600

µA

-25°C<Tj<120°C

PCSF

PCS (primary current simulation)

Gate enable threshold

voltage

0.9

1.0

1.1

: Out=Low

PCSE

PCS PCSE

Basic voltage

1.45

1.55

150

100

1.65

230

160

gate low

PCSB

PCS

Shut down delay

nsec

µA

Mains undervoltage lock-

out current 2)

PCS

Voltage drop startup diode

Discharge current

0.85

2.6

=300µA

PCS

PCSD

1.6

3.6

=3V

PCS

PCSD

OFC (overcurrent fault comparator)

Bias Current

-1

µA

OFCB

Gate drive disabled

threshold voltage

0.93

1.0

1.05

240

OFC

Shut Down Delay

180

OFC

2) See diagram mains

undervolt. lockout current

Version 1.4

27 Apr 2004

ICE1QS01

Parameter

Symbol min. typ.

max. Unit Test Condition

Restart Timer

Restart time

µs

<25mV

RES

RZI

Gate Drive

Output voltage low

0.7

0.8

1.1

1.4

=20mA

OUT

=200mA

Output voltage high

9.5

10.6

10.5

11.0

=-20mA

OUT

=-180mA

Output voltage active shut

down

1.0

1.35

OUT

=7V

=20mA

Rise time

Fall time

100

120

=1nF

OUT

Version 1.4

27 Apr 2004

ICE1QS01

Figure: Circuit Diagram for Standard Application with PFC

Version 1.4

27 Apr 2004

ICE1QS01

Figure: Circuit Diagram for Application with PFC and Low Voltage Standby Mode

Version 1.4

27 Apr 2004

ICE1QS01

Plastic Package, P-DSO-8-3

(Plastic Dual Small Outline Package)

Plastic Package, P-DIP-8-4

(Plastic Dual In-line Package)

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our

Data Book “Package Information”.

Dimensions in mm

SMD = Surface Mounted Device

Version 1.4

27 Apr 2004

ICE1QS01 [INFINEON]

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