ICE2PCS05G_技术文档

Version 1.0, 09 Oct 2008

CCM-PFC

ICE2PCS05

ICE2PCS05G

Standalone Power Factor

Correction (PFC) Controller in

Continuous Conduction Mode

(CCM)

Power Management & Supply

N e v e r s t o p t h i n k i n g .

CCM-PFC

Revision History:

Datasheet

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Subjects (major changes since last revision)

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CoolMOST™, CoolSET™ are trademarks of Infineon Technologies AG.

Edition 2008-10-09

Published by

Infineon Technologies AG

81726 München, Germany

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The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties

and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights

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For further information on technology, delivery terms and conditions and prices please contact your nearest

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be endangered.

CCM-PFC

ICE2PCS05

ICE2PCS05G

Standalone Power Factor Correction

(PFC) Controller in Continuous

ICE2PCS05

PG-DIP-8

Conduction Mode (CCM)

Product Highlights

• Leadfree DIP and DSO Package

• Wide Input Range

• Optimized for applications which require fast Startup

• Output Power Controllable by External Sense Resistor

• Programmable Operating Frequency

• Output Over-Voltage Protection

ICE2PCS05G

test

PG-DSO-8

• Fast Output Dynamic Response during Load Jumps

Features

Description

•

Ease of Use with Few External Components

The ICE2PCS05/G is a 8-pin wide input range controller

IC for active power factor correction converters. It is de-

signed for converters in boost topology, and requires few

Supports Wide Range

Average Current Control

External Current and Voltage Loop Compensation external components. Its power supply is recommended

for Greater User Flexibility

to be provided by an external auxiliary supply which will

switch on and off the IC.

•

Programmable Operating/Switching Frequency

(20kHz - 250kHz)

The IC operates in the CCM with average current control,

and in DCM only under light load condition. The switching

frequency is programmable by the resistor at pin 4. Both

compensations for the current and voltage loop are exter-

nal to allow full user control.

•

Max Duty Cycle of 95% (at 25°C) at 125kHz

Trimmed Internal Reference Voltage (3V+2% at

25°C)

•

VCC Under-Voltage Lockout

Cycle by Cycle Peak Current Limiting

Output Over-Voltage Protection

Open Loop Detection

There are various protection features incorporated to en-

sure safe system operation conditions. The internal refer-

ence is trimmed (3V+2%) to ensure precise protection and

control level. The device has a fast startup time with con-

trolled peak start up current.

Enhanced Dynamic Response

Short Startup(SoftStart) duration

Fulfills Class D Requirements of IEC 1000-3-2

Soft Overcurrent Protection

Typical Application

V_OUT

Auxiliary Supply

VCC

EMI-Filter

85 ... 265 VAC

SWITCH

ICE2PCS05/

PFC-Controller

ICE2PCS05G

Protection Unit

VSENSE

VCOMP

PWM Logic

Driver

Voltage Loop

Compensation

GATE

FREQ

Variable

Ramp

Oscillator

Generator

ICOMP

Current Loop

Compensation

Nonlinear

Gain

ISENSE

GND

Type

Package

ICE2PCS05

ICE2PCS05G

Version 1.0

PG-DIP-8

PG-DSO-8

3

09 Oct 2008

CCM-PFC

ICE2PCS05/G

1

Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1

1.2

2

Representative Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Soft Over Current Control (SOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Peak Current Limit (PCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Open Loop Protection / Input Under Voltage Protect (OLP) . . . . . . . . . . . 9

Over-Voltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Frequency Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Average Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Complete Current Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Current Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Nonlinear Gain Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PWM Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Voltage Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Enhanced Dynamic Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.1

3.2

3.3

3.4

3.4.1

3.4.2

3.4.3

3.4.4

3.5

3.6

3.6.1

3.6.2

3.6.3

3.6.4

3.7

3.8

3.8.1

3.8.2

3.9

4

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Variable Frequency Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

System Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Current Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Voltage Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

4.1

4.2

4.3

4.3.1

4.3.2

4.3.3

4.3.4

4.3.5

4.3.6

4.3.7

5

Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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09 Oct 2008

CCM-PFC

ICE2PCS05/G

Pin Configuration and Functionality

1

Pin Configuration and Functionality

1.1

Pin Configuration

ICOMP (Current Loop Compensation)

Low pass filter and compensation of the current control

loop. The capacitor which is connected at this pin

integrates the output current of OTA2 and averages the

current sense signal.

Symbol Function

1

2

3

4

5

6

7

8

GND

IC Ground

ICOMP Current Loop Compensation

ISENSE Current Sense Input

ISENSE (Current Sense Input)

The ISENSE Pin senses the voltage drop at the

external sense resistor (R1). This is the input signal for

the average current regulation in the current loop. It is

also fed to the peak current limitation block.

FREQ

Switching Frequency Setting

VCOMP Voltage Loop Compensation

VSENSE V_OUTSense (Feedback) Input

During power up time, high inrush currents cause high

negative voltage drop at R1, driving currents out of pin

3 which could be beyond the absolute maximum

ratings. Therefore a series resistor (R2) of around

220Ω is recommended in order to limit this current into

the IC.

VCC

IC Supply Voltage

Gate Drive Output

GATE

FREQ (Frequency Setting)

This pin allows the setting of the operating switching

frequency by connecting a resistor to ground. The

frequency range is from 20kHz to 250kHz.

Package PG-DIP-8 / PG-DSO-8

VSENSE (Voltage Sense/Feedback)

The output bus voltage is sensed at this pin via a

resistive divider. The reference voltage for this pin is

3V.

GND

ICOMP

ISENSE

FREQ

1

8

7

6

5

GATE

VCC

2

VCOMP (Voltage Loop Compensation)

3

4

VSENSE

This pin provides the compensation of the output

voltage loop with a compensation network to ground

(see Figure 2). This also gives the soft start function

which controls an increasing AC input current during

start-up.

VCOMP

VCC (Power Supply)

The VCC pin is the positive supply of the IC and should

be connected to an external auxiliary supply. The

operating range is between 11V and 26V. The turn-on

threshold is at 11.8V and under voltage occurs at 11V.

There is no internal clamp for a limitation of the power

supply.

Figure 1

Pin Configuration (top view)

GATE

1.2

Pin Functionality

The GATE pin is the output of the internal driver stage,

which has a capability of 1.5A instantaneous source

and 2.0A instantaneous sink current.

GND (Ground)

The ground potential of the IC.

Its gate drive voltage is clamped at 15V (typically).

Version 1.0

5 09 Oct 2008

CCM-PFC

ICE2PCS05/G

Representative Block diagram

2

Representative Block diagram

Figure 2

Representative Block diagram

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09 Oct 2008

CCM-PFC

ICE2PCS05/G

Functional Description

3

Functional Description

If VCC drops below 11V, the IC is off. The IC will then

be consuming typically 300µA, whereas consuming

13mA during normal operation.

3.1

General

The ICE2PCS05/G is a 8 pin control IC for power factor

correction converters. It comes in both DIP and DSO

packages and is suitable for wide range line input

applications from 85 to 265 VAC. The IC supports

converters in boost topology and it operates in

continuous conduction mode (CCM) with average

current control.

The IC operates with a cascaded control; the inner

current loop and the outer voltage loop. The inner

current loop of the IC controls the sinusoidal profile for

the average input current. It uses the dependency of

the PWM duty cycle on the line input voltage to

determine the corresponding input current. This means

the average input current follows the input voltage as

long as the device operates in CCM. Under light load

condition, depending on the choke inductance, the

system may enter into discontinuous conduction mode

(DCM). In DCM, the average current waveform will be

distorted but the resultant harmonics are still low

enough to meet the Class D requirement of IEC 1000-

3-2.

The IC can be turned off and forced into standby mode

by pulling down the voltage at pin 6 (VSENSE) to lower

than 0.6V. The current consumption is reduced to

300µA in this mode.

3.3

Start-up

Figure 4 shows the operation of voltage loop’s OTA1

during startup. The VCOMP pin is pull internally to

ground via switch S1 during UVLO and other fault

conditions (see later section on “System Protection”).

During power up when V_OUTis less than 83% of the

rated level, OTA1 sources an output current, maximum

30µA, into the compensation network at pin 5

(VCOMP) causing the voltage at this pin to rise linearly.

This results in a controlled linear increase of the input

current from 0A thus reducing the stress on the

external component.

The outer voltage loop controls the output bus voltage.

Depending on the load condition, OTA1 establishes an

appropriate voltage at VCOMP pin which controls the

amplitude of the average input current.

VSENSE

R4

x V_OUT

)

(

R3 + R4

The IC is equipped with various protection features to

ensure safe operating condition for both the system

and device. Important protection features are namely

Open-Loop protection, Current Limitation and Output

Over-voltage Protection.

OTA1

3V

VCOM P

protect

S1

R6

C4

3.2

Power Supply

C5

ICE2PCS05/G

An internal under voltage lockout (UVLO) block

monitors the VCC power supply. As soon as it exceeds

11.8V and the voltage at pin 6 (VSENSE) is >0.6V, the

IC begins operating its gate drive and performs its

Startup as shown in Figure 3.

Figure 4

Startup Circuit

As V_OUThas not reached within 5% from the rated

value, VCOMP voltage is level-shifted by the window

detect block as shown in Figure 5, to ensure there is

fast boost up of the output voltage.

.

(V_VSENSE> 0.6 V) (V_VSENSE< 0.6 V)

(V_VSENSE> 0.6 V)

When V_OUTapproaches its rated value, OTA1’s

sourcing current drops and the level shift of the window

detect block is removed. The normal voltage loop then

takes control.

V_CC

11.8 V

OFF

11.0 V

OFF

t

IC's

State

Start

Normal

Open loop/

Standby

Up

Operation

Figure 3

State of Operation respect to VCC

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09 Oct 2008

CCM-PFC

ICE2PCS05/G

Functional Description

3.4

System Protection

The IC provides several protection features in order to

ensure the PFC system in safe operating range.

Depending on the input line voltage (V_IN) and output

bus voltage (V_OUT), Figure 7 and 8 show the conditions

when these protections are active.

Normal Control

V_OUT=rated

Window Detect

Max Vcomp current

V_OUT

95%rated

83%rated

VCC > V_CCUVLO

VCC<V_CCUVLO

V_IN(VAC)

t

Level-shifted VCOMP

av(I_IN)

t

Normal

Operation

IC’s

IC OFF

State

VCOMP

t

Figure 6

V_INRelated Protection Features

V_OUT

V_OUT,Rated

Figure 5

Startup with controlled maximum current

108%

100%

20%

t

PCL / SOC

OVP

OLP

Figure 7

V_OUTRelated Protection Features

The following sections describe the functionality of

these protection features.

3.4.1

Soft Over Current Control (SOC)

The IC is designed not to support any output power

that corresponds to a voltage lower than -0.75V at the

ISENSE pin. A further increase in the inductor current,

which results in a lower ISENSE voltage, will activate

the Soft Over Current Control (SOC). This is a soft

control as it does not directly switch off the gate drive.

It acts on the nonlinear gain block to result in a reduced

PWM duty cycle.

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09 Oct 2008

CCM-PFC

ICE2PCS05/G

Functional Description

connected) or an insufficient input voltage V_INfor

normal operation. In this case, most of the blocks within

the IC will be shutdown. It is implemented using

comparator C3 with a threshold of 0.6V as shown in the

IC block diagram in Figure 2.

P_OUT(rated)

P_OUT(max)

IC’s

Normal

State Operation

3.4.4

Over-Voltage Protection (OVP)

Whenever V_OUTexceeds the rated value by 5%, the

over-voltage protection OVP is active as shown in

Figure 6. This is implemented by sensing the voltage at

pin VSENSE with respect to a reference voltage of

3.15V. A VSENSE voltage higher than 3.15V will

immediately reduce the output duty cycle, bypassing

the normal voltage loop control. This results in a lower

input power to reduce the output voltage V_OUT. A

VSENSE voltage higher than 3.25V will immediately

turn off the gate, thereby preventing damage to bus

capacitor.

SOC

PCL

V_ISENSE

-0.61V -0.75V

-1.04V

0

Figure 8

SOC and PCL Protection as function of

V_ISENSE

The rated output power with a minimum V_IN(V_INMIN) is

0.61

P

_OUT(rated) = V_INMIN× ------------------

R1 ⋅

2

3.5

Frequency Setting

Due to the internal parameter tolerance, the maximum

power with V_INMINis

The switching frequency of the PFC converter can be

set with an external resistor R5 at FREQ pin as shown

Figure 10. The pin voltage V_FREQis typically 1.7V. The

corresponding capacitor for the oscillator is integrated

in the device and the R5/frequency relationship is given

at the “Electrical Characteristic” section. The

recommended operating frequency range is from

20kHz to 250kHz. As an example, a R5 of 33kΩ at pin

FREQ will set a switching frequency F_SWof 134kHz

typically.

0.75

P

_OUT(max) = V_INMIN× ------------------

R1 ⋅

2

3.4.2

Peak Current Limit (PCL)

The IC provides a cycle by cycle peak current limitation

(PCL). It is active when the voltage at pin 3 (ISENSE)

reaches -1.04V. This voltage is amplified by OP1 by a

factor of -1.43 and connected to comparator C2 with a

reference voltage of 1.5V as shown in Figure 9. A

deglitcher with 300ns after the comparator improves

noise immunity to the activation of this protection.

Current Limit

1.5V

Full-wave

Rectifier

Deglitcher

300ns

Turn Off

Driver

C2

ISENSE

R2

1.43x

I

INDUCTOR

OP1

R1

I

C

E2PCS01

/

G

Peak Current Limit (PCL)

Figure 9

3.4.3

Open Loop Protection / Input Under

Voltage Protect (OLP)

Whenever VSENSE voltage falls below 0.6V, or

equivalently V_OUTfalls below 20% of its rated value, it

indicates an open loop condition (i.e. VSENSE pin not

F r e q u e n c y / k H z

Figure 10

Frequency Versus R_FREQ

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CCM-PFC

ICE2PCS05/G

Functional Description

From the above equation, D_OFFis proportional to V_IN.

The objective of the current loop is to regulate the

average inductor current such that it is proportional to

the off duty cycle D_OFF, and thus to the input voltage

V_IN. Figure 12 shows the scheme to achieve the

objective.

3.6

Average Current Control

3.6.1

Complete Current Loop

The complete system current loop is shown in Figure

11.

Vout

L1

D1

R3

R4

ave(I_IN) at ICOMP

ramp profile

From

Full-wave

Retifier

C2

R7

R2

R1

GATE

ISENSE

ICOMP

Current Loop

voltage

proportional to

averaged

Gate

Inductor current

Driver

Current Loop

Compensation

PWM

Comparator

GATE

drive

Q

R

S

C1

OTA2

1.0mS

PWM Logic

+/-50uA (linear range)

t

C3

S2

Input From

Nonlinear

Gain

4.2V

Voltage Loop

Figure 12 Average Current Control in CCM

Fault

The PWM is performed by the intersection of a ramp

signal with the averaged inductor current at pin 5

(ICOMP). The PWM cycle starts with the Gate turn off

for a duration of T_OFFMIN(250ns typ.) and the ramp is

kept discharged. The ramp is then allowed to rise after

T_OFFMINexpires. The off time of the boost transistor

ends at the intersection of the ramp signal and the

averaged current waveform. This results in the

proportional relationship between the average current

ICE2PCS05/G

Figure 11 Complete System Current Loop

It consists of the current loop block which averages the

voltage at pin ISENSE, resulted from the inductor

current flowing across R1. The averaged waveform is

compared with an internal ramp in the ramp generator

and PWM block. Once the ramp crosses the average

waveform, the comparator C1 turns on the driver stage

through the PWM logic block. The Nonlinear Gain block

defines the amplitude of the inductor current. The

following sections describe the functionality of each

individual blocks.

and the off duty cycle D_OFF

.

Figure 13 shows the timing diagrams of T_OFFMINand the

PWM waveforms.

T_OFFMIN

2.5% of T

3.6.2

Current Loop Compensation

PWM cycle

The compensation of the current loop is done at the

ICOMP pin. This is the OTA2 output and a capacitor C3

has to be installed at this node to ground (see Figure

11). Under normal mode of operation, this pin gives a

voltage which is proportional to the averaged inductor

current. This pin is internally shorted to 4.2V in the

event of IC shuts down when OLP and UVLO occur.

(1)

V_CREF

V_RAMP

PWM

ramp

released

3.6.3

Pulse Width Modulation (PWM)

t

The IC employs an average current control scheme in

continuous conduction mode (CCM) to achieve the

power factor correction.

(1)

V

is a function of V_ICOMP

CREF

Figure 13 Ramp and PWM waveforms

3.6.4 Nonlinear Gain Block

Assuming the voltage loop is working and output

voltage is kept constant, the off duty cycle D_OFFfor a

CCM PFC system is given as

V_IN

D_OFF= -------------

V_OUT

The nonlinear gain block controls the amplitude of the

regulated inductor current. The input of this block is the

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09 Oct 2008

CCM-PFC

ICE2PCS05/G

Functional Description

voltage at pin VCOMP. This block has been designed

to support the wide input voltage range (85-265VAC).

Vout

D1

L1

R7

From

Full-wave

Retifier

R3

3.7

PWM Logic

C2

R4

The PWM logic block prioritizes the control input

signals and generates the final logic signal to turn on

the driver stage. The speed of the logic gates in this

block, together with the width of the reset pulse T_OFFMIN

,

Gate Driver

are designed to meet a maximum duty cycle D_MAXof

95% at the GATE output under 136kHz of operation.

Current Loop

+

PWM Generation

In case of high input currents which result in Peak

Current Limitation, the GATE will be turned off

immediately and maintained in off state for the current

PWM cycle. The signal Toffmin resets (highest priority,

overriding other input signals) both the current limit

latch and the PWM on latch as illustrated in Figure 14.

V_IN

GATE

Nonlinear

Gain

OTA1

Av(I_IN)

3V

VSENSE

t

Current

VCOMP

Limit Latch

Q

Peak Current

Limit

G1

S

R

HIGH =

turn GATE on

L1

R6

C4

PWM on

Latch

C5

Current Loop

PWM on signal

S

L2

R

Q

Figure 15 Voltage Loop

3.8.2 Enhanced Dynamic Response

Toffmin

2.5% of T

Due to the low frequency bandwidth of the voltage loop,

the dynamic response is slow and in the range of about

several 10ms. This may cause additional stress to the

bus capacitor and the switching transistor of the PFC in

the event of heavy load changes.

Figure 14 PWM Logic

3.8

Voltage Loop

The IC provides therefore a “window detector” for the

feedback voltage V_VSENSEat pin 6 (VSENSE).

Whenever V_VSENSEexceeds the reference value (3V)

by +5%, it will act on the nonlinear gain block which in

turn affect the gate drive duty cycle directly. This

change in duty cycle is bypassing the slow changing

VCOMP voltage, thus results in a fast dynamic

The voltage loop is the outer loop of the cascaded

control scheme which controls the PFC output bus

voltage V_OUT. This loop is closed by the feedback

sensing voltage at VSENSE which is a resistive divider

tapping from V_OUT. The pin VSENSE is the input of

OTA1 which has an internal reference of 3V. Figure 15

shows the important blocks of this voltage loop.

response of V_OUT

.

3.8.1

Voltage Loop Compensation

3.9

Output Gate Driver

The compensation of the voltage loop is installed at the

VCOMP pin (see Figure 15). This is the output of OTA1

and the compensation must be connected at this pin to

ground. The compensation is also responsible for the

soft start function which controls an increasing AC input

current during start-up.

The output gate driver is a fast totem pole gate drive. It

has an in-built cross conduction currents protection and

a Zener diode Z1 (see Figure 16) to protect the external

transistor switch against undesirable over voltages.

The maximum voltage at pin 8 (GATE) is typically

clamped at 15V.

The output is active HIGH and at VCC voltages below

the under voltage lockout threshold V_CCUVLO, the gate

drive is internally pull low to maintain the off state.

Version 1.0

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CCM-PFC

ICE2PCS05/G

Functional Description

VCC

Gate Driver

PWM Logic

HIGH to

turn on

LV

Z1

External

MOS

GATE

* LV: Level Shift

ICE2PCS05/G

Figure 16 Gate Driver

Version 1.0

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09 Oct 2008

CCM-PFC

ICE2PCS05/G

Electrical Characteristics

4

Electrical Characteristics

4.1

Absolute Maximum Ratings

Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction

of the integrated circuit.

Parameter

Symbol

Limit Values

Unit

Remarks

min.

max.

25

5

V_CCSupply Voltage

FREQ Voltage

V_CC

-0.3

-20

-1

V

V_FREQ

V_ICOMP

V_ISENSE

I_ISENSE

V_VSENSE

I_VSENSE

V_VCOMP

V_GATE

V

ICOMP Voltage

ISENSE Voltage

ISENSE Current

VSENSE Voltage

VSENSE Current

VCOMP Voltage

GATE Voltage

5

V

2)

5

V

1

mA

V

Recommended R2=220Ω

-0.3

-1

5

1

mA

V

R3>400kΩ

-0.3

5

17

V

Clamped at 15V if driven

internally.

Junction Temperature

Storage Temperature

T_j

-40

-55

-

150

185

°C

T_S

°C

Thermal Resistance

R

_thJA(DSO)

K/W

PG-DSO-8-13

Junction-Ambient for DSO-8-13

Thermal Resistance

R

_thJA(DIP)

-

90

2

K/W

kV

PG-DIP-8-4

Junction-Ambient for DIP-8-4

ESD Protection

V_ESD

Human Body Model¹⁾

1)

According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor)

2)

Absolute ISENSE current should not be exceeded

4.2

Operating Range

Note: Within the operating range the IC operates as described in the functional description.

Parameter

Symbol

Limit Values

min. max.

V_CCUVLO25

-40 125

Unit

Remarks

V_CCSupply Voltage

V_CC

V

Junction Temperature

T_JCon

°C

Version 1.0

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CCM-PFC

ICE2PCS05/G

Electrical Characteristics

4.3

Characteristics

Note: The electrical characteristics involve the spread of values within the specified supply voltage and junction

temperature range T_Jfrom – 40 °C to 125°C.Typical values represent the median values, which are

related to 25°C. If not otherwise stated, a supply voltage of V_CC=18V is assumed for test condition.

4.3.1

Supply Section

Parameter

Symbol

Limit Values

Unit Test Condition

min.

typ.

max.

VCC Turn-On Threshold

V_CCon

11.4

11.8

12.7

11.7

1.4

V

VCC Turn-Off Threshold/

Under Voltage Lock Out

V_CCUVLO

V_CChy

I_CCstart

I_CCHG

10.4

11.0

0.8

VCC Turn-On/Off Hysteresis

0.65

Start Up Current

Before V_CCon

-

450

15

1100 µA

20

V_VCC=V_VCCon-0.1V

Operating Current with active GATE

mA R5 = 33kΩ

C_L= 4.7nF

Operating Current during Standby

I_CCStdby

-

700 1300 µA

V_VSENSE= 0.5V

V

_ICOMP= 4V

4.3.2

Variable Frequency Section

Parameter

Symbol

Limit Values

typ. max.

136 147 kHz R5 = 33kΩ

Unit Test Condition

min.

Switching Frequency (Typical)

Switching Frequency (Min.)

Switching Frequency (Max.)

Voltage at FREQ pin

F_SWnom

F_SWmin

F_SWmax

V_FREQ

124

17

21

25

kHz I_FREQ=V_FREQ/ 234kΩ

250

1.65

285

1.70

315 kHz R5 = 15kΩ

1.76

V

Version 1.0

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CCM-PFC

ICE2PCS05/G

Electrical Characteristics

4.3.3

PWM Section

Parameter

Symbol

Limit Values

Unit Test Condition

min.

typ.

max.

Max. Duty Cycle

Min. Duty Cycle

Min. Off Time

D_MAX

D_MIN

92

95

98.5

%

ns

F_SW= F_SWnom

(R5 = 33kΩ)

0

V_VCOMP= 0V, V_VSENSE= 3V

V

_ICOMP= 4.3V

T_OFFMIN

100

250

580

V_VSENSE= 3V

V_ISENSE= 0.1V (R5 = 33kΩ)

The parameter is not subject to production test - verified by design/characterization

4.3.4 System Protection Section

Parameter

Symbol

Limit Values

Unit Test Condition

min.

typ.

max.

0.65

Open Loop Protection (OLP)

VSENSE Threshold

V_OLP

V_PCL

V_SOC

V_OVP

0.55

0.6

V

Peak Current Limitation (PCL)

ISENSE Threshold

-1.16 -1.04 -0.95

-0.75 -0.68 -0.61

Soft Over Current Control (SOC)

ISENSE Threshold

Output Over-Voltage Protection (OVP)

3.1

3.25

3.4

Version 1.0

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09 Oct 2008

CCM-PFC

ICE2PCS05/G

Electrical Characteristics

4.3.5

Current Loop Section

Parameter

Symbol

Limit Values

Unit Test Condition

min.

typ.

max.

OTA2 Transconductance Gain

OTA2 Output Linear Range¹⁾

ICOMP Voltage during OLP

Gm_OTA2

I_OTA2

0.8

1.0

1.3

mS At Temp = 25°C

-

± 50

4.2

-

µA

V_ICOMPF

3.9

V

V_VSENSE= 0.5V

4.3.6

Voltage Loop Section

Parameter

Symbol

Limit Values

Unit Test Condition

min.

typ.

max.

OTA1 Reference Voltage

V_OTA1

Gm_OTA1

I_OTA1SO

I_OTA1SK

2.92

3.00

3.08

V

measured at VSENSE

OTA1 Transconductance Gain

26

18

21

39

30

51

38

41

µS

OTA1 Max. Source Current

Under Normal Operation

µA V_VSENSE= 2V

V

_VCOMP= 3V

OTA1 Max. Sink Current

Under Normal Operation

µA V_VSENSE= 4V

_VCOMP= 3V

V

Enhanced Dynamic Response

VSENSE High Threshold

VSENSE Low Threshold

V_Hi

V_Lo

3.09

2.76

3.18

2.85

3.26

2.94

V

VSENSE Input Bias Current at 3V

VSENSE Input Bias Current at 1V

VCOMP Voltage during OLP

I_VSEN3V

0

-

1.5

µA V_VSENSE= 3V

I_VSEN1V

-

1

µA V_VSENSE= 1V

V_VCOMPF

0.2

0.4

V

V_VSENSE= 0.5V

_VCOMP= 0.5mA

I

Version 1.0

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09 Oct 2008

CCM-PFC

ICE2PCS05/G

Electrical Characteristics

4.3.7

Driver Section

Parameter

Symbol

Limit Values

Unit Test Condition

min.

typ.

max.

GATE Low Voltage

V_GATEL

-

1.2

V

V_CC=10V

_GATE= 5 mA

I

-

1.5

V_CC=10V

I

_GATE=20 mA

_GATE= 0 A

-

0.4

-

1.0

-

V

I

-

-0.2

-

I_GATE= 20 mA

I_GATE= -20 mA

0

GATE High Voltage

V_GATEH

14.8

-

V_CC= 25V

C_L= 4.7nF

-

7.8

-

14.8

9.2

60

50

-

V

V_CC= 19V

C_L= 4.7nF

-

V_CC= V_VCCoff+ 0.2V

C_L= 4.7nF

GATE Rise Time

GATE Fall Time

t_r

-

ns

V_Gate= 2V ...12V

C_L= 4.7nF

t_f

-

ns

A

V_Gate= 12V ...2V

C_L= 4.7nF

C_L= 4.7nF¹⁾

GATE Current, Peak,

Rising Edge

I_GATE

-1.5

-

GATE Current, Peak,

Falling Edge

-

2.0

A

C_L= 4.7nF¹⁾

1)

Design characteristics (not meant for production testing)

Version 1.0

17

09 Oct 2008

CCM-PFC

ICE2PCS05/G

Outline Dimension

5

Outline Dimension

Figure 17

PG-DSO-8 and PG-DIP-8 Outline Dimension

Version 1.0

18

09 Oct 2008

CCM-PFC

ICE2PCS05/G

Outline Dimension

Version 1.0

19

09 Oct 2008

CCM-PFC

ICE2PCS05/G

Outline Dimension

Version 1.0

20

09 Oct 2008

CCM-PFC

ICE2PCS05/G

Outline Dimension

Version 1.0

21

09 Oct 2008

Total Quality Management

Qualität hat für uns eine umfassende

Bedeutung. Wir wollen allen Ihren

Ansprüchen in der bestmöglichen

Weise gerecht werden. Es geht uns also

nicht nur um die Produktqualität –

unsere Anstrengungen gelten

gleichermaßen der Lieferqualität und

Logistik, dem Service und Support

sowie allen sonstigen Beratungs- und

Betreuungsleistungen.

Quality takes on an allencompassing

significance at Semiconductor Group.

For us it means living up to each and

every one of your demands in the best

possible way. So we are not only

concerned with product quality. We

direct our efforts equally at quality of

supply and logistics, service and

support, as well as all the other ways in

which we advise and attend to you.

Dazu gehört eine bestimmte

Part of this is the very special attitude of

our staff. Total Quality in thought and

deed, towards co-workers, suppliers

and you, our customer. Our guideline is

“do everything with zero defects”, in an

open manner that is demonstrated

beyond your immediate workplace, and

to constantly improve.

Throughout the corporation we also

think in terms of Time Optimized

Processes (top), greater speed on our

part to give you that decisive

competitive edge.

Geisteshaltung unserer Mitarbeiter.

Total Quality im Denken und Handeln

gegenüber Kollegen, Lieferanten und

Ihnen, unserem Kunden. Unsere

Leitlinie ist jede Aufgabe mit „Null

Fehlern“ zu lösen – in offener

Sichtweise auch über den eigenen

Arbeitsplatz hinaus – und uns ständig

zu verbessern.

Unternehmensweit orientieren wir uns

dabei auch an „top“ (Time Optimized

Processes), um Ihnen durch größere

Schnelligkeit den entscheidenden

Wettbewerbsvorsprung zu verschaffen.

Geben Sie uns die Chance, hohe

Leistung durch umfassende Qualität zu

beweisen.

Give us the chance to prove the best of

performance through the best of quality

– you will be convinced.

Wir werden Sie überzeugen.

h t t p : / / w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	ICE2PCS05G
厂家：	Infineon
描述：	Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM) 单机功率因数校正（ PFC ）控制器在连续导通模式（ CCM ）稳压器开关式稳压器或控制器电源电路开关式控制器功率因数校正光电二极管
文件：	总22页 (文件大小：536K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICE2PCS05G [INFINEON]

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