ICE2QS03_11_技术文档

Datasheet,Version 2.1, April 21, 2011

ICE2QS03

Quasi-Resonant PWM

Controller

Power Management & Supply

N e v e r s t o p t h i n k i n g .

ICE2QS03

Revision History:

April 21, 2011

Datasheet

Previous Version:

Page17

2.0

test condition Iout changed from 20mA to 10mA

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Edition April 21, 2011

Published by

Infineon Technologies AG

81726 München, Germany

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ICE2QS03

Quasi-Resonant PWM Controller

Product Highlight

•

Active burst mode for low standby power

Digital frequency reduction for better overall system efficiency

Integrated power cell for IC self-power supply

Features

Description

•

Quasiresonant operation till very low load

Active burst mode operation at light/no load for low

standby input power (< 100mW)

Digital frequency reduction with decreasing load

Power cell for VCC pre-charging with constant

current

Built-in digital soft-start

Foldback correction and cycle-by-cycle peak

current limitation

Auto restart mode for VCC Overvoltage protection

Auto restart mode for VCC Undervoltage protection

Auto restart mode for openloop/overload protection

Latch-off mode for adjustable output overvoltage

protection

ICE2QS03 is

a

quasi-resonant PWM controller

optimized for off-line switch power supply applications

such as LCD TV, CRT TV and notebook adapter. The

digital frequency reduction with decreasing load

enables a quasi-resonant operation till very low load.

As a result, the overall system efficiency is significantly

improved compared to other conventional solutions.

The active burst mode operation enables an ultra-low

power consumption at standby mode with small and

controllable output voltage ripple. Based on the

BiCMOS technology, the product has a wide operation

range (up to 26V) of IC power supply and lower power

consumption. The numerous protection functions give

a full protection of the power supply system in failure

situations. All of these make the ICE2QS03 an

outstanding controller for quasi-resonant flyback

converter in the market.

•

Latch-off mode for Short-winding protection

Typical Application Circuit

L_f

W_p

D_O

Snubber

C_f

V_O

C_bus

W_s

85 ~ 265Vac

R_VCC

D_VCC

C_O

C_VCC

R_ZC2

R_ZC1

W_a

D_r1~D_r4

C_ZC

HV

VCC

ZC

C_PS

Power

Cell

Q1

R_b1

C_DS

Gate

Driver

GATE

Zero Crossing Detection

Power Management

Digital Process Block

Active Burst Mode

R_b2

R_ovs1

Control Unit

GND

FB

Optocoupler

R_c1

Current

Limitation

C_FB

CS

Protection Block

R_CS

C_c2

C_c1

Current Mode Control

TL431

ICE2QS03

R_ovs2

Type

Package

ICE2QS03

PG-DIP-8-6

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Quasi-Resonant PWM Controller

ICE2QS03

Table of Contents

Page

1

Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Pin Configuration with PG-DIP-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Package PG-DIP-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

1.1

1.2

1.3

2

Representative Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3

3.1

3.2

3.3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

VCC Pre-Charging and Typical VCC Voltage During Start-up . . . . . . . . . . .7

Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Digital Frequency Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Up/down counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Zero crossing (ZC counter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Ringing suppression time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Switch Off Determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Foldback Point Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Entering Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . .10

During Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Leaving Active Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.3.1

3.3.1.1

3.3.1.2

3.3.2

3.3.3

3.4

3.4.1

3.5

3.5.1

3.5.2

3.5.3

3.6

4

4.1

4.2

4.3

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Soft Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Foldback Point Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Digital Zero Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Gate Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

4.3.1

4.3.2

4.3.3

4.3.4

4.3.5

4.3.6

4.3.7

4.3.8

4.3.9

4.3.10

5

Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

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Quasi-Resonant PWM Controller

ICE2QS03

Pin Configuration and Functionality

1.3

Pin Functionality

1

Pin Configuration and

Functionality

ZC (Zero Crossing)

At this pin, the voltage from the auxiliary winding after

a time delay circuit is applied. Internally, this pin is

connected to the zero-crossing detector for switch-on

determination. Additionally, the output overvoltage

detection is realized by comparing the voltage Vzc with

an internal preset threshold.

1.1

Pin Configuration with PG-DIP-

8-6

Symbol Function

FB (Feedback)

Normally, an external capacitor is connected to this pin

1

2

3

4

5

6

7

8

ZC

FB

Zero Crossing

for

a smooth voltage V_FB. Internally, this pin is

Feedback

connected to the PWM signal generator for switch-off

determination (together with the current sensing

signal), the digital signal processing for the frequency

reduction with decreasing load during normal

operation, and the Active Burst Mode controller for

entering Active Burst Mode operation determination

and burst ratio control during Active Burst Mode

CS

Current Sense

HV

High Voltage Input

Gate Drive Output

Controller Supply Voltage

Controller Ground

HV

GATE

VCC

GND

operation. Additionally, the open-loop

/ over-load

protection is implemented by monitoring the voltage at

this pin.

CS (Current Sense)

1.2

Package PG-DIP-8-6

This pin is connected to the shunt resistor for the

primary current sensing, externally, and the PWM

signal generator for switch-off determination (together

with the feedback voltage), internally. Moreover, short-

winding protection is realised by monitoring the voltage

Vcs during on-time of the main power switch.

ZC

FB

CS

HV

1

8

7

6

5

GND

VCC

GATE

HV

GATE (Gate Drive Output)

2

This output signal drives the external main power

switch, which is a power MOSFET in most case.

3

4

HV (High Voltage)

The pin HV is connected to the bus voltage, externally,

and to the power cell, internally. The current through

this pin pre-charges the VCC capacitor with constant

current once the supply bus voltage is applied.

VCC (Power supply)

VCC pin is the positive supply of the IC. The operating

range is between V_VCCoffand V_VCCOVP

.

Figure 1

Pin Configuration PG-DIP-8-6(top view)

GND (Ground)

This is the common ground of the controller.

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Quasi-Resonant PWM Controller

ICE2QS03

Representative Block diagram

2

Representative Block diagram

Figure 2

Representative Block diagram

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April 21, 2011

Quasi-Resonant PWM Controller

ICE2QS03

Functional Description

then will reach a constant value depending on output

load.

3

Functional Description

3.1

VCC Pre-Charging and Typical

VCC Voltage During Start-up

3.2

Soft-start

At the time t_on, the IC begins to operate with a soft-start.

By this soft-start the switching stresses for the switch,

diode and transformer are minimised. The soft-start

implemented in ICE2QS03 is a digital time-based

function. The preset soft-start time is 12ms with 4

steps. If not limited by other functions, the peak voltage

on CS pin will increase step by step from 0.32V to 1V

finally.

In ICE2QS03, a high voltage startup cell is integrated.

As shown in Figure 2, the start cell consists of a high

voltage device and a controller, whereby the high

voltage device is controlled by the controller. The

startup cell provides

a pre-charging of the VCC

capacitor till VCC voltage reaches the VCC turned-on

threshold V_VCConand the IC begins to operate.

Once the mains input voltage is applied, a rectified

voltage shows across the capacitor C_bus. The high

voltage device provides a current to charge the VCC

capacitor C_vcc. Before the VCC voltage reaches a

certain value, the amplitude of the current through the

high voltage device is only determined by its channel

resistance and can be as high as several mA. After the

VCC voltage is high enough, the controller controls the

high voltage device so that a constant current around

1mA is provided to charge the VCC capacitor further,

until the VCC voltage exceeds the turned-on threshold

V_VCCon. As shown as the time phase I in Figure 3, the

VCC voltage increase near linearly and the charging

speed is independent of the mains voltage level.

Vcs_sst

(V)

1.00

0.83

0.66

0.49

0.32

t_on

3

6

9

12

Time(ms)

Figure 4

Maximum current sense voltage during

softstart

V_VCC

3.3

Normal Operation

i

ii

iii

V_VCCon

The PWM controller during normal operation consists

of a digital signal processing circuit including an up/

down counter, a zero-crossing counter (ZC counter)

and a comparator, and an analog circuit including a

current measurement unit and a comparator. The

switch-on and -off time points are each determined by

the digital circuit and the analog circuit, respectively. As

input information for the switch-on determination, the

zero-crossing input signal and the value of the up/down

counter are needed, while the feedback signal V_FBand

the current sensing signal V_CSare necessary for the

switch-off determination. Details about the full

operation of the PWM controller in normal operation

are illustrated in the following paragraphs.

V_VCCoff

t2

VCC voltage at start up

t

t1

Figure 3

The time taking for the VCC pre-charging can then be

approximately calculated as:



 





------------------------------------------



=

[1]





 

where I_VCCcharge2is the charging current from the

startup cell which is 1.05mA, typically.

3.3.1

Digital Frequency Reduction

As mentioned above, the digital signal processing

circuit consists of an up/down counter, a ZC counter

and a comparator. These three parts are key to

implement digital frequency reduction with decreasing

load. In addition, a ringing suppression time controller

is implemented to avoid mistriggering by the high

frequency oscillation, when the output voltage is very

low under conditions such as soft start or output short

circuit . Functionality of these parts is described as in

the following.

Exceeds the VCC voltage the turned-on threshold

V

_VCConof at time t₁, the startup cell is switched off, and

the IC begins to operate with a soft-start. Due to power

consumption of the IC and the fact that still no energy

from the auxiliary winding to charge the VCC capacitor

before the output voltage is built up, the VCC voltage

drops (Phase II). Once the output voltage is high

enough, the VCC capacitor receives then energy from

the auxiliary winding from the time point t₂on. The VCC

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Quasi-Resonant PWM Controller

ICE2QS03

Functional Description

3.3.1.1

Up/down counter

threshold voltages, V_FBZLand V_FBZH, are changed

internally depending on the line voltage levels.

The up/down counter stores the number of the zero

crossing to be ignored before the main power switch is

switched on after demagnetisation of the transformer.

This value is fixed according to the feedback voltage,

clock

T=48ms

V_FB

, which contains information about the output

power. Indeed, in a typical peak current mode control,

a high output power results in a high feedback voltage,

and a low output power leads to a low regulation

voltage. Hence, according to V_FB, the value in the up/

down counter is changed to vary the power MOSFET

off-time according to the output power. In the following,

the variation of the up/down counter value according to

the feedback voltage is explained.

t

V_FB

V_FBR1

V_FBZH

V_FBZL

The feedback voltage V_FBis internally compared with

three threshold voltages V_RL, V_RHand V_RM, at each

clock period of 48ms. The up/down counter counts then

upward, keep unchanged or count downward, as

shown in Table 1.

Up/down

counter

1

Case 1

4

2

7

5

3

7

6

4

7

6

4

7

6

4

7

5

4

2

5

3

1

4

Case 2

Case 3

4

7

3

6

Table 1

Operation of the up/down counter

Figure 5 Up/down counter operation

3.3.1.2 Zero crossing (ZC counter)

up/down counter

action

v_FB

Count upwards till

7

In the system, the voltage from the auxiliary winding is

applied to the zero-crossing pin through a RC network,

which provides a time delay to the voltage from the

auxiliary winding. Internally, this pin is connected to a

clamping network, a zero-crossing detector, an output

overvoltage detector and a ringing suppression time

controller.

Always lower than V_FBZL

Once higher than V_FBZL, but

always lower than V_FBZH

Stop counting, no

value changing

Once higher than V_FBZH, but Count downwards

always lower than V_FBR1

till 1

During on-state of the power switch a negative voltage

applies to the ZC pin. Through the internal clamping

network, the voltage at the pin is clamped to certain

level.

Set up/down

counter to 1

Once higher than V_FBR1

In the ICE2QS03, the number of zero crossing is

limited to 7. Therefore, the counter varies between 1

and 7, and any attempt beyond this range is ignored.

When V_FBexceeds V_FBR1voltage, the up/down counter

is initialised to 1, in order to allow the system to react

The ZC counter has a minimum value of 0 and

maximum value of 7. After the internal MOSFET is

turned off, every time when the falling voltage ramp of

on ZC pin crosses the 100mV threshold, a zero

crossing is detected and ZC counter will increase by 1.

It is reset every time after the GATE output is changed

to high.

rapidly to

a sudden load increase. The up/down

counter value is also intialised to 1 at the start-up, to

ensure an efficient maximum load start up. Figure 5

shows some examples on how up/down counter is

changed according to the feedback voltage over time.

The voltage v_ZCis also used for the output overvoltage

protection. Once the voltage at this pin is higher than

the threshold V_ZCOVPduring off-time of the main switch,

the IC is latched off after a fixed blanking time.

The use of two different thresholds V_FBZLand V_FBZHto

count upward or downward is to prevent frequency

jittereing when the feedback voltage is close to the

threshold point. However, for a stable operation, these

two thresholds must not be affected by the foldback

current limitation (see Section 3.4.1), which limits the

V_CSvoltage. Hence, to prevent such situation, the

To achieve the switch-on at voltage valley, the voltage

from the auxiliary winding is fed to a time delay network

(the RC network consists of D_zc, R_zc1, R_zc2and C_zcas

shown in typical application circuit) before it is applied

to the zero-crossing detector through the ZC pin. The

needed time delay to the main oscillation signal t

should be approximately one fourth of the oscillation

period (by transformer primary inductor and drain-

source capacitor) minus the propagation delay from

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Quasi-Resonant PWM Controller

ICE2QS03

Functional Description

thedetected zero-crossing to the switch-on of the main To avoid mistriggering caused by the voltage spike

switch t_delay, theoretically:

across the shunt resistor at the turn on of the main

power switch, a leading edge blanking time, t_LEB, is

applied to the output of the comparator. In other words,

once the gate drive is turned on, the minimum on time

of the gate drive is the leading edge blanking time.







--------------

 =

– 

[2]



This time delay should be matched by adjusting the

time constant of the RC network which is calculated as:

In addition, there is

a maximum on time, t_OnMax,

limitation implemented in the IC. Once the gate drive

has been in high state longer than the maximum on

time, it will be turned off to prevent the switching

frequency from going too low because of long on time.



 

 

---------------------------------



= 



[3]







+ 





3.4

Current Limitation

3.3.2

Ringing suppression time

There is a cycle by cycle current limitation realized by

the current limit comparator to provide an overcurrent

detection. The source current of the MOSFET is

sensed via a sense resistor R_CS. By means of R_CSthe

source current is transformed to a sense voltage V_CS

which is fed into the pin CS. If the voltage V_CSexceeds

an internal voltage limit, adjusted according to the

Mains voltage, the comparator immediately turns off

the gate drive.

After MOSFET is turned off, there will be some

oscillation on V_DS, which will also appear on the voltage

on ZC pin. To avoid that the MOSFET is turned on

mistriggerred by such oscillations,

a

ringing

suppression timer is implemented. The timer is

dependent on the voltage v_ZC. When the voltage v_ZCis

lower than the threshold V_ZCRS, a longer preset time

applies, while a shorter time is set when the voltage v_ZC

is higher than the threshold.

To prevent the Current Limitation process from

distortions caused by leading edge spikes, a Leading

Edge Blanking time (t_LEB) is integrated in the current

sensing path.

3.3.2.1

Switch on determination

After the gate drive goes to low, it can not be changed

to high during ring suppression time.

A

further comparator is implemented to detect

After ring suppression time, the gate drive can be

turned on when the ZC counter value is higher or equal

to up/down counter value.

dangerous current levels (V_CSSW) which could occur if

one or more transformer windings are shorted or if the

secondary diode is shorted. To avoid an accidental

latch off, a spike blanking time of t_CSSWis integrated in

the output path of the comparator .

However, it is also possible that the oscillation between

primary inductor and drain-source capacitor damps

very fast and IC can not detect enough zero crossings

and ZC counter value will not be high enough to turn on

the gate drive. In this case, a maximum off time is

implemented. After gate drive has been remained off

for the period of T_OffMax, the gate drive will be turned on

again regardless of the counter values and V_ZC. This

function can effectively prevent the switching

frequency from going lower than 20kHz, otherwise

which will cause audible noise, during start up.

3.4.1

Foldback Point Correction

When the main bus voltage increases, the switch on

time becomes shorter and therefore the operating

frequency is also increased. As a result, for a constant

primary current limit, the maximum possible output

power is increased, which the converter may have not

been designed to support.

To avoid such a situation, the internal foldback point

correction circuit varies the V_CSvoltage limit according

to the bus voltage. This means the V_CSwill be

decreased when the bus voltage increases. To keep a

constant maximum input power of the converter, the

3.3.3

Switch Off Determination

In the converter system, the primary current is sensed

by an external shunt resistor, which is connected

between low-side terminal of the main power switch

and the common ground. The sensed voltage across

the shunt resistor v_CSis applied to an internal current

measurement unit, and its output voltage V₁is

compared with the regulation voltage V_FB. Once the

voltage V₁exceeds the voltage V_FB, the output flip-flop

is reset. As a result, the main power switch is switched

off. The relationship between the V₁and the v_CSis

described by:



=   

+ 

[4]





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April 21, 2011

Quasi-Resonant PWM Controller

ICE2QS03

Functional Description

required maximum V_CSversus various input bus about Active Burst Mode operation are explained in the

voltage can be calculated, which is shown in Figure 6. following paragraphs.

1

3.5.1

Entering Active Burst Mode Operation

For determination of entering Active Burst Mode

operation, three conditions apply:

0.9

0.8

0.7

0.6

•

the feedback voltage is lower than the threshold of

V_FBEB(1.25V). Accordingly, the peak current sense

voltage across the shunt resistor is 0.17;

the up/down counter is 7; and

•

a certain blanking time (t_BEB).

Once all of these conditions are fulfilled, the Active

Burst Mode flip-flop is set and the controller enters

Active Burst Mode operation. This multi-condition

determination for entering Active Burst Mode operation

prevents mistriggering of entering Active Burst Mode

operation, so that the controller enters Active Burst

Mode operation only when the output power is really

low during the preset blanking time.

80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 400

Vin(V)

Figure 6 Variation of the VCS limit voltage according

to the I_ZCcurrent

According to the typical application circuit, when

MOSFET is turned on, a negative voltage proportional

to bus voltage will be coupled to auxiliary winding.

Inside ICE2QS03, an internal circuit will clamp the

voltage on ZC pin to nearly 0V. As a result, the current

flowing out from ZC pin can be calculated as

3.5.2

During Active Burst Mode Operation

After entering the Active Burst Mode the feedback

voltage rises as V_OUTstarts to decrease due to the

inactive PWM section. One comparator observes the

feedback signal if the voltage level V_BH(3.6V) is

exceeded. In that case the internal circuit is again

activated by the internal bias to start with swtiching.







------------------------

=





[5]











Turn-on of the power MOSFET is triggered by the

timer. The PWM generator for Active Burst Mode

operation composes of a timer with a fixed frequency of

52kHz, typically, and an analog comparator. Turn-off is

resulted by comparison of the voltage signal v₁with an

internal threshold, by which the voltage across the

shunt resistor V_csBis 0.34V, accordingly. A turn-off can

also be triggered by the maximal duty ratio controller

which sets the maximal duty ratio to 50%. In operation,

the output flip-flop will be reset by one of these signals

which come first.

When this current is higher than I_{ZC_1}, the amount of

current exceeding this threshold is used to generate an

offset to decrease the maximum limit on V_CS. Since the

ideal curve shown in Figure 6 is a nonlinear one, a

digital block in ICE2QS03 is implemented to get a

better control of maximum output power. Additional

advantage to use digital circuit is the production

tolerance is smaller compared to analog solutions. The

typical maximum limit on V_CSversus the ZC current is

shown in Figure 7.

If the output load is still low, the feedback signal

decreases as the PWM section is operating. When

feedback signal reaches the low threshold V_BL(3.0V),

the internal bias is reset again and the PWM section is

disabled until next time regultaion siganl increases

beyond the V_BHthreshold. If working in Active Burst

Mode the feedback signal is changing like a saw tooth

between 3.0V and 3.6V shown in Figure 7.

1

0.9

0.8

0.7

0.6

3.5.3

Leaving Active Burst Mode Operation

300

Figure 7

3.5

500

700

900

1100

1300

1500

1700

1900

2100

The feedback voltage immediately increases if there is

a high load jump. This is observed by one comparator.

As the current limit is 34% during Active Burst Mode a

certain load is needed so that feedback voltage can

exceed V_LB(4.5V). After leaving active busrt mode,

maximum current can now be provided to stabilize V_O.

In addition, the up/down counter will be set to 1

Izc(uA)

V_CS-maxversus I_ZC

Active Burst Mode Operation

At light load condition, the IC enters Active Burst Mode

operation to minimize the power consumption. Details

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Quasi-Resonant PWM Controller

ICE2QS03

Functional Description

immediately after leaving Active Burst Mode. This is IC is reset and the main power switch is then kept off.

helpful to decrease the output voltage undershoot.

After the VCC voltage falls below the threshold V_VCCoff,

the startup cell is activated. The VCC capacitor is then

charged up. Once the voltage exceeds the threshold

V_VCCon, the IC begins to operate with a new soft-start.

V_FB

Entering

Active Burst

Mode

Leaving

Active Burst

Mode

V_FBLB

V_FBBOn

V_FBBOff

In case of open control loop or output over load, the

feedback voltage will be pulled up . After a blanking

time of 24ms, the IC enters auto-restart mode. The

blanking time here enables the converter to provide a

high power in case the increase in V_FBis due to a

sudden load increase. During off-time of the power

switch, the voltage at the zero-crossing pin is

monitored for output over-voltage detection. If the

voltage is higher than the preset threshold v_ZCOVP, the

IC is latched off after the preset blanking time.

V_FBEB

Blanking Window (t_BEB

)

t

V_CS

Current limit level

during Active Burst

Mode

1.0V

If the junction temperature of IC exceeds 140 C, the IC

enter into autorestart mode.

V_CSB

If the voltage at the current sensing pin is higher than

the preset threshold v_CSSWduring on-time of the power

switch, the IC is latched off. This is short-winding

protection.

V_VCC

t

During latch-off protection mode, when the VCC

voltage drops to 10.5V,the startup cell is activated and

the VCC voltage is charged to 18V then the startup cell

is shut down againand repeats the previous procedure.

V_VCCoff

There is also an maximum on time limitation inside

ICE2QS03. Once the gate voltage is high longer than

t_OnMAx, it is turned off immediately.

V_O

Max. Ripple < 1%

Figure 8

Signals in Active Burst Mode

3.6

Protection Functions

The IC provides full protection functions. The following

table summarizes these protection functions.

Table 2

Protection features

VCC Overvoltage

Auto Restart Mode

Latched Off Mode

VCC Undervoltage

Overload/Open Loop

Over temperature

Output Overvoltage

Short Winding

During operation, the VCC voltage is continuously

monitored. In case of an under- or an over-voltage, the

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Quasi-Resonant PWM Controller

ICE2QS03

Electrical Characteristics

4

Electrical Characteristics

Note: All voltages are measured with respect to ground (Pin 8). The voltage levels are valid if other ratings are

not violated.

4.1

Absolute Maximum Ratings

Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction

of the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 7

(VCC) is discharged before assembling the application circuit.

Parameter

Symbol

Limit Values

Unit

Remarks

min.

max.

500

27

HV Voltage

V_HV

V_VCC

V_FB

-

V

VCC Supply Voltage

FB Voltage

-0.3

3

V

5.0

27

V

ZC Voltage

V_ZC

V_CS

V_OUT

I_ZCMAX

T_j

V

CS Voltage

V

GATE Voltage

V

Maximum current out from ZC pin

Junction Temperature

Storage Temperature

-

mA

C

K/W

-40

-55

-

125

150

90

T_S

Thermal Resistance

Junction -Ambient

R_thJA

PG-DIP-8

ESD Capability (incl. Drain Pin)

V_ESD

-

2

kV

Human body model¹⁾

1)

According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k series resistor)

4.2

Operating Range

Note: Within the operating range the IC operates as described in the functional description.

Parameter

Symbol

Limit Values

Unit

Remarks

min.

max.

V_VCCOVP

125

VCC Supply Voltage

V_VCC

T_jCon

V_VCCoff

-25

V

Junction Temperature of

Controller

°C

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Quasi-Resonant PWM Controller

ICE2QS03

Electrical Characteristics

4.3

Characteristics

4.3.1

Supply Section

Note: The electrical characteristics involve the spread of values within the specified supply voltage and junction

temperature range T_Jfrom – 25 C to 125 C. Typical values represent the median values, which are

related to 25°C. If not otherwise stated, a supply voltage of V_CC= 18 V is assumed.

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

Start Up Current

I_VCCstart

-

300

550

A

V_VCC=V_VCCon-0.2V

VCC Charge Current

I_VCCcharge1

-

5.0

-

mA

V_VCC= 0V

I_VCCcharge20.8

-

V_VCC= 1V

I_VCCcharge3

I_DrainIn

-

1.0

-

V_VCC=V_VCCon-0.2V

Maximum Input Current of

2

Startup Cell and CoolMOS^®

Leakage Current of

I_DrainLeak

I_VCCNM

I_VCCAR

-

0.2

1.5

300

50

2.3

-

A

mA

A

V_Drain= 610V

at T_j=100°C

Startup Cell and CoolMOS^®

Supply Current in normal

operation

output low

Supply Current in

Auto Restart Mode with Inactive

Gate

I_FB= 0A

Supply Current in Latch-off Mode I_VCClatch

-

300

500

-

A

Supply Current in Burst Mode with I_VCCburst

inactive Gate

950

V_FB= 2.5V, exclude the

current flowing out from

FB pin

VCC Turn-On Threshold

VCC Turn-Off Threshold

VCC Turn-On/Off Hysteresis

V_VCCon

V_VCCoff

V_VCChys

17.0

9.8

-

18.0

10.5

7.5

19.0

11.2

-

V

4.3.2

Internal Voltage Reference

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

5.20

Internal Reference Voltage

V_REF

4.80

5.00

V

Measured at pin FB

I

_FB=0

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Quasi-Resonant PWM Controller

ICE2QS03

Electrical Characteristics

4.3.3

PWM Section

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

14

typ.

23

max.

Feedback Pull-Up Resistor

PWM-OP Gain

R_FB

33

-

k

-

G_PWM

V_PWM

t_OnMax

3.18

0.63

22

3.3

0.7

30

Offset for Voltage Ramp

-

V

Maximum on time in normal

operation

41

s

4.3.4

Current Sense

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

Peak current limitation in normal V_CSth

operation

0.97

1.03

1.09

V

Leading Edge Blanking time

t_LEB

200

330

460

ns

V

Peak Current Limitation in

Active Burst Mode

V_CSB

0.29

0.34

0.39

4.3.5

Soft Start

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

12

max.

Soft-Start time

t_SS

8.5

-

ms

V

1)

soft-start time step

t_{SS_S}

-

3

1)

Internal regulation voltage at

first step

V_SS1

1.76

1)

Internal regulation voltage step V_{SS_S}

at soft start

-

0.56

-

V

1)

The parameter is not subjected to production test - verified by design/characterization

4.3.6

Parameter

Foldback Point Correction

Symbol

Limit Values

Unit

Test Condition

min.

0.35

1.8

-

typ.

0.5

2

max.

ZC current first step threshold

ZC current last step threshold

CS threshold minimum

I_{ZC_FS}

I_{ZC_LS}

V_CSMF

0.621

2.2

-

mA

V

0.66

I_zc=2.2mA, V_FB=3.8V

Version 2.1

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Quasi-Resonant PWM Controller

ICE2QS03

Electrical Characteristics

4.3.7

Digital Zero Crossing

Symbol

Parameter

Limit Values

Unit

Test Condition

min.

50

typ.

100

0.7

max.

Zero crossing threshold voltage V_ZCCT

Ringing suppression threshold V_ZCRS

170

-

mV

V

-

Minimum ringing suppression

time

t_ZCRS1

t_ZCRS2

V_FBR1

V_FBZHL

1.8

2.5

3.4

s

V_ZC> V_ZCRS

V_ZC< V_ZCRS

Maximum ringing suppression

time

-

25

-

s

V

Threshold to set Up/Down

Counter to one

3.9

3.2

2.5

2.9

2.3

1.3

0.8

48

Threshold for downward

counting at low line

V

Threshold for upward counting V_FBZLL

at low line

V

Threshold for downward

counting at hig line

V_FBZHH

V

Threshold for upward counting V_FBZLH

at highline

V

ZC current for IC switch

threshold to high line

I_ZCSH

-

mA

ms

s

ZC current for IC switch

threshold to low line

Counter time¹⁾

I_ZCSL

t_COUNT

Maximum restart time in normal t_OffMax

operation

30

42

57.5

1)

The parameter is not subjected to production test - verified by design/characterization

Version 2.1

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April 21, 2011

Quasi-Resonant PWM Controller

ICE2QS03

Electrical Characteristics

4.3.8

Active Burst Mode

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

Feedback voltage for entering

Active Burst Mode

V_FBEB

-

1.25

-

V

Minimum Up/down value for

entering Active Burst Mode

N_{ZC_ABM}

7

Blanking time for entering Active t_BEB

Burst Mode

-

24

4.5

-

ms

V

Feedback voltage for leaving

Active Burst Mode

V_FBLB

Feedback voltage for burst-on

Feedback voltage for burst-off

V_FBBOn

V_FBBOff

f_sB

3.6

3.0

52

V

Fixed Switching Frequency in

Active Burst Mode

-

kHz

Max. Duty Cycle in Active Burst D_maxB

0.5

Mode

4.3.9

Protection

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

25.0

4.5

max.

VCC overvoltage threshold

V_VCCOVP

V_FBOLP

24.0

26.0

V

Over Load or Open Loop

Detection threshold for OLP

protection at FB pin

Over Load or Open Loop

Protection Blanking Time

t_{OLP_B}

V_ZCOVP

t_ZCOVP

V_CSSW

20

30

44

ms

V

Output Overvoltage detection

threshold at the ZC pin

3.55

3.7

3.84

Blanking time for Output

Overvoltage protection

100

1.68

190

140

s

V

Threshold for short winding

protection

1.63

1.78

Blanking time for short-windding t_CSSW

protection

Over temperature protection¹⁾

-

ns

⁰C

T_jCon

Note: The trend of all the voltage levels in the Control Unit is the same regarding the deviation except V_VCCOVP

Version 2.1

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April 21, 2011

Quasi-Resonant PWM Controller

ICE2QS03

Electrical Characteristics

4.3.10

Gate Drive

Parameter

Symbol

Limit Values

Unit

Test Condition

min.

typ.

max.

Output voltage at logic low

Output voltage at logic high

V_GATElow

V_GATEhigh

-

1.0

V

V_VCC=18V

I

_OUT= 10mA

9.0

10.0

V_VCC=18V

I_OUT= -10mA

Output voltage active shut down V_GATEasd

1.0

V

V_VCC= 7V

I_OUT= 10mA

Rise Time

Fall Time

t_rise

t_fall

-

117

27

-

ns

C_OUT= 1.0nF

V

_GATE= 2V ... 8V

ns

C_OUT= 1.0nF

V_GATE= 8V ... 2V

Version 2.1

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April 21, 2011

Quasi-Resonant PWM Controller

ICE2QS03

Outline Dimension

5

Outline Dimension

PG-DIP-8-6 / PG-DIP-8-9

(Leadfree Plastic Dual In-Line Outline)

Figure 9

PG-DSO-8 (Pb-free lead plating Plastic Dual Small Outline)

Dimensions in mm

Version 2.1

18

April 21, 2011

Total Quality Management

Qualität hat für uns eine umfassende

Bedeutung. Wir wollen allen Ihren Ansprüchen in

der bestmöglichen Weise gerecht werden. Es

geht uns also nicht nur um die Produktqualität –

unsere Anstrengungen gelten gleichermaßen

der Lieferqualität und Logistik, dem Service und

Support sowie allen sonstigen Beratungs- und

Betreuungsleistungen.

Throughout the corporation we also think in

terms of Time Optimized Processes (top),

greater speed on our part to give you that

decisive competitive edge.

Give us the chance to prove the best of

performance through the best of quality – you will

be convinced.

Dazu gehört eine bestimmte Geisteshaltung

unserer Mitarbeiter. Total Quality im Denken und

Handeln gegenüber Kollegen, Lieferanten und

Ihnen, unserem Kunden. Unsere Leitlinie ist jede

Aufgabe mit „Null Fehlern“ zu lösen – in offener

Sichtweise auch über den eigenen Arbeitsplatz

hinaus – und uns ständig zu verbessern.

Unternehmensweit orientieren wir uns dabei

auch an „top“ (Time Optimized Processes), um

Ihnen durch größere Schnelligkeit den

entscheidenden Wettbewerbsvorsprung zu

verschaffen.

Geben Sie uns die Chance, hohe Leistung durch

umfassende Qualität zu beweisen.

Wir werden Sie überzeugen.

Quality

takes

on

an

allencompassing

significance at Semiconductor Group. For us it

means living up to each and every one of your

demands in the best possible way. So we are not

only concerned with product quality. We direct

our efforts equally at quality of supply and

logistics, service and support, as well as all the

other ways in which we advise and attend to you.

Part of this is the very special attitude of our staff.

Total Quality in thought and deed, towards co-

workers, suppliers and you, our customer. Our

guideline is “do everything with zero defects”, in

an open manner that is demonstrated beyond

your immediate workplace, and to constantly

improve.

h t t p : / / w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG


型号：	ICE2QS03_11
厂家：	Infineon
描述：	Quasi-Resonant PWM Controller 准谐振PWM控制器控制器
文件：	总19页 (文件大小：664K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICE2QS03_11 [INFINEON]

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