ICE5AR3995BZ_技术文档

ICE5xRxxxxxZ

Fixed-frequency 800 V / 950 V CoolSET™

in DIP-7 package

Features



Integrated 800 V / 950 V avalanche rugged CoolMOS™

Enhanced Active Burst mode with selectable entry and

exit standby power



Digital frequency reduction for better overall system efficiency

Fast startup achieved with cascode configuration

DCM and CCM operation with slope compensation

Frequency jitter and soft gate driving for low EMI

Built-in digital soft start

PG-DIP-7

Integrated error amplifier to support direct feedback

in non-isolated flyback and buck topologies



Comprehensive protection with input line overvoltage, V_CC

overvoltage, V_CCundervoltage, overload, open loop and

overtemperature



All protections are in auto restart mode

Limited charging current for V_CCshort to GND

Pb-free lead plating, halogen-free mold compound, RoHS-compliant

Potential applications



Auxiliary power supply for home appliances, white goods, TV, PC and server, smart metering

Blu-ray players, set-top boxes, and LCD/LED monitors

Product validation

Fully qualified according to JEDEC for Industrial Applications.

Description

The ICE5xRxxxxxZ is the fifth-generation of fixed-frequency integrated power IC (CoolSET™) optimized for off-

line switch-mode power supplies in cascode configuration. The CoolSET™ package contains two separate

chips. One is the controller chip and the other is the 800 V / 950 V CoolMOS™ chip. The cascode configuration

helps achieve fast startup. The frequency reduction with soft gate driving and frequency jitter operation offers

lower EMI and better efficiency between a light load and 50% load. The selectable entry and exit standby power

ABM enables flexibility and ultra-low power consumption in standby mode with small and controllable output

voltage ripple. The product has a wide operating range (10.0 V to 25.5 V) of IC power supply and lower power

consumption. The numerous protection functions support the power supply system in failure situations. All

these make the fifth-generation CoolSET™ series an outstanding integrated power stage fixed frequency

flyback and buck converter in the market.

Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

page 1 of 40

Rev 1.1

2022-07-19

Fixed-frequency 800 V / 950 V CoolSET™

in DIP-7 package

W_p

W_a

L_f1

L_f2

D_O1

W_s1

C_bus

Snubber

D_VCC

R_STARTUP

R_VCC

V_O1

C_f1

C_f2

C_O1

85 ~ 300 VAC

C_VCC

D_O2

W_s2

C_O2

V_O2

D_r1~D_r4

DRAIN

VCC

GATE

R_I1

VIN

R_I2

C_PS

CoolMOS^TM

Power Management

D

PWM controller

Current Mode Control

Cycle-by-Cycle

current limitation

Gate

Driver

R_b1

R_b2

R_c1

# R_ovs3

R_ovs1

GND

R_CS

CS

Digital Control

FB

C₂

Active Burst Mode

Protections

Control Unit

ICE5xRxxxxCZ CoolSET^TM

# Optional

R_Sel(Burst mode detect)

C_c1C_c2

R_ovs2

TL431

R_ovs3(V₀₂feedback)

Optocoupler

Figure 1

Typical application in isolated flyback using TL431 and optocoupler

W_p

L_f1

D_O1

W_s1

C_bus

Snubber

D_VCC

R_STARTUP

R_VCC

V_O1

C_f1

C_O1

85 ~ 300 VAC

C_VCC

W_a

D_P1

D_r1~D_r4

DRAIN

VCC

D

GATE

L_fP1

CoolMOS^TM

V_P1

W_P1

C_P1

C_fP1

Power Management

C_PS

PWM controller

Current Mode Control

Cycle-by-Cycle

current limitation

Gate

Driver

GND

R_CS

CS

R_F2

Digital Control

Error Amplifier

VERR

FB

R_F1

Active Burst Mode

R₁

C₁

Control Unit

ICE5xRxxxxBZ CoolSET^TM

# Optional

R_Sel(Burst mode detect)

C₂

Protections

Figure 2

Typical application in non-isolated flyback utilizing integrated error amplifier

ICE5BRxxxxBZ CoolSET^TM

DRAIN

GATE

FB

VCC

VERR

CS

C_vcc

R_cs

D_aux

D2

R_h

R_startup

AC line

C_in

C_fb

R_l

C1

R1

GND

L1

C_out

*Rs

C2

D1

*Rs is recommended to avoid saturation of inductor (L1) during output short circuit

Figure 3

Typical application in non-isolated buck

Datasheet

2 of 40

Rev 1.1

2022-07-19

Fixed-frequency 800 V / 950 V CoolSET™

in DIP-7 package

Output power of fifth-generation fixed-frequency CoolSET™ in flyback design

Table 1

Output power of fifth-generation fixed-frequency CoolSET™ in flyback design

220 V AC

85-300 V AC²85-300 V AC²

1

Type

Package

Marking

V_DS

F_sw

R_DSon

±20%²at DCM at DCM

at CCM

16.5 W

18 W

ICE5BR4780BZ

ICE5BR3995BZ

ICE5BR3995CZ

ICE5AR3995BZ

ICE5BR2280BZ

ICE5AR2280CZ

PG-DIP-7

5BR4780BZ

5BR3995BZ

5BR3995CZ

5AR3995BZ

5BR2280BZ

5AR2280CZ

800 V

950 V

800 V

65 kHz

100 kHz

65 kHz

100 kHz

4.13 Ω

3.46 Ω

2.13 Ω

27.5 W

30 W

40 W

15 W

16.5 W

22 W

18 W

24 W

22 W

24 W

Output current of fifth-generation fixed-frequency CoolSET™ in non-isolated buck design

Infineon® recommends the 65 kHz variant for a non-isolated Buck converter.

Table 2

Output current of fifth-generation generation fixed-frequency CoolSET™ in non-isolated

buck design

85-265 V AC³

at DCM

Typical output

voltage

1

Type

Package

Marking

V_DS

Fsw

R_DSon

ICE5BR4780BZ

ICE5BR3995BZ

ICE5BR2280BZ

PG-DIP-7

5BR4780BZ

5BR3995BZ

5BR2280BZ

800 V

950 V

800 V

65 kHz

4.13 Ω

3.46 Ω

2.13 Ω

450 mA

550 mA

700 mA

15 V

¹Typically at T_i= 25°C (inclusive of low side MOSFET).

²Calculated maximum output power rating in an open frame design at T_a= 50°C, T_j= 125°C (integrated high voltage MOSFET) and using

minimum drain pin copper area in a 2 oz copper single-sided PCB. The output power figure is for selection purpose only. The actual

power can vary depending on the designs. Contact a technical expert from Infineon® for more information.

³Calculated maximum output currrent rating in an open frame design at T_a= 50°C, T_j= 125°C (integrated high voltage MOSFET) and using

minimum 100mm²drain pin copper area in a 2 oz copper single-sided PCB. The output current figure is for selection purpose only.

The actual current can vary depending on the designs. Contact a technical expert from Infineon® for more information.

Datasheet

3 of 40

Rev 1.1

2022-07-19

Fixed-frequency 800 V / 950 V CoolSET™

in DIP-7 package

Table of contents

Table of contents............................................................................................................................ 4

1

2

Block diagram........................................................................................................................ 6

Pin configuration ................................................................................................................... 7

3

Functional description............................................................................................................ 8

V_CCprecharging and typical V_CCvoltage during startup .........................................................................8

Soft start ..................................................................................................................................................9

Normal operation....................................................................................................................................9

PWM operation and peak current mode control ..............................................................................9

3.1

3.2

3.3

3.3.1

3.3.1.1

3.3.1.2

3.3.2

3.3.3

3.3.4

3.3.5

3.3.6

3.4

Switch-on determination..............................................................................................................9

Switch-off determination .............................................................................................................9

Current sense ...................................................................................................................................10

Frequency reduction........................................................................................................................11

Slope compensation ........................................................................................................................11

Oscillator and frequency jittering....................................................................................................12

Modulated gate drive .......................................................................................................................12

Peak current limitation .........................................................................................................................12

Propagation delay compensation ...................................................................................................13

Active burst mode with selectable power level ...................................................................................14

Entering ABM operation...................................................................................................................14

During ABM operation......................................................................................................................14

Leaving ABM operation ....................................................................................................................14

ABM configuration............................................................................................................................16

Non-isolated/isolated configuration....................................................................................................16

Protection functions .............................................................................................................................17

Line overvoltage (CZ version) ..........................................................................................................17

V_CCovervoltage and undervoltage...................................................................................................17

Overload or open loop .....................................................................................................................17

Overtemperature .............................................................................................................................17

V_CCshort to GND................................................................................................................................18

Protection modes.............................................................................................................................18

3.4.1

3.5

3.5.1

3.5.2

3.5.3

3.5.4

3.6

3.7

3.7.1

3.7.2

3.7.3

3.7.4

3.7.5

3.7.6

4

Electrical characteristics........................................................................................................20

Absolute maximum ratings...................................................................................................................20

Operating range ....................................................................................................................................21

Operating conditions ............................................................................................................................21

Internal voltage reference.....................................................................................................................22

PWM section ..........................................................................................................................................22

Error amplifier .......................................................................................................................................23

Current sense.........................................................................................................................................23

Soft start ................................................................................................................................................24

Active burst mode .................................................................................................................................24

Line overvoltage protection (CZ version).............................................................................................25

V_CCovervoltage protection....................................................................................................................25

Overload protection..............................................................................................................................25

Thermal protection ...............................................................................................................................25

CoolMOS™ section.................................................................................................................................26

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

4.11

4.12

4.13

4.14

5

CoolMOS™ performance characteristics...................................................................................27

6

Output power curve ..............................................................................................................33

Datasheet

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Fixed-frequency 800 V / 950 V CoolSET™

in DIP-7 package

Table of contents

7

Output current curve.............................................................................................................36

8

8.1

Package information .............................................................................................................37

Marking ..................................................................................................................................................38

9

Revision history ....................................................................................................................39

Datasheet

5 of 40

Rev 1.1

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Fixed-frequency 800 V / 950 V CoolSET™

in DIP-7 package

Block diagram

1

Block diagram

VCC

GATE DRAIN

Power Management

Line Overvoltage Protection

Thermal Protection

50 µs

CZ Version

250 µs

Blanking

time

Undervoltage Lockout

16.0V

Internal

Bias

T_j> T_{jcon_OTP}

Blanking

time

S

R

V_{VIN_LOVP}

Voltage

Reference

Q

C7a

Input

OVP

OTP

Mode

S

R

Q

10.0V

VIN

Mode

100 ns

Blanking

time

T_j< T_{jcon_OTP}-T_{jHYS_OTP}

Autorestart

Protect

C20

t_{VCC_OVP_B}

Autorestart

Protect

V_{VCC_OVP}

f_{OSC_2}

Error Amplifier

OSC with

Jitter and

Frequency

Reduction

BZ Version

Non-

Isolated

Detector

f_OSC

OSC

D1

VERR

ERR

V_{ERR_REF}

Gate Driver

Gate

Drive

V_REF

Protection and PWM Digital Control

R_FB

Overload Protection

Gate

Drive

Burst

Mode

detect

GND

C12

t_{FB_OLP_B}

V_{FB_OLP}

/

V_{FB_LB}

V_{CS_BLP}

V_{CS_BHP}

V_REF

C13

FB

Slope

Comp

Active Burst Block

Peak current

limit

Burst Mode

Level Select

V_{CS_Nx}

Leading

Edge

10kΩ

C15

V_{FB_EBHP}

V_{FB_EBLP}

CS

Blanking

t_{CS_LEB}

Active

Burst Mode

1pF

D2

No burst

C9

t_{FB_BEB}

PWM

Comparator

C15a

C_PWM

2pF

V₁

C10

C11

Soft-start

V_{FB_BOn}

PWM OP

G_PWM

Delay

t_{CS_STG}

C19

V_PWM

Current Mode

V_{CS_STG}

V_{FB_BOff}

Slope Compensation/Current Limiting

Figure 4

Block diagram

Note:

Junction temperature of the controller chip is sensed for overtemperature protection. The

CoolMOS^TMis a separate chip from the controller chip in the same package. Refer to the design

guide or consult a technical expert for the proper thermal design.

Datasheet

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Fixed-frequency 800 V / 950 V CoolSET™

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Pin configuration

2

Pin configuration

The pin configuration is shown in Figure 5 and the functions are described in Table 3.

Figure 5

Pin configuration

Table 3

Pin definitions and functions

Function

Pin Symbol

Error amplifier

VERR

(BZ version)

VERR pin is internally connected to the transconductance error amplifier for a non-

isolated converter. Connect this pin to GND for an isolated converter.

1

Input line overvoltage protection (LOVP)

VIN

VIN pin is connected to the bus via a resistor divider (see Figure 1) to sense the line

(CZ version) voltage. Internally, it is connected to the line overvoltage comparator which stops the

switching when a LOVP condition occurs. To disable LOVP, connect this pin to GND.

Feedback and ABM entry and exit control

2

3

FB

FB pin combines the functions of feedback control, selectable burst entry/exit control

and overload/open loop protection.

Current sense

The CS pin is connected to the shunt resistor for the primary current sensing externally

and to the PWM signal generator block for switch-off determination (together with the

feedback voltage) internally.

CS

Gate driver output

The GATE pin is connected to the Gate of the internal CoolMOS™ and additionally, a pull-

up resistor is connected from a bus voltage to turn on the internal CoolMOS™ for charging

up the V_CCcapacitor during startup.

4

GATE

DRAIN (Drain of integrated CoolMOS™)

The DRAIN pin is connected to the drain of the integrated CoolMOS™.

VCC (Positive voltage supply)

5

7

8

DRAIN

VCC

The VCC pin is the positive voltage supply to the IC. The operating range is between

V_{VCC_OFF}and V_{VCC_OVP}

.

Ground

GND

The GND pin is the common ground of the controller.

Datasheet

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Fixed-frequency 800 V / 950 V CoolSET™

in DIP-7 package

Functional description

3

Functional description

3.1

V_CCprecharging and typical V_CCvoltage during startup

As shown in Figure 1, once the line input voltage is applied, a rectified voltage appears across the capacitor

C_BUS.The pull-up resistor R_STARTUPprovides a current to charge the C_iss(input capacitance) of CoolMOS™ and

gradually generate one voltage level. If the voltage over C_issis high enough, CoolMOS™ and the V_CCcapacitor are

charged through the primary inductance of a transformer L_P,CoolMOS™ and the internal diode D₁with the two

1

steps constant current source I_{VCC_ Charge1}¹and I_{VCC_ Charge3}

.

A very small constant current source (I_{VCC_Charge1}) is charged to the V_CCcapacitor until V_CCreaches V_{CC_SCP}to protect

the controller from the V_CCpin short to ground during the startup. After this, the second step constant current

source (I_{VCC_Charge3}) is provided to charge the V_CCcapacitor further, until the V_CCvoltage exceeds the turned-on

threshold V_{VCC_ON}. As shown in the time phase I in Figure 6, the V_CCvoltage increases almost linearly with two

steps.

V_VCC

I

II

III

V_{VCC_ON}

V_{VCC_OFF}

V_{VCC_SCP}

t_A

t_B

t

I_VCC

I_{VCC_Normal2}

t

0

I_{VCC_Charge1}

I_{VCC_Charge2/3}

-I_VCC

t1 t2

Figure 6

The time for the V_CCprecharging can then be calculated as:

푉_{ꢀ퐶퐶_푆퐶푃}× ꢁ_ꢀ퐶퐶(푉_{ꢀ퐶퐶_푂푁}− 푉_{ꢀ퐶퐶_푆퐶푃}) × ꢁ_ꢀ퐶퐶

V_CCvoltage and current at startup

(1)

푡₁= 푡_A+ 푡_B=

+

퐼_{ꢀ퐶퐶_퐶ℎ푎푟ꢂ푒1}

퐼_{ꢀ퐶퐶_퐶ℎ푎푟ꢂ푒3}

When the V_CCvoltage exceeds the V_CCturn on threshold V_{VCC_ON}at time t₁, the IC starts to operate with soft start.

Due to the power consumption of the IC and the fact that there is still no energy from the auxiliary winding to

charge the V_CCcapacitor before the output voltage is built up, the V_CCvoltage drops (phase II). Once the output

voltage rises close to regulation, the auxiliary winding starts to charge the V_CCcapacitor from the time t₂onward

and delivering the I_{VCC_ Normal2}²to the CoolSET™. V_CCthen reaches a constant value depending on the output load.

¹I_{VCC_ Charge1/2/3}is charging current from the controller to VCC capacitor during startup.

²I_{VCC_ Normal2}is supply current from VCC capacitor or auxiliary winding to the CoolSET™ during normal operation.

Datasheet

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Fixed-frequency 800 V / 950 V CoolSET™

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Functional description

3.2

Soft start

As shown in Figure 7, the IC starts to operate with a soft start at time t_on. The switching stresses on the power

MOSFET, diode, and transformer are minimized during soft start. The soft start implemented in ICE5xRxxxxxZ is

a digital time-based function. The preset soft start time is t_SS(12 ms) with four steps. If not limited by other

functions, the peak voltage on CS pin increases step by step from 0.3 V to finally V_{CS_N}(0.8 V). The normal

feedback loop takes over the control when the output voltage reaches its regulated value.

Figure 7

Maximum current sense voltage during soft start

3.3

Normal operation

The PWM controller during normal operation consists of a digital signal processing circuit including regulation

control and an analog circuit including a current measurement unit and a comparator. Details about the full

operation of the CoolSET™ in normal operation are illustrated in the following paragraphs.

3.3.1

PWM operation and peak current mode control

3.3.1.1

Switch-on determination

The power MOSFET turn-on is synchronized with the internal oscillator with a switching frequency F_SWthat

corresponds to the voltage level V_FB(see Figure 9).

3.3.1.2

Switch-off determination

In peak current mode control, the PWM comparator monitors voltage V₁(see Figure 4), which represents the

instantaneous current of the power MOSFET. When V₁exceeds V_FB, the PWM comparator sends a signal to

switch off the GATE of the power MOSFET. Therefore, the peak current of the power MOSFET is controlled by

the feedback voltage V_FB(see Figure 8).

At switch-on transient of the power MOSFET, a voltage spike across R_CScan cause V₁to increase and exceed V_FB.

To avoid a false switch off, the IC has a blanking time t_{CS_LEB}before detecting the voltage across R_CSto mask the

voltage spike. Therefore, the minimum turn on time of the power MOSFET is t_{CS_LEB}

.

If the voltage level at V₁takes a long time to exceed V_FB, the IC has implemented a maximum duty cycle control

to force the power MOSFET to switch off when D_MAX= 0.75 is reached.

Datasheet

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Fixed-frequency 800 V / 950 V CoolSET™

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Functional description

Figure 8

Pulse width modulation

3.3.2

Current sense

The power MOSFET current generates a voltage V_CSacross the current sense resistor R_CSconnected between the

CS pin and the GND pin. V_CSis amplified with gain G_PWM, then, added with an offset V_PWMto become V₁as

described below in equation 3.

푉_CS= 퐼_D× 푅_CS

(2)

(3)

푉 = 푉_CS× 퐺_PWM+ 푉_PWM

1

where:

V_CS

I_D

: CS pin voltage

: Power MOSFET current

R_CS

V₁

: Resistance of the current sense resistor

: Voltage level compared to V_FBas described in chapter 3.3.1.2

G_PWM: PWM-OP gain

V_PWM: Offset for voltage ramp

Datasheet

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Fixed-frequency 800 V / 950 V CoolSET™

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Functional description

If the voltage at the current sense pin is lower than the preset threshold V_{CS_STG}after the time t_{CS_STG_SAM}for three

consecutive pulses during on-time of the power switch, this abnormal V_CStriggers the IC into auto restart mode.

3.3.3

Frequency reduction

Frequency reduction is implemented in ICE5xRxxxxxZ to achieve a better efficiency during the light load.

At light load, the reduced switching frequency F_SWimproves efficiency by reducing the switching loses.

When the load decreases, V_FBdecreases as well. F_SWis dependent on the V_FBas shown in Figure 9. Therefore, F_SW

decreases as the load decreases.

For example, F_SWat high load is 65 kHz and starts to decrease at V_FB= 1.7 V. There is no further frequency

reduction once it reached the f_{OSC2_MIN}even the load is further reduced.

f_SW(V_FB)

V_CS(V_FB)

Vcs

V_{CS_N}

0.80 V

f_OSC2/f_OSC4

Fsw

65 kHz / 100 kHz

f_{OSC2_ABM}/ f_{OSC4_ABM}

BM

54 kHz / 83 kHz

No BM

BM

f_{OSC2_MIN}/ f_{OSC4_MIN}

28 kHz / 43 kHz

V_{CS_BHP /}V_{CS_BLP}

0.27 V /0.22 V

No BM

V_FB

V_{FB_EBxP}

0.5 V 0.93 / 1.03 V 1.35 V

V_{FB_OLP}

2.73 V

1.7 V

Figure 9

Frequency reduction curve

3.3.4

Slope compensation

ICE5xRxxxxxZ can operate at continuous conduction mode (CCM). At CCM operation, a duty cycle greater than

50% may generate a subharmonic oscillation. To avoid the subharmonic oscillation, slope compensation is

added to V_CSpin when the gate of the power MOSFET is turned on for more than 40% of the switching cycle

period.

The relationship between V_FBand the V_CSfor CCM operation is described in equation 4:

푉_FB= 푉_CS× 퐺_PWM+ 푉_PWM+ 푀_COMP× (푇_ON− 40% × 푇_PERIOD

)

(4)

where:

T_ON

: Gate turn on time of the power MOSFET

Datasheet

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Fixed-frequency 800 V / 950 V CoolSET™

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Functional description

M_COMP: Slope compensation rate

T_PERIOD: Switching cycle period

Slope compensation circuit is disabled and no slope compensation is added into the V_CSpin during Active Burst

mode to save the power consumption.

3.3.5

Oscillator and frequency jittering

The oscillator generates a frequency of 65 kHz / 100 kHz with frequency jittering of ±4% at a jittering period of

T_JITTER(4 ms). The frequency jittering helps to reduce conducted EMI.

A capacitor, a current source, and a current sink that determine the frequency are integrated. The charging and

discharging current of the implemented oscillator capacitor are internally trimmed to achieve a highly accurate

switching frequency.

Once the soft start period is over and when the IC goes into normal operating mode, the frequency jittering is

enabled. There is also frequency jittering during frequency reduction.

3.3.6

Modulated gate drive

The drive-stage is optimized for EMI consideration. The switch-on speed is slowed down before it reaches the

CoolMOS™ turn on threshold. That is a slope control of the rising edge at the output of the driver (see Figure

10). Thus the leading switch spike during turn on is minimized.

Figure 10

Gate rising waveform

3.4

Peak current limitation

There is a cycle-by-cycle peak current limitation realized by the current limit comparator to provide primary

over-current protection. The primary current generates a voltage V_CSacross the current sense resistor R_CS

connected between the CS pin and the GND pin. If the voltage V_CSexceeds an internal voltage limit V_{CS_N}, the

comparator immediately turns off the gate drive.

The primary peak current I_{PEAK_PRI}can be calculated as below:

⁄

퐼_{PEAK_PRI}= 푉_{CS_N}푅_CS

(5)

To avoid mistriggering caused by the MOSFET switch on transient voltage spikes, a leading edge-blanking time

(t_{CS_LEB}) is integrated in the current sensing path.

Datasheet

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Fixed-frequency 800 V / 950 V CoolSET™

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Functional description

3.4.1

Propagation delay compensation

In case of an overcurrent detection, there is always a propagation delay from sensing the V_CSto switching the

power MOSFET off. An overshoot on the peak current I_peakcaused by the delay depends on the ratio of dI/dt of

the primary current (see Figure 11).

Figure 11 Current limiting

The overshoot of Signal2 is larger than Signal1 due to the steeper rising waveform. This change in the slope is

depending on the AC input voltage. Propagation delay compensation is integrated to reduce the overshoot due

to dI/dt of the rising primary current. Thus the propagation delay time between exceeding the current sense

threshold V_{CS_N}and the switching off of the power MOSFET is compensated over wide bus voltage range.

Current limiting becomes more accurate, which results in a minimum difference of overload protection

triggering power between low and high AC line input voltage.

Under CCM operation, the same V_CSdo not result in the same power. To achieve a close overload triggering level

for CCM, ICE5xRxxxxxZ has implemented a two compensation curve as shown Figure 12. One of the curve is

used for T_ONgreater than 0.40 duty cycle and the other is for lower than 0.40 duty cycle.

Figure 12 Dynamic voltage threshold V_{CS_N}

Datasheet

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Fixed-frequency 800 V / 950 V CoolSET™

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Functional description

Similarly, the same concept of propagation delay compensation is also implemented in ABM with reduced

level. With this implementation, the entry and exit Burst mode power can be close between low and high AC

line input voltage.

3.5

Active burst mode with selectable power level

At light load condition, the IC enters Active Burst mode (ABM) operation to minimize the power consumption.

Details about the ABM operation are explained in the following paragraphs.

3.5.1

Entering ABM operation

The system enters into ABM operation when the two conditions below are met:



The FB voltage is lower than the threshold of V_{FB_EBLP}/V_{FB_EBHP,}depending on the burst configuration option

setup.



A certain blanking time t_{FB_BEB}

.

Once all of these conditions are fulfilled, the ABM flip-flop is set and the controller enters ABM operation. This

multicondition determination for entering ABM operation prevents mis-triggering of entering ABM operation,

so that the controller enters ABM operation only when the output power is really low.

3.5.2

During ABM operation

After entering ABM, the PWM section is inactive, making the V_OUTstart to decrease. As the V_OUTdecreases, V_FB

rises. Once V_FBexceeded V_{FB_BOn}, the internal circuit is again activated by the internal bias to start with the

switching.

If the PWM is still operating and the output load is still low, V_OUTincreases and V_FBsignal starts to decrease.

When V_FBreaches the low threshold V_{FB_BOff}, the internal bias is reset again and the PWM section is disabled with

no switching until V_FBincreases back to exceed V_{FB_BOn}threshold.

In ABM, V_FBis like a sawtooth waveform swinging between V_{FB_BOff}and V_{FB_BOn}shown in Figure 13.

During ABM, the peak current I_{PEAK_ABM}of the power MOSFET is defined by:

⁄

퐼_{PEAK_ABM}= 푉_{CS_BxP}푅_CS

(6)

where V_{CS_BxP}is the peak current limitation in ABM.

3.5.3

Leaving ABM operation

The FB voltage immediately increases if there is a sudden increase in the output load. When V_FBexceeds V_{FB_LB,}it

leaves ABM and the peak current limitation threshold voltage returns back to V_{CS_N}immediately.

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V_FB

Entering Active Burst Mode

V_{FB_LB}

Leaving Active Burst Mode

V_{FB_BOn}

V_{FB_BOff}

V_{FB_EBHP}/V_{FB_EBLP}

Blanking Window (t_{FB_BEB}

)

t

V_CS

V_{CS_N}

Current limit level during Active Burst Mode

V_{CS_BHP}/V_{CS_BLP}

t

V_VCC

V_{VCC_off}

t

V_O

Max. Ripple < 1%

t

Burst Mode Operation

Figure 13

Signals in ABM

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3.5.4

ABM configuration

The burst mode entry level can be selected by changing the different resistance R_Selat FB pin. There are three

configuration options depending on R_Sel, which corresponds to the options of no ABM (option 1), low range of

ABM power (option 2) and high range of ABM power (option 3). The table below shows the control logic for the

entry and exit level with the FB voltage.

Table 4

Option

ABM configuration option setup

R_Sel

V_FB

V_{CS_BxP}

Entry level

V_{FB_EBxP}

Exit level

V_{FB_LB}

1

2

< 470 kΩ

V_FB< V_{FB_P_BIAS1}

-

No ABM

0.93 V

No ABM

2.73 V

720 kΩ ~ 790 kΩ

V_{FB_P_BIAS1}< V_FB< V_{FB_P_BIAS2}0.22 V

V_FB> V_{FB_P_BIAS2}0.27 V

3 (default) > 1210 kΩ

1.03 V

2.73 V

During IC first startup, the controller preset the ABM selection to option 3, the FB resistor (R_FB) is turned off by

internal switch S2 (see Figure 14) and a current source I_selis turned on instead. From V_CC= 4.44 V to V_CCon

threshold, the FB pin starts to charge resistor R_Selwith current I_Selto a certain voltage level. When V_CCreaches V_CC

on threshold, the FB voltage is sensed. The burst mode option is then chosen according to the FB voltage level.

After finishing the selection, any change on the FB level does not change the burst mode option and the current

source (I_sel) is turned off while the FB resistor (R_FB) is connected back to the circuit (Figure 14).

Figure 14

ABM detect and adjust

3.6

Non-isolated/isolated configuration

ICE5xRxxxxBZ has a VERR pin, which is connected to the input of an integrated error amplifier to support a non-

isolated converter (see Figure 2). When V_CCis charging and before reaching the V_CCon threshold, a current

source I_{ERR_P_BIAS}from the VERR pin together with R_F1and R_F2generates a voltage across it. If the VERR voltage is

more than V_{ERR_P_BIAS}(0.2 V), non-isolated configuration is selected, otherwise, isolated configuration is selected.

In an isolated configuration, the error amplifier output is disconnected from the FB pin.

In case of non-isolated configuration, the voltage divider R_F1and R_F2are used to sense the output voltage and

compared with the internal reference voltage V_{ERR_REF}. The difference between the sensed voltage and the

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Functional description

reference voltage is converted as an output current by the error amplifier. The output current charges or

discharges the resistor and capacitor network connected at the FB pin for the loop compensation.

3.7

Protection functions

The ICE5xRxxxxxZ provides numerous protection functions that considerably improve the power supply system

robustness, safety, and reliability. The following table summarizes these protection functions and the

corresponding protection mode whether as a non-switch auto restart, auto restart or odd skip auto restart

mode. Refer to Figure 15, Figure 16 and Figure 17 for the waveform illustration of protection modes.

Table 5

Protection functions

Normal mode

Burst mode

Protection mode

Burst ON

Burst OFF

Line overvoltage (CZ version)

V_CCovervoltage

√

n/a¹

Non-switch auto restart

Odd skip auto restart

Auto restart

V_CCundervoltage

√

n/a¹

√

Overload or open loop

Overtemperature

n/a¹

√

Odd skip auto restart

Non-switch auto restart

No startup

√

V_CCshort to GND

√

3.7.1

Line overvoltage (CZ version)

The AC line overvoltage protection (LOVP) is detected by the sensing bus capacitor voltage through the VIN pin

via the voltage divider resistors, R_l1and R_l2(Figure 1). Once the V_VINvoltage is higher than the line overvoltage

threshold (V_{VIN_LOVP}), the controller enters into protection mode until V_VINis lower than V_{VIN_LOVP}. This protection

can be disabled by connecting the VIN pin to GND.

3.7.2

V_CCovervoltage and undervoltage

During operation, the V_CCvoltage is continuously monitored. If V_CCis either below V_{VCC_OFF}for 50 µs (t_{VCC_OFF_B}) or

above V_{VCC_OVP}for 55 µs (t_{VCC_OVP_B}), the power MOSFET is kept switch off. After the V_CCvoltage falls below the

threshold V_VCCoff, the new startup sequence is activated. The V_CCcapacitor is then charged up. Once the voltage

exceeds the threshold V_{VCC_ON}, the IC begins to operate with a new soft start.

3.7.3

Overload or open loop

In case of open control loop or output overload, the FB voltage is pulled up. When V_FBexceeds V_{FB_OLP}after a

blanking time of t_{FB_OLP_B}, the IC enters odd skip auto restart mode. The blanking time enables the converter to

provide a peak power in case the increase in V_FBis due to a sudden load increase.

3.7.4

Overtemperature

If the junction temperature of the controller exceeds T_{jcon_OTP}, the IC enters into overtemperature protection

(OTP) auto restart mode. The IC has also implemented with a 40°C hysteresis. That means the IC can only be

recovered from OTP when the controller junction temperature is dropped 40°C lower than the

overtemperature trigger point.

¹Not applicable.

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3.7.5

V_CCshort to GND

To limit the power dissipation of the startup circuit at V_CCshort to GND condition, the V_CCcharging current is

limited to a minimum level of I_{VCC_ Charge1}. With such low current, the power loss of the IC is limited to prevent

overheating.

3.7.6

Protection modes

All the protections are in auto restart mode with a new soft start sequence. The three auto restart modes are

illustrated in the following figures.

Fault

Fault released

detected

Switching start at the

following restart cycle

Start up and detect at

every charging cycle

V_VCC

V_{CC_ON}

V_{CC_OFF}

t

V_CS

No switching

Figure 15

Non-switch auto restart mode

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Fault

Fault released

detected

Start up and detect at every

charging cycle

Switching start at the

following restart cycle

t

V_VCC

V_{CC_ON}

V_{CC_OFF}

t

V_CS

Figure 16

Auto restart mode

Fault

detected

Fault released

Start up and detect at

every even charging

cycle

Switching start at the

following even restart

t

V_VCC

No detect

cycle

V_{CC_ON}

V_{CC_OFF}

t

V_CS

Figure 17 Odd skip auto restart

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Electrical characteristics

4

Electrical characteristics

Attention: All voltages are measured with respect to ground (pin 8). The voltage levels are valid if other

ratings are not violated.

4.1

Absolute maximum ratings

Attention: Stresses above the maximum values listed here may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device

reliability. Maximum ratings are absolute ratings; exceeding any one of these values may cause

irreversible damage to the integrated circuit. For the same reason, make sure that any capacitor

that is connected to pin 7 (VCC) is discharged before assembling the application circuit.

T_a= 25°C unless otherwise specified.

Table 6

Absolute maximum ratings

Parameter

Symbol Limit values

Unit Note or

test condition

Min.

Max.

Drain voltage

ICE5xRxx80xZ

ICE5xR3995xZ

V_DRAIN

V

T_j= 25°C

800

950

–

Pulse drain current

ICE5xR3995xZ

ICE5BR4780BZ

ICE5xR2280xZ

I_D,Pulse

A

–

5.0¹

2.6¹

5.8²

Avalanche energy, repetitive, t_ARlimited

by maximal T_j= 150°C and T_j,Start= 25°C

ICE5xR2280xZ

ICE5BR4780BZ

ICE5xR3995xZ

E_AR

mJ

A

–

0.05

0.02

0.04

I_D= 0.40 A, V_DD= 50 V

I_D= 0.20 A, V_DD= 50 V

Avalanche current, repetitive, t_ARlimited

by maximal T_j= 150°C and T_j,Start= 25°C

I_AR

ICE5BR4780BZ

ICE5xR3995xZ

ICE5xR2280xZ

–

0.20

0.40

27.0

3.6

VCC supply voltage

GATE voltage

V_CC

V_GATE

V_FB

-0.3

-10.0

V

FB voltage

V

VERR voltage

V_ERR

V_CS

3.6

V

CS voltage

3.6

V

VIN voltage

V_VIN

3.6

V

Maximum DC current on any pin

10.0

mA

Except DRAIN and CS pin.

¹Pulse width t_Plimited by T_j,max

.

²Pulse width t_P= 20 µs and limited by T_j,max

.

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Electrical characteristics

Parameter

Symbol Limit values

Unit Note or

test condition

Min.

–

Max.

2000

500

ESD robustness HBM

ESD robustness CDM

Junction temperature range

Storage temperature

Thermal resistance (junction-ambient)

ICE5BR4780BZ

V_{ESD_HBM}

V_{ESD_CDM}

T_j

V

According to EIA/JESD22.

–

V

-40

-55

150

°C

Controller and CoolMOS™.

T_STORE

R_thJA

150

K/W Setup according to the

JEDEC standard JESD51

and using minimum drain

pin copper area in a 2 oz

copper single-sided PCB.

–

107

106

104

ICE5xR3995xZ

ICE5xR2280xZ

4.2

Operating range

Note:

Within the operating range, the IC operates as described in the functional description.

Table 7

Operating range

Parameter

Symbol

Limit values

Unit Note or

test condition

Min.

V_{VCC_OFF}

-40

Max.

VCC supply voltage

V_VCC

V_{VCC_OVP}

Junction temperature of controller T_{jCon_op}

T_{jCon_OTP}°C

Maximum value limited due to

OTP of controller chip.

Junction temperature of

T_{jCoolMOS_op}

-40

150

°C

CoolMOS™

4.3

Operating conditions

Note:

The electrical characteristics involve the spread of values within the specified supply voltage and

junction temperature range T_Jfrom – 40°C to 125°C. Typical values represent the median values,

which are related to 25°C. If not otherwise stated, a supply voltage of V_CC= 18 V is assumed.

Table 8

Operating conditions

Parameter

Symbol

Limit values

Min. Typ.

Unit

Note or

test Condition

Max.

VCC charge current

I_{VCC_Charge1}-0.35 -0.20 -0.09 mA

V_VCC= 0 V, R_StartUp= 50 MΩ

and V_DRAIN= 90 V

I_{VCC_Charge2}

–

-3.2

-3

–

mA

V_VCC= 3 V, R_StartUp= 50 MΩ

and V_DRAIN= 90 V

I_{VCC_Charge3}-5

-1

V_VCC= 15 V, R_StartUp= 50 MΩ

and V_DRAIN= 90 V

Current consumption, startup current

I_{VCC_Startup}

I_{VCC_Normal1}

–

0.25

0.9

–

mA

V_VCC= 15 V

I_FB= 0 A

Current consumption, normal with

Inactive Gate

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Parameter

Symbol

Limit values

Min. Typ.

Unit

Note or

test Condition

Max.

Current consumption, normal with

Active Gate

I_{VCC_Normal2}

mA

ICE5BR2280BZ

ICE5BR3995xZ

ICE5AR3995BZ

ICE5BR4780BZ

ICE5AR2280CZ

–

1.89

1.82

2.21

1.69

2.31

–

Current consumption, auto restart

I_{VCC_AR}

410

µA

Current consumption, Burst mode –

I_{VCC_Burst}

–

0.54

–

mA

isolated

Mode_ISO

Current consumption, Burst mode –

I_{VCC_Burst}

–

0.61

–

mA

non-isolated

Mode_NISO

VCC turn-on threshold voltage

VCC turn-off threshold voltage

VCC short circuit protection

VCC turn-off blanking

V_{VCC_ON}

15.3

9.4

–

16.0

10.0

1.1

16.5

10.4

1.9

–

V

V_{VCC_OFF}

V_{VCC_SCP}

t_{VCC_OFF_B}

V

–

50

µs

4.4

Internal voltage reference

Table 9

Internal voltage reference

Parameter

Symbol Limit values

Min. Typ.

Unit Note or

test condition

Max.

Internal reference voltage

V_REF

3.20 3.30

3.39

V

Measured at FB pin

I_FB= 0 A

4.5

PWM section

Table 10

PWM section

Parameter

Symbol

Limit values

Unit

Note or

test condition

Min.

92

Typ.

100

83

Max.

108

106

94

Fixed oscillator frequency –

f_OSC3

kHz

100 kHz

f_OSC4

94

T_j= 25°C

Fixed oscillator frequency –

f_{OSC4_ABM}

71

100 kHz (ABM)

Fixed oscillator frequency –

100 kHz (minimum F_sw)

f_{OSC4_MIN}

36

43

51

kHz

T_j= 25°C

Fixed oscillator frequency –

65 kHz

f_OSC1

59.8

61.1

46.2

65

54

70.2

68.9

61.1

kHz

f_OSC2

T_j= 25°C

Fixed oscillator frequency –

f_{OSC2_ABM}

65 kHz (ABM)

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Parameter

Symbol

Limit values

Unit

Note or

test condition

Min.

Typ.

Max.

Fixed oscillator frequency –

65 kHz (minimum F_sw)

f_{OSC2_MIN}

23.4

28

33.2

kHz

T_j= 25°C

Frequency jittering range

Frequency jittering period

Maximum duty cycle

Feedback pull-up resistor

PWM-OP gain

F_JITTER

T_JITTER

D_MAX

R_FB

–

± 4

4

–

%

T_j= 25°C

–

ms

%

70

11

1.91

0.42

75

80

20

2.16

0.58

15

kΩ

G_PWM

V_PWM

2.03

0.50

Offset for voltage ramp

Slope compensation rate -

100 kHz

V

M_COMP

41

50

58

38

mV/μs

V_cs= 0 V

Slope compensation rate -

65 kHz

26.5

32.5

mV/μs

4.6

Error amplifier

Table 11

Error amplifier

Parameter

Symbol

Limit values

Unit

Note or

test condition

Min.

2.14

6.9

Typ.

2.80

9.2

Max.

Transconductance

G_{ERR_M}

3.44

11.6

223

1.84

3.15

mA/V

μA

Transconductance – Burst mode

Error amplifier source current

Error amplifier sink current

Error amplifier reference voltage

G_{ERR_BM}

I_{ERR_SOURCE}

I_{ERR_SINK}

V_{ERR_REF}

V_{ERR_DYN}

85

150

1.80

–

85

μA

1.76

0.05

V

Error amplifier output dynamic

range of transconductance

V

Error amplifier mode bias current

Error amplifier mode threshold

I_{ERR_P_BIAS}

V_{ERR_P_BIAS}

9.5

14.0

0.20

18.5

0.24

μA

0.16

V

4.7

Current sense

Table 12

Current sense

Parameter

Symbol

Limit values

Unit

Note or

test condition

Min.

Typ.

Max.

Peak current limitation in normal V_{CS_N}

operation

0.72

0.80

0.88

V

dV_sense/dt = 0.41 V/μ s

Peak current limitation in normal V_{CS_N15}

operation, 15% of T_ON

0.74

0.79

0.84

Leading edge-blanking time

t_{CS_LEB}

70

220

0.27

365

ns

V

Peak current limitation in ABM -

high power

V_{CS_BHP}

0.23

0.31

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Peak current limitation in ABM -

low power

V_{CS_BLP}

V_{CS_STG}

0.18

0.22

0.26

V

Abnormal CS voltage threshold

0.06

0.10

3

0.15

V

Abnormal CS voltage consecutive P_{CS_STG}

–

cycle

trigger

Abnormal CS voltage sample

period

t_{CS_STG_SAM}

t_PERIOD

× 0.36 × 0.4

t_PERIOD

t_PERIODµs

× 0.44

4.8

Soft start

Table 13

Soft start

Parameter

Symbol

Limit values

Unit Note or

test condition

Min.

7.3

–

Typ.

12.0

3

Max.

–

Soft start time

Soft start time step

t_SS

t_{SS_S}

ms

1

CS peak voltage at first step of soft V_SS1

start

Step increment of CS peak voltage

in soft start

–

0.30

–

V

CS peak voltage.

1

V_{SS_S}

–

0.15

–

V

4.9

Active burst mode

Table 14

Active Burst mode

Parameter

Symbol

Limit values

Unit Note or

test condition

Min.

Typ.

Max.

Charging current to select burst

mode

I_sel

2.5

3.0

3.5

µA

Burst mode selection reference

voltage threshold

V_{FB_P_BIAS1}

V_{FB_P_BIAS2}

V_{FB_EBHP}

V_{FB_EBLP}

t_{FB_BEB}

1.65

2.76

0.98

0.88

1.73

2.89

1.03

0.93

1.80

3.01

1.08

0.98

V

Burst mode selection reference

voltage threshold

V

Feedback voltage for entering

ABM for high power

V

Feedback voltage for entering

ABM for low power

V

Blanking time for entering ABM

–

36

–

ms

V

Feedback voltage for leaving ABM V_{FB_LB}

2.63

2.26

2.73

2.35

2.83

2.45

Feedback voltage for burst-on

V_{FB_Bon_ISO}

V

– isolated case

Feedback voltage for burst-off

V_{FB_BOff_ISO}

1.88

2.00

2.05

V

– isolated case

¹Not subject to production test, specified by design.

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Electrical characteristics

Feedback voltage for burst-on

– non-isolated case

V_{FB_Bon_NISO}

V_{FB_BOff_NISO}

1.88

1.50

1.95

1.55

2.05

1.64

V

Feedback voltage for burst-off

– non-isolated case

4.10

Line overvoltage protection (CZ version)

Table 15

Line OVP

Parameter

Symbol

Limit values

Unit Note or

test condition

Test Condition

Min.

2.75

–

Typ.

2.85

250

Max.

2.95

–

Line overvoltage threshold

Line overvoltage blanking

V_{VIN_LOVP}

V

t_{VIN_LOVP_B}

µs

4.11

V_CCovervoltage protection

Table 16

V_CCovervoltage protection

Parameter

Symbol

Limit values

Unit Note or

test condition

Test Condition

Min.

24.0

–

Typ.

25.5

55

Max.

27.0

–

VCC overvoltage threshold

VCC overvoltage blanking

V_{VCC_OVP}

V

t_{VCC_OVP_B}

µs

4.12

Overload protection

Table 17

Overload protection

Parameter

Symbol Limit values

Unit Note or

test condition

Min.

Typ.

Max.

Overload detection threshold for

OLP protection at FB pin

V_{FB_OLP}

2.63

2.73

2.83

V

Overload protection blanking time

t_{FB_OLP_B}

30

54

–

ms

4.13

Thermal protection

Table 18

Thermal protection

Parameter

Symbol

Limit values

Unit Note or

test condition

Min.

129

–

Typ.

140

40

Max.

150

–

1

Overtemperature protection

Overtemperature hysteresis

Overtemperature blanking time

T_{jcon_OTP}

°C

µs

Junction temperature of

the controller chip (not

the CoolMOS™ chip).

T_{jHYS_OTP}

T_{jcon_OTP_B}

–

50

–

¹Not subject to production test, specified by design.

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4.14

CoolMOS™ section

Table 19

ICE5xRxxxxxZ

Parameter

Symbol Limit values

Unit Note or

test condition

Min.

Typ. Max.

V_(BR)DSS

Drain source breakdown voltage

ICE5xRxx80xZ

ICE5xR3995xZ

V

T_j= 25°C

800

950

–

R_DSon

Drain source on-resistance

Ω

(inclusive of low side MOSFET)

ICE5BR4780BZ

ICE5xR2280xZ

ICE5xR3995xZ

–

4.13 4.85

8.69¹

2.13 2.35

4.31¹

T_j= 25°C

T_j= 125°C at I_D= 0.4 A

T_j= 25°C

T_j= 125°C at I_D= 1 A

T_j= 25°C

T_j= 125°C at I_D= 0.8 A

–

3.46 4.05

7.69¹

–

C_o(er)

Effective output capacitance,

energy related¹

pF

ICE5BR4780BZ

ICE5xR2280xZ

ICE5xR3995xZ

Rise time

–

3

7

5

–

V_GS= 0 V, V_DS= 0 ~ 500 V

V_GS= 0 V, V_DS= 0 ~ 400 V

2

t_rise

30

ns

2

Fall time

t_fall

¹Not subject to production test, specified by design.

²Measured in a typical flyback / buck converter application.

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Rev 1.1

2022-07-19

Fixed-frequency 800 V / 950 V CoolSET™

in DIP-7 package

CoolMOS™ performance characteristics

5

CoolMOS™ performance characteristics

Figure 18 Safe operating area (SOA) curve for ICE5BR4780BZ

Figure 19 Safe operating area (SOA) curve for ICE5xR2280xZ

Datasheet

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CoolMOS™ performance characteristics

Figure 20 Safe operating area (SOA) curve for ICE5xR3995xZ

Figure 21

Power dissipation of ICE5BR4780BZ; P_tot= f(T_a) (Maximum ratings as given in chapter 4.1

must not be exceeded)

Datasheet

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Rev 1.1

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Fixed-frequency 800 V / 950 V CoolSET™

in DIP-7 package

CoolMOS™ performance characteristics

Figure 22

Power dissipation of ICE5xR3995xZ;P_tot= f(T_a) (Maximum ratings as given in chapter 4.1

must not be exceeded)

Figure 23

Power dissipation of ICE5xR2280xZ;P_tot= f(T_a) (Maximum ratings as given in chapter 4.1

must not be exceeded)

Datasheet

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CoolMOS™ performance characteristics

Figure 24

Drain-source breakdown voltage ICE5xRxx80xZ; V_BR(DSS)= f(T_J), I_D= 1 mA

Figure 25

Drain-source breakdown voltage ICE5xR3995xZ; V_BR(DSS)= f(T_J), I_D= 1 mA

Datasheet

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Rev 1.1

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CoolMOS™ performance characteristics

Figure 26

Typical CoolMOS™ capacitances of ICE5BR4780BZ (C = f(V_DS); V_GS= 0 V; f = 250 kHz)

Figure 27

Typical CoolMOS™ capacitances of ICE5xR2280xZ (C = f(V_DS); V_GS= 0 V; f = 250 kHz)

Datasheet

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Fixed-frequency 800 V / 950 V CoolSET™

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CoolMOS™ performance characteristics

Figure 28

Typical CoolMOS™ capacitances of ICE5xR3995xZ (C = f(V_DS); V_GS= 0 V; f = 250 kHz)

Datasheet

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Output power curve

6

Output power curve

The calculated output power curves versus ambient temperature are shown below. The curves are derived

based on a typical DCM/CCM flyback in an open frame design setting the maximum T_jof the integrated

CoolMOS™ at 125°C, using minimum drain pin copper area in a 2 oz copper single-sided PCB and steady state

operation only (no design margins for abnormal operation modes are included).

The output power figure is for selection purpose only. The actual power can vary depending on a particular

design. In a power supply system, appropriate thermal design margins must be considered to make sure that

the operation of the device is within the maximum ratings given in chapter 4.1.

Figure 29 Output power curve of ICE5BR4780BZ

Datasheet

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Fixed-frequency 800 V / 950 V CoolSET™

in DIP-7 package

Output power curve

Figure 30 Output power curve of ICE5BR3995xZ

Figure 31 Output power curve of ICE5AR3995BZ

Datasheet

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in DIP-7 package

Output power curve

Figure 32 Output power curve of ICE5AR2280CZ

Figure 33 Output power curve of ICE5BR2280BZ

Datasheet

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in DIP-7 package

Output current curve

7

Output current curve

The calculated output current curves showing typical output power against ambient temperature are shown

below. The curves are derived based on an open-frame design at T_a= 50°C, T_J= 125°C (integrated HV MOSFET

for CoolSET™), using the minimum 100 mm²drain pin copper area in a 2 oz copper single-sided PCB and steady-

state operation only (no design margins for abnormal operation modes are included). The output power figure

is for selection purposes only. The actual power can vary depending on the specific design.

Figure 34

Output current curve of ICE5BRxxxxBZ

Datasheet

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Package information

8

Package information

Figure 35

PG-DIP-7

Green product (RoHS-compliant)

To meet the world-wide customer requirements for environmentally friendly products and to be compliant

with government regulations, the device is available as a green product. Green products are RoHS-compliant

(i.e., Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).

Further information on packages

https://www.infineon.com/packages

Datasheet

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Fixed-frequency 800 V / 950 V CoolSET™

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Package information

8.1

Marking

Figure 36 Marking of PG-DIP-7

Datasheet

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Revision history

9

Revision history

Revision

Rev 1.0

Rev 1.1

Date

Changes

22 February 2022

19 July 2022

Initial release

Add new part number - ICE5AR3995BZ

Datasheet

39 of 40

Rev 1.1

2022-07-19

Trademarks

All referenced product or service names and trademarks are the property of their respective owners.

IMPORTANT NOTICE

The information given in this document shall in no

event be regarded as a guarantee of conditions or

characteristics ("Beschaffenheitsgarantie").

For further information on the product, delivery

terms and conditions and prices please contact

your nearest Infineon Technologies office

(www.infineon.com).

Edition 2022-07-19

Published by

Infineon Technologies AG

81726 Munich, Germany

With respect to any examples, hints or any typical

values stated herein and/or any information

regarding the application of the product, Infineon

Technologies hereby disclaims any and all

warranties and liabilities of any kind, including

without limitation warranties of non-infringement

of intellectual property rights of any third party.

In addition, any information given in this document

is subject to customer's compliance with its

obligations stated in this document and any

applicable legal requirements, norms and

standards concerning customer's products and any

use of the product of Infineon Technologies in

customer's applications.

The data contained in this document is exclusively

intended for technically trained staff. It is the

responsibility of customer's technical departments

to evaluate the suitability of the product for the

intended application and the completeness of the

product information given in this document with

respect to such application.

WARNINGS

Due to technical requirements products may

contain dangerous substances. For information on

the types in question please contact your nearest

Infineon Technologies office.

Except as otherwise explicitly approved by Infineon

Technologies in a written document signed by

Do you have a question about this

document?

authorized

representatives

of

Infineon

Technologies, Infineon Technologies’ products may

not be used in any applications where a failure of

the product or any consequences of the use thereof

can reasonably be expected to result in personal

injury.

Email: erratum@infineon.com

Document reference

ICE5xRxxxxxZ


型号：	ICE5AR3995BZ
厂家：	Infineon
描述：	100 kHz offline flyback regulator with integrated 950 V CoolMOS™ superjunction MOSFET
文件：	总40页 (文件大小：2350K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICE5AR3995BZ [INFINEON]

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