IPAN65R650CE [INFINEON]
;型号: | IPAN65R650CE |
厂家: | Infineon |
描述: | |
文件: | 总14页 (文件大小:733K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IPAN65R650CE
MOSFET
PG-TOꢀ220ꢀFP
650VꢀCoolMOS™ꢀCEꢀPowerꢀTransistor
CoolMOS™ꢀisꢀaꢀrevolutionaryꢀtechnologyꢀforꢀhighꢀvoltageꢀpower
MOSFETs,ꢀdesignedꢀaccordingꢀtoꢀtheꢀsuperjunctionꢀ(SJ)ꢀprincipleꢀand
pioneeredꢀbyꢀInfineonꢀTechnologies.ꢀCoolMOS™ꢀCEꢀisꢀa
price-performanceꢀoptimizedꢀplatformꢀenablingꢀtoꢀtargetꢀcostꢀsensitive
applicationsꢀinꢀConsumerꢀandꢀLightingꢀmarketsꢀbyꢀstillꢀmeetingꢀhighest
efficiencyꢀstandards.ꢀTheꢀnewꢀseriesꢀprovidesꢀallꢀbenefitsꢀofꢀaꢀfast
switchingꢀSuperjunctionꢀMOSFETꢀwhileꢀnotꢀsacrificingꢀeaseꢀofꢀuseꢀand
offeringꢀtheꢀbestꢀcostꢀdownꢀperformanceꢀratioꢀavailableꢀonꢀtheꢀmarket.
Features
•ꢀExtremelyꢀlowꢀlossesꢀdueꢀtoꢀveryꢀlowꢀFOMꢀRdson*QgꢀandꢀEoss
•ꢀVeryꢀhighꢀcommutationꢀruggedness
•ꢀEasyꢀtoꢀuse/drive
Drain
Pin 2, Tab
•ꢀPb-freeꢀplating,ꢀHalogenꢀfreeꢀmoldꢀcompound
•ꢀQualifiedꢀforꢀstandardꢀgradeꢀapplications
Gate
Pin 1
Applications
Source
Pin 3
PFCꢀstages,ꢀhardꢀswitchingꢀPWMꢀstagesꢀandꢀresonantꢀswitchingꢀstages
forꢀe.g.ꢀPCꢀSilverbox,ꢀAdapter,ꢀLCDꢀ&ꢀPDPꢀTVꢀandꢀindoorꢀlighting.
Pleaseꢀnote:ꢀForꢀMOSFETꢀparallelingꢀtheꢀuseꢀofꢀferriteꢀbeadsꢀonꢀtheꢀgate
orꢀseparateꢀtotemꢀpolesꢀisꢀgenerallyꢀrecommended.
Tableꢀ1ꢀꢀꢀꢀꢀKeyꢀPerformanceꢀParameters
Parameter
VDS @ Tj,max
RDS(on),max
ID.
Value
700
650
10.1
23
Unit
V
mΩ
A
Qg.typ
nC
A
ID,pulse
18
Eoss@400V
2
µJ
Typeꢀ/ꢀOrderingꢀCode
Package
Marking
RelatedꢀLinks
PG-TO 220 FullPAK -
Narrow Lead
IPAN65R650CE
65S650CE
see Appendix A
F
Final Data Sheet
1
Rev.2.2, 2018-04-25
650VꢀCoolMOS™ꢀCEꢀPowerꢀTransistor
IPAN65R650CE
TableꢀofꢀContents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Final Data Sheet
2
Rev.2.2, 2018-04-25
650VꢀCoolMOS™ꢀCEꢀPowerꢀTransistor
IPAN65R650CE
1ꢀꢀꢀꢀꢀMaximumꢀratings
atꢀTjꢀ=ꢀ25°C,ꢀunlessꢀotherwiseꢀspecified
Tableꢀ2ꢀꢀꢀꢀꢀMaximumꢀratings
Values
Typ.
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
-
-
-
-
10.1
6.4
TC=25°C
A
Continuous drain current1)
ID
TC=100°C
Pulsed drain current2)
ID,pulse
EAS
-
-
-
-
-
-
-
-
18
A
TC=25°C
Avalanche energy, single pulse
Avalanche energy, repetitive
Avalanche current, repetitive
MOSFET dv/dt ruggedness
Gate source voltage (static)
Gate source voltage (dynamic)
-
142
0.21
1.3
50
mJ
mJ
A
ID=1.3A; VDD=50V; see table 11
EAR
-
ID=1.3A; VDD=50V; see table 11
-
IAR
-
dv/dt
VGS
VGS
-
V/ns VDS=0...480V
-20
-30
20
V
V
static;
30
AC (f>1 Hz)
Power dissipation (Non FullPAK)
TO-252
Ptot
-
-
86
W
TC=25°C
Storage temperature
Tstg
Tj
-40
-40
-
-
-
-
-
150
150
7.1
18
°C
°C
A
-
Operating junction temperature
Continuous diode forward current
Diode pulse current2)
-
IS
TC=25°C
TC=25°C
IS,pulse
-
A
VDS=0...400V,ꢀISD<=IS,ꢀTj=25°Cꢀꢀꢀꢀꢀꢀꢀꢀ
see table 9
Reverse diode dv/dt3)
dv/dt
dif/dt
Ptot
-
-
-
-
-
-
-
-
-
-
15
V/ns
A/µs
W
VDS=0...400V,ꢀISD<=IS,ꢀTj=25°Cꢀꢀꢀꢀꢀꢀꢀꢀ
see table 9
Maximum diode commutation speed
500
28
Power dissipation (FullPAK)
TO-220FP
TC=25°C
Mounting torque (FullPAK)
TO-220FP
-
50
Ncm M2.5 screws
Vrms,ꢀTC=25°C,ꢀt=1min
Insulation withstand voltage for
TO-220FP
VISO
2500
V
1) Limited by Tj max.TO252 equivalent, Maximum duty cycle D=0.50
2) Pulse width tp limited by Tj,max
3)ꢀIdenticalꢀlowꢀsideꢀandꢀhighꢀsideꢀswitchꢀwithꢀidenticalꢀRG
Final Data Sheet
3
Rev.2.2, 2018-04-25
650VꢀCoolMOS™ꢀCEꢀPowerꢀTransistor
IPAN65R650CE
2ꢀꢀꢀꢀꢀThermalꢀcharacteristics
Tableꢀ3ꢀꢀꢀꢀꢀThermalꢀcharacteristicsꢀ(FullPAK)ꢀTO-220FP
Values
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Typ.
Max.
4.5
Thermal resistance, junction - case
RthJC
-
-
-
-
°C/W -
Thermal resistance, junction - ambient RthJA
80
°C/W leaded
Soldering temperature, wavesoldering
only allowed at leads
Tsold
-
-
260
°C
1.6mm (0.063 in.) from case for 10s
Final Data Sheet
4
Rev.2.2, 2018-04-25
650VꢀCoolMOS™ꢀCEꢀPowerꢀTransistor
IPAN65R650CE
3ꢀꢀꢀꢀꢀElectricalꢀcharacteristics
atꢀTj=25°C,ꢀunlessꢀotherwiseꢀspecified
Tableꢀ4ꢀꢀꢀꢀꢀStaticꢀcharacteristics
Values
Typ.
-
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
650
2.5
Max.
-
Drain-source breakdown voltage
Gate threshold voltage
V(BR)DSS
V(GS)th
V
V
VGS=0V,ꢀID=1mA
3.0
3.5
VDS=VGS,ꢀID=0.21mA
-
-
-
10
1
-
VDS=650,ꢀVGS=0V,ꢀTj=25°C
VDS=650,ꢀVGS=0V,ꢀTj=150°C
Zero gate voltage drain current
Gate-source leakage current
Drain-source on-state resistance
Gate resistance
IDSS
µA
nA
Ω
IGSS
-
-
100
VGS=20V,ꢀVDS=0V
-
-
0.54
1.40
0.65
-
VGS=10V,ꢀID=2.1A,ꢀTj=25°C
VGS=10V,ꢀID=2.1A,ꢀTj=150°C
RDS(on)
RG
-
10.5
-
Ω
f=1MHz,ꢀopenꢀdrain
Tableꢀ5ꢀꢀꢀꢀꢀDynamicꢀcharacteristics
Values
Typ.
440
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Input capacitance
Output capacitance
Ciss
-
-
-
-
pF
pF
VGS=0V,ꢀVDS=100V,ꢀf=1MHz
VGS=0V,ꢀVDS=100V,ꢀf=1MHz
Coss
30
Effective output capacitance,
energy related1)
Co(er)
Co(tr)
td(on)
tr
-
-
-
-
-
-
21
88
10
8
-
-
-
-
-
-
pF
pF
ns
ns
ns
ns
VGS=0V,ꢀVDS=0...480V
Effective output capacitance,
time related2)
ID=constant,ꢀVGS=0V,ꢀVDS=0...480V
VDD=400V,ꢀVGS=13V,ꢀID=3.2A,
RG=6.8Ω;ꢀseeꢀtableꢀ10
Turn-on delay time
Rise time
VDD=400V,ꢀVGS=13V,ꢀID=3.2A,
RG=6.8Ω;ꢀseeꢀtableꢀ10
VDD=400V,ꢀVGS=13V,ꢀID=3.2A,
RG=6.8Ω;ꢀseeꢀtableꢀ10
Turn-off delay time
Fall time
td(off)
tf
64
11
VDD=400V,ꢀVGS=13ꢀV,ꢀID=3.2A,
RG=6.8Ω;ꢀseeꢀtableꢀ10
Tableꢀ6ꢀꢀꢀꢀꢀGateꢀchargeꢀcharacteristics
Values
Typ.
2.75
12
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Gate to source charge
Gate to drain charge
Gate charge total
Qgs
-
-
-
-
-
-
-
-
nC
nC
nC
V
VDD=480V,ꢀID=3.2A,ꢀVGS=0ꢀtoꢀ10V
VDD=480V,ꢀID=3.2A,ꢀVGS=0ꢀtoꢀ10V
VDD=480V,ꢀID=3.2A,ꢀVGS=0ꢀtoꢀ10V
VDD=480V,ꢀID=3.2A,ꢀVGS=0ꢀtoꢀ10V
Qgd
Qg
23
Gate plateau voltage
Vplateau
5.5
1)ꢀCo(er)ꢀisꢀaꢀfixedꢀcapacitanceꢀthatꢀgivesꢀtheꢀsameꢀstoredꢀenergyꢀasꢀCossꢀwhileꢀVDSꢀisꢀrisingꢀfromꢀ0ꢀtoꢀ80%ꢀVo(BR)DSS
2)ꢀCo(tr)ꢀisꢀaꢀfixedꢀcapacitanceꢀthatꢀgivesꢀtheꢀsameꢀstoredꢀenergyꢀasꢀCossꢀwhileꢀVDSꢀisꢀrisingꢀfromꢀ0ꢀtoꢀ80%ꢀVo(BR)DSS
Final Data Sheet
5
Rev.2.2, 2018-04-25
650VꢀCoolMOS™ꢀCEꢀPowerꢀTransistor
IPAN65R650CE
Tableꢀ7ꢀꢀꢀꢀꢀReverseꢀdiodeꢀcharacteristics
Values
Typ.
0.9
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Diode forward voltage
Reverse recovery time
VSD
trr
-
-
V
VGS=0V,ꢀIF=3.2A,ꢀTj=25°C
VR=400V,ꢀIF=3.2A,ꢀdiF/dt=100A/µs;
see table 9
-
-
-
270
2
-
-
-
ns
VR=400V,ꢀIF=3.2A,ꢀdiF/dt=100A/µs;
see table 9
Reverse recovery charge
Qrr
Irrm
µC
A
VR=400V,ꢀIF=3.2A,ꢀdiF/dt=100A/µs;
see table 9
Peak reverse recovery current
13
Final Data Sheet
6
Rev.2.2, 2018-04-25
650VꢀCoolMOS™ꢀCEꢀPowerꢀTransistor
IPAN65R650CE
4ꢀꢀꢀꢀꢀElectricalꢀcharacteristicsꢀdiagrams
Diagramꢀ2:ꢀPowerꢀdissipationꢀ(FullPAK)
Diagramꢀ4:ꢀMax.ꢀtransientꢀthermalꢀimpedanceꢀ(FullPAK)
30
101
25
20
15
10
5
0.5
0.2
100
0.1
0.05
0.02
10-1
0.01
single pulse
0
10-2
0
25
50
75
100
125
150
10-5
10-4
10-3
10-2
10-1
100
101
TCꢀ[°C]
tpꢀ[s]
Ptot=f(TC)
ZthJCꢀ=f(tP);ꢀparameter:ꢀD=tp/T
Diagramꢀ6:ꢀSafeꢀoperatingꢀareaꢀ(FullPAK)
Diagramꢀ8:ꢀSafeꢀoperatingꢀareaꢀ(FullPAK)
102
102
1 µs
1 µs
101
100
10 µs
101
10 µs
100 µs
1 ms
100 µs
1 ms
10 ms
100
10-1
10-2
10-3
10-4
10 ms
DC
DC
10-1
10-2
10-3
10-4
100
101
102
103
100
101
102
103
VDSꢀ[V]
VDSꢀ[V]
ID=f(VDS);ꢀTC=25ꢀ°C;ꢀD=0;ꢀparameter:ꢀtp
ID=f(VDS);ꢀTC=80ꢀ°C;ꢀD=0;ꢀparameter:ꢀtp
F
Final Data Sheet
7
Rev.2.2, 2018-04-25
650VꢀCoolMOS™ꢀCEꢀPowerꢀTransistor
IPAN65R650CE
Diagramꢀ9:ꢀTyp.ꢀoutputꢀcharacteristics
Diagramꢀ10:ꢀTyp.ꢀoutputꢀcharacteristics
20
12
20 V
20 V
10 V
10 V
7 V
8 V
16
9
6
3
0
8 V
12
6 V
7 V
8
5.5 V
6 V
5 V
5.5 V
4
4.5 V
5 V
4.5 V
0
0
5
10
15
20
0
5
10
15
20
VDSꢀ[V]
VDSꢀ[V]
ID=f(VDS);ꢀTj=25ꢀ°C;ꢀparameter:ꢀVGS
ID=f(VDS);ꢀTj=125ꢀ°C;ꢀparameter:ꢀVGS
Diagramꢀ11:ꢀTyp.ꢀdrain-sourceꢀon-stateꢀresistance
Diagramꢀ12:ꢀDrain-sourceꢀon-stateꢀresistance
2.0
1.60
1.50
1.40
1.30
1.20
1.10
1.00
1.9
1.8
1.7
1.6
7 V
5 V
5.5 V
6 V
6.5 V
1.5
1.4
1.3
1.2
1.1
1.0
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
98%
10 V
typ
0
2
4
6
8
10
12
-50
-25
0
25
50
75
100
125
150
IDꢀ[A]
Tjꢀ[°C]
RDS(on)=f(ID);ꢀTj=125ꢀ°C;ꢀparameter:ꢀVGS
RDS(on)=f(Tj);ꢀID=2.1ꢀA;ꢀVGS=10ꢀV
Final Data Sheet
8
Rev.2.2, 2018-04-25
650VꢀCoolMOS™ꢀCEꢀPowerꢀTransistor
IPAN65R650CE
Diagramꢀ13:ꢀTyp.ꢀtransferꢀcharacteristics
Diagramꢀ14:ꢀTyp.ꢀgateꢀcharge
20
10
25 °C
18
9
8
7
6
5
4
3
2
1
0
16
14
12
120 V
480 V
10
150 °C
8
6
4
2
0
0
2
4
6
8
10
12
0
5
10
15
20
25
VGSꢀ[V]
Qgateꢀ[nC]
ID=f(VGS);ꢀVDS=20V;ꢀparameter:ꢀTj
VGS=f(Qgate);ꢀID=3.2ꢀAꢀpulsed;ꢀparameter:ꢀVDD
Diagramꢀ15:ꢀForwardꢀcharacteristicsꢀofꢀreverseꢀdiode
Diagramꢀ16:ꢀAvalancheꢀenergy
102
150
25 °C
125 °C
125
100
75
50
25
0
101
100
10-1
0.0
0.5
1.0
1.5
2.0
25
50
75
100
125
150
VSDꢀ[V]
Tjꢀ[°C]
IF=f(VSD);ꢀparameter:ꢀTj
EAS=f(Tj);ꢀID=1.3ꢀA;ꢀVDD=50ꢀV
F
Final Data Sheet
9
Rev.2.2, 2018-04-25
650VꢀCoolMOS™ꢀCEꢀPowerꢀTransistor
IPAN65R650CE
Diagramꢀ17:ꢀDrain-sourceꢀbreakdownꢀvoltage
Diagramꢀ18:ꢀTyp.ꢀcapacitances
740
104
720
700
680
660
640
620
600
580
103
Ciss
102
Coss
101
Crss
100
-75 -50 -25
0
25
50
75 100 125 150 175
0
100
200
300
400
500
Tjꢀ[°C]
VDSꢀ[V]
VBR(DSS)=f(Tj);ꢀID=1.0ꢀmA
C=f(VDS);ꢀVGS=0ꢀV;ꢀf=1ꢀMHz
Diagramꢀ19:ꢀTyp.ꢀCossꢀstoredꢀenergy
2.5
2.0
1.5
1.0
0.5
0.0
0
100
200
300
400
500
VDSꢀ[V]
Eoss=f(VDS
)
Final Data Sheet
10
Rev.2.2, 2018-04-25
650VꢀCoolMOS™ꢀCEꢀPowerꢀTransistor
IPAN65R650CE
5ꢀꢀꢀꢀꢀTestꢀCircuits
Tableꢀ8ꢀꢀꢀꢀꢀDiodeꢀcharacteristics
Test circuit for diode characteristics
Diode recovery waveform
V,I
VDS
Rg1
VDS(peak)
VDS
trr
VDS
IF
tF
tS
dIF / dt
Rg 2
IF
t
10%Irrm
Q
F
Q
S
IF
dI / dt
rr
trr =tF +tS
rr
Irrm
Q =QF +Q
S
Rg1 = Rg 2
Tableꢀ9ꢀꢀꢀꢀꢀSwitchingꢀtimes
Switching times test circuit for inductive load
Switching times waveform
VDS
90%
10%
VDS
VGS
VGS
td(off)
tf
td(on)
ton
tr
toff
Tableꢀ10ꢀꢀꢀꢀꢀUnclampedꢀinductiveꢀload
Unclamped inductive load test circuit
Unclamped inductive waveform
V(BR)DS
ID
VDS
VDS
VDS
ID
Final Data Sheet
11
Rev.2.2, 2018-04-25
650VꢀCoolMOS™ꢀCEꢀPowerꢀTransistor
IPAN65R650CE
6ꢀꢀꢀꢀꢀPackageꢀOutlines
DOCUMENT NO.
Z8B00188573
REVISION
01
SCALE 5:1
5mm
0
1
2
3
4
EUROPEAN PROJECTION
ISSUE DATE
22.03.2018
MILLIMETERS
MAX.
4.80
DIMENSIONS
MIN.
4.60
2.60
2.47
0.56
1.01
0.46
15.90
9.58
10.40
A
A1
A2
b
2.80
2.67
0.69
b1
c
1.15
0.59
D
16.10
9.78
D1
E
10.60
2.54
e
N
3
L
13.45
1.70
3.00
3.25
13.75
1.91
L1
øP
Q
3.20
3.45
Figure 1 Outline PG-TO 220 FullPAK - Narrow Lead, dimensions in mm
Final Data Sheet
12
Rev.2.2, 2018-04-25
650V CoolMOS™ CE Power Transistor
IPAN65R650CE
7
Appendix A
Table 11 Related Links
• IFX CoolMOSTM CE Webpage: www.infineon.com
• IFX CoolMOSTM CE application note: www.infineon.com
• IFX CoolMOSTM CE simulation model: www.infineon.com
• IFX Design tools: www.infineon.com
F
Final Data Sheet
13
Rev.2.2, 2018-04-25
650VꢀCoolMOSªꢀCEꢀPowerꢀTransistor
IPAN65R650CE
RevisionꢀHistory
IPAN65R650CE
Revision:ꢀ2018-04-30,ꢀRev.ꢀ2.2
Previous Revision
Revision Date
Subjects (major changes since last revision)
2.0
2.1
2.2
Release of final version
2016-04-27
2016-11-28
2018-04-30
Revised package drawing on page 11
Revised package drawing
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14
Rev.ꢀ2.2,ꢀꢀ2018-04-30
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