IPB019N08N5 [INFINEON]

与前几代产品相比,英飞凌OptiMOS™5 80V工业功率MOSFETIPB019N08N5,其R DS(on)降低了43%,非常适合高开关频率。该器件专为通信和服务器电源中的同步整流而设计。此外,它们还可以在其他工业应用中使用,例如太阳能、低压驱动器和适配器。;
IPB019N08N5
型号: IPB019N08N5
厂家: Infineon    Infineon
描述:

与前几代产品相比,英飞凌OptiMOS™5 80V工业功率MOSFETIPB019N08N5,其R DS(on)降低了43%,非常适合高开关频率。该器件专为通信和服务器电源中的同步整流而设计。此外,它们还可以在其他工业应用中使用,例如太阳能、低压驱动器和适配器。

通信 开关 驱动 服务器 驱动器
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IPB019N08N5  
MOSFET  
OptiMOSªꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
D²-PAKꢀ7pin  
Features  
•ꢀIdealꢀforꢀhighꢀfrequencyꢀswitchingꢀandꢀsync.ꢀrec.  
•ꢀOptimizedꢀtechnologyꢀforꢀDC/DCꢀconverters  
•ꢀExcellentꢀgateꢀchargeꢀxꢀRDS(on)ꢀproductꢀ(FOM)  
•ꢀVeryꢀlowꢀon-resistanceꢀꢀRDS(on)  
tab  
1
•ꢀN-channel,ꢀnormalꢀlevel  
•ꢀ100%ꢀavalancheꢀtested  
7
•ꢀPb-freeꢀplating;ꢀRoHSꢀcompliant  
•ꢀIndustrialꢀqualifiedꢀaccordingꢀtoꢀJEDEC1)ꢀꢀforꢀtargetꢀapplications  
•ꢀHalogen-freeꢀaccordingꢀtoꢀIEC61249-2-21  
Drain  
Pin 4, tab  
Tableꢀ1ꢀꢀꢀꢀꢀKeyꢀPerformanceꢀParameters  
Parameter  
Value  
Unit  
Gate  
Pin 1  
VDS  
80  
V
Source  
Pin 2,3,5,6,7  
RDS(on),max  
ID  
1.95  
180  
116  
99  
m  
A
Qoss  
nC  
nC  
QG(0V..10V)  
Typeꢀ/ꢀOrderingꢀCode  
Package  
Marking  
RelatedꢀLinks  
IPB019N08N5  
PG-TO 263-7  
019N08N5  
-
1) J-STD20 and JESD22  
Final Data Sheet  
1
Rev.ꢀ2.0,ꢀꢀ2017-07-20  
OptiMOSªꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB019N08N5  
TableꢀofꢀContents  
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Final Data Sheet  
2
Rev.ꢀ2.0,ꢀꢀ2017-07-20  
OptiMOSªꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB019N08N5  
1ꢀꢀꢀꢀꢀMaximumꢀratings  
atꢀTA=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified  
Tableꢀ2ꢀꢀꢀꢀꢀMaximumꢀratings  
Values  
Typ.  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
-
-
-
-
180  
170  
TC=25ꢀ°C  
A
Continuous drain current  
ID  
TC=100ꢀ°C  
Pulsed drain current1)  
Avalanche energy, single pulse2)  
Gate source voltage  
ID,pulse  
EAS  
-
-
-
-
-
720  
374  
20  
A
TC=25ꢀ°C  
-
mJ  
V
ID=100ꢀA,ꢀRGS=25ꢀΩ  
VGS  
Ptot  
-20  
-
-
Power dissipation  
224  
W
TC=25ꢀ°C  
IEC climatic category;  
DIN IEC 68-1: 55/175/56  
Operating and storage temperature  
Tj,ꢀTstg  
-55  
-
175  
°C  
2ꢀꢀꢀꢀꢀThermalꢀcharacteristics  
Tableꢀ3ꢀꢀꢀꢀꢀThermalꢀcharacteristics  
Values  
Typ.  
0.4  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
Thermal resistance, junction - case  
RthJC  
RthJA  
-
0.67  
K/W  
K/W  
-
-
Thermal resistance, junction - ambient,  
minimal footprint  
-
-
-
-
-
-
62  
Thermal resistance, junction - ambient,  
6 cm2 cooling area3)  
RthJA  
Tsold  
40  
K/W  
°C  
-
Soldering temperature and  
reflow soldering is allowed  
260  
Reflow MSL1  
1) See Diagram 3 for more detailed information  
2) See Diagram 13 for more detailed information  
3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection.  
PCB is vertical in still air.  
Final Data Sheet  
3
Rev.ꢀ2.0,ꢀꢀ2017-07-20  
OptiMOSªꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB019N08N5  
3ꢀꢀꢀꢀꢀElectricalꢀcharacteristics  
Tableꢀ4ꢀꢀꢀꢀꢀStaticꢀcharacteristics  
Values  
Typ.  
-
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
80  
Max.  
-
Drain-source breakdown voltage  
Gate threshold voltage  
V(BR)DSS  
VGS(th)  
V
V
VGS=0ꢀV,ꢀID=1ꢀmA  
2.2  
3.0  
3.8  
VDS=VGS,ꢀID=154ꢀµA  
-
-
0.1  
10  
1
100  
VDS=80ꢀV,ꢀVGS=0ꢀV,ꢀTj=25ꢀ°C  
VDS=80ꢀV,ꢀVGS=0ꢀV,ꢀTj=125ꢀ°C  
Zero gate voltage drain current  
Gate-source leakage current  
Drain-source on-state resistance  
IDSS  
µA  
nA  
IGSS  
-
1
100  
VGS=20ꢀV,ꢀVDS=0ꢀV  
-
-
1.7  
2.3  
1.95  
3.1  
VGS=10ꢀV,ꢀID=100ꢀA  
VGS=6ꢀV,ꢀID=50ꢀA  
RDS(on)  
mΩ  
Gate resistance1)  
Transconductance  
RG  
gfs  
-
1.4  
2.1  
-
-
94  
187  
S
|VDS|>2|ID|RDS(on)max,ꢀID=100ꢀA  
Tableꢀ5ꢀꢀꢀꢀꢀDynamicꢀcharacteristics1)ꢀ  
Values  
Typ.  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
Input capacitance  
Ciss  
Coss  
Crss  
-
-
-
6900 8970 pF  
1100 1430 pF  
VGS=0ꢀV,ꢀVDS=40ꢀV,ꢀf=1ꢀMHz  
VGS=0ꢀV,ꢀVDS=40ꢀV,ꢀf=1ꢀMHz  
VGS=0ꢀV,ꢀVDS=40ꢀV,ꢀf=1ꢀMHz  
Output capacitance  
Reverse transfer capacitance  
49  
18  
86  
-
pF  
ns  
VDD=40ꢀV,ꢀVGS=10ꢀV,ꢀID=100ꢀA,  
RG,ext=1.6ꢀΩ  
Turn-on delay time  
Rise time  
td(on)  
tr  
td(off)  
tf  
-
-
-
-
VDD=40ꢀV,ꢀVGS=10ꢀV,ꢀID=100ꢀA,  
RG,ext=1.6ꢀΩ  
11  
41  
15  
-
-
-
ns  
ns  
ns  
VDD=40ꢀV,ꢀVGS=10ꢀV,ꢀID=100ꢀA,  
RG,ext=1.6ꢀΩ  
Turn-off delay time  
Fall time  
VDD=40ꢀV,ꢀVGS=10ꢀV,ꢀID=100ꢀA,  
RG,ext=1.6ꢀΩ  
Tableꢀ6ꢀꢀꢀꢀꢀGateꢀchargeꢀcharacteristics2)ꢀ  
Values  
Typ.  
33  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Max.  
Gate to source charge  
Gate to drain charge1)  
Switching charge  
Qgs  
-
-
-
-
-
-
-
-
nC  
nC  
nC  
nC  
V
VDD=40ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV  
VDD=40ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV  
VDD=40ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV  
VDD=40ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV  
VDD=40ꢀV,ꢀID=100ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV  
VDS=0.1ꢀV,ꢀVGS=0ꢀtoꢀ10ꢀV  
Qgd  
21  
32  
Qsw  
33  
-
Gate charge total1)  
Qg  
99  
123  
Gate plateau voltage  
Gate charge total, sync. FET  
Output charge1)  
Vplateau  
Qg(sync)  
Qoss  
4.7  
-
85  
-
nC  
nC  
116  
155  
VDD=40ꢀV,ꢀVGS=0ꢀV  
1) Defined by design. Not subject to production test.  
2) See Gate charge waveformsfor parameter definition  
Final Data Sheet  
4
Rev.ꢀ2.0,ꢀꢀ2017-07-20  
OptiMOSªꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB019N08N5  
Tableꢀ7ꢀꢀꢀꢀꢀReverseꢀdiode  
Values  
Parameter  
Symbol  
Unit Noteꢀ/ꢀTestꢀCondition  
Min.  
Typ.  
-
Max.  
180  
720  
1.2  
Diode continous forward current  
Diode pulse current  
IS  
-
-
-
-
-
A
TC=25ꢀ°C  
IS,pulse  
VSD  
trr  
-
A
TC=25ꢀ°C  
Diode forward voltage  
0.9  
61  
92  
V
VGS=0ꢀV,ꢀIF=100ꢀA,ꢀTj=25ꢀ°C  
VR=40ꢀV,ꢀIF=100ꢀA,ꢀdiF/dt=100ꢀA/µs  
VR=40ꢀV,ꢀIF=100ꢀA,ꢀdiF/dt=100ꢀA/µs  
Reverse recovery time1)  
Reverse recovery charge1)  
122  
184  
ns  
nC  
Qrr  
1) Defined by design. Not subject to production test.  
Final Data Sheet  
5
Rev.ꢀ2.0,ꢀꢀ2017-07-20  
OptiMOSªꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB019N08N5  
4ꢀꢀꢀꢀꢀElectricalꢀcharacteristicsꢀdiagrams  
Diagramꢀ1:ꢀPowerꢀdissipation  
Diagramꢀ2:ꢀDrainꢀcurrent  
250  
200  
180  
160  
140  
120  
100  
80  
200  
150  
100  
50  
60  
40  
20  
0
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
TCꢀ[°C]  
TCꢀ[°C]  
Ptot=f(TC)  
ID=f(TC);ꢀVGS10ꢀV  
Diagramꢀ3:ꢀSafeꢀoperatingꢀarea  
Diagramꢀ4:ꢀMax.ꢀtransientꢀthermalꢀimpedance  
103  
100  
1 µs  
10 µs  
100 µs  
102  
101  
100  
10-1  
0.5  
0.2  
1 ms  
10-1  
0.1  
10 ms  
0.05  
DC  
0.02  
0.01  
single pulse  
10-2  
10-1  
100  
101  
102  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
VDSꢀ[V]  
tpꢀ[s]  
ID=f(VDS);ꢀTC=25ꢀ°C;ꢀD=0;ꢀparameter:ꢀtp  
ZthJC=f(tp);ꢀparameter:ꢀD=tp/T  
Final Data Sheet  
6
Rev.ꢀ2.0,ꢀꢀ2017-07-20  
OptiMOSªꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB019N08N5  
Diagramꢀ5:ꢀTyp.ꢀoutputꢀcharacteristics  
Diagramꢀ6:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance  
720  
5
10 V  
4.5 V  
6.5 V  
640  
4
5 V  
560  
5.5 V  
480  
400  
320  
240  
160  
80  
6 V  
6 V  
3
6.5 V  
5.5 V  
2
1
0
10 V  
5 V  
4.5 V  
0
0
1
2
3
4
5
0
50  
100 150 200 250 300 350 400 450  
VDSꢀ[V]  
IDꢀ[A]  
ID=f(VDS);ꢀTj=25ꢀ°C;ꢀparameter:ꢀVGS  
RDS(on)=f(ID);ꢀTj=25ꢀ°C;ꢀparameter:ꢀVGS  
Diagramꢀ7:ꢀTyp.ꢀtransferꢀcharacteristics  
Diagramꢀ8:ꢀTyp.ꢀforwardꢀtransconductance  
300  
250  
250  
200  
150  
100  
200  
150  
100  
50  
175 °C  
50  
25 °C  
0
0
0
2
4
6
8
0
40  
80  
120  
160  
VGSꢀ[V]  
IDꢀ[A]  
ID=f(VGS);ꢀ|VDS|>2|ID|RDS(on)max;ꢀparameter:ꢀTj  
gfs=f(ID);ꢀTj=25ꢀ°C  
Final Data Sheet  
7
Rev.ꢀ2.0,ꢀꢀ2017-07-20  
OptiMOSªꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB019N08N5  
Diagramꢀ9:ꢀDrain-sourceꢀon-stateꢀresistance  
Diagramꢀ10:ꢀTyp.ꢀgateꢀthresholdꢀvoltage  
4
4.0  
3.5  
1540 µA  
3
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
154 µA  
max  
typ  
2
1
0
-60  
-20  
20  
60  
100  
140  
180  
-60  
-20  
20  
60  
100  
140  
180  
Tjꢀ[°C]  
Tjꢀ[°C]  
RDS(on)=f(Tj);ꢀID=100ꢀA;ꢀVGS=10ꢀV  
VGS(th)=f(Tj);ꢀVGS=VDS;ꢀparameter:ꢀID  
Diagramꢀ11:ꢀTyp.ꢀcapacitances  
Diagramꢀ12:ꢀForwardꢀcharacteristicsꢀofꢀreverseꢀdiode  
104  
103  
25 °C  
175 °C  
25 °C, max  
175 °C, max  
Ciss  
Coss  
103  
102  
101  
102  
101  
100  
Crss  
0
20  
40  
60  
80  
0.0  
0.5  
1.0  
1.5  
2.0  
VDSꢀ[V]  
VSDꢀ[V]  
C=f(VDS);ꢀVGS=0ꢀV;ꢀf=1ꢀMHz  
IF=f(VSD);ꢀparameter:ꢀTj  
Final Data Sheet  
8
Rev.ꢀ2.0,ꢀꢀ2017-07-20  
OptiMOSªꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB019N08N5  
Diagramꢀ13:ꢀAvalancheꢀcharacteristics  
Diagramꢀ14:ꢀTyp.ꢀgateꢀcharge  
103  
10  
8
6
4
2
0
40 V  
64 V  
102  
16 V  
25 °C  
100 °C  
150 °C  
101  
100  
100  
101  
102  
103  
0
25  
50  
75  
100  
tAVꢀ[µs]  
Qgateꢀ[nC]  
IAS=f(tAV);ꢀRGS=25ꢀ;ꢀparameter:ꢀTj(start)  
VGS=f(Qgate);ꢀID=100ꢀAꢀpulsed;ꢀparameter:ꢀVDD  
Diagramꢀ15:ꢀDrain-sourceꢀbreakdownꢀvoltage  
Gate charge waveforms  
90  
85  
80  
75  
70  
-60  
-20  
20  
60  
100  
140  
180  
Tjꢀ[°C]  
VBR(DSS)=f(Tj);ꢀID=1ꢀmA  
Final Data Sheet  
9
Rev.ꢀ2.0,ꢀꢀ2017-07-20  
OptiMOSªꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB019N08N5  
5ꢀꢀꢀꢀꢀPackageꢀOutlines  
Figureꢀ1ꢀꢀꢀꢀꢀOutlineꢀPG-TOꢀ263-7,ꢀdimensionsꢀinꢀmm/inches  
Final Data Sheet  
10  
Rev.ꢀ2.0,ꢀꢀ2017-07-20  
OptiMOSªꢀꢀ5ꢀPower-Transistor,ꢀ80ꢀV  
IPB019N08N5  
RevisionꢀHistory  
IPB019N08N5  
Revision:ꢀ2017-07-20,ꢀRev.ꢀ2.0  
Previous Revision  
Revision Date  
2.0  
Subjects (major changes since last revision)  
Release of final version  
2017-07-20  
TrademarksꢀofꢀInfineonꢀTechnologiesꢀAG  
AURIX™,ꢀC166™,ꢀCanPAK™,ꢀCIPOS™,ꢀCoolGaN™,ꢀCoolMOS™,ꢀCoolSET™,ꢀCoolSiC™,ꢀCORECONTROL™,ꢀCROSSAVE™,ꢀDAVE™,ꢀDI-POL™,ꢀDrBlade™,  
EasyPIM™,ꢀEconoBRIDGE™,ꢀEconoDUAL™,ꢀEconoPACK™,ꢀEconoPIM™,ꢀEiceDRIVER™,ꢀeupec™,ꢀFCOS™,ꢀHITFET™,ꢀHybridPACK™,ꢀInfineon™,  
ISOFACE™,ꢀIsoPACK™,ꢀi-Wafer™,ꢀMIPAQ™,ꢀModSTACK™,ꢀmy-d™,ꢀNovalithIC™,ꢀOmniTune™,ꢀOPTIGA™,ꢀOptiMOS™,ꢀORIGA™,ꢀPOWERCODE™,  
PRIMARION™,ꢀPrimePACK™,ꢀPrimeSTACK™,ꢀPROFET™,ꢀPRO-SIL™,ꢀRASIC™,ꢀREAL3™,ꢀReverSave™,ꢀSatRIC™,ꢀSIEGET™,ꢀSIPMOS™,ꢀSmartLEWIS™,  
SOLIDꢀFLASH™,ꢀSPOC™,ꢀTEMPFET™,ꢀthinQꢁ™,ꢀTRENCHSTOP™,ꢀTriCore™.  
TrademarksꢀupdatedꢀAugustꢀ2015  
OtherꢀTrademarks  
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81726ꢀMünchen,ꢀGermany  
©ꢀ2017ꢀInfineonꢀTechnologiesꢀAG  
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Theꢀinformationꢀgivenꢀinꢀthisꢀdocumentꢀshallꢀinꢀnoꢀeventꢀbeꢀregardedꢀasꢀaꢀguaranteeꢀofꢀconditionsꢀorꢀcharacteristicsꢀ  
(“Beschaffenheitsgarantie”)ꢀ.  
Withꢀrespectꢀtoꢀanyꢀexamples,ꢀhintsꢀorꢀanyꢀtypicalꢀvaluesꢀstatedꢀhereinꢀand/orꢀanyꢀinformationꢀregardingꢀtheꢀapplicationꢀofꢀthe  
product,ꢀInfineonꢀTechnologiesꢀherebyꢀdisclaimsꢀanyꢀandꢀallꢀwarrantiesꢀandꢀliabilitiesꢀofꢀanyꢀkind,ꢀincludingꢀwithoutꢀlimitation  
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Information  
Forꢀfurtherꢀinformationꢀonꢀtechnology,ꢀdeliveryꢀtermsꢀandꢀconditionsꢀandꢀpricesꢀpleaseꢀcontactꢀyourꢀnearestꢀInfineon  
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Warnings  
Dueꢀtoꢀtechnicalꢀrequirements,ꢀcomponentsꢀmayꢀcontainꢀdangerousꢀsubstances.ꢀForꢀinformationꢀonꢀtheꢀtypesꢀinꢀquestion,  
pleaseꢀcontactꢀtheꢀnearestꢀInfineonꢀTechnologiesꢀOffice.  
TheꢀInfineonꢀTechnologiesꢀcomponentꢀdescribedꢀinꢀthisꢀDataꢀSheetꢀmayꢀbeꢀusedꢀinꢀlife-supportꢀdevicesꢀorꢀsystemsꢀand/or  
automotive,ꢀaviationꢀandꢀaerospaceꢀapplicationsꢀorꢀsystemsꢀonlyꢀwithꢀtheꢀexpressꢀwrittenꢀapprovalꢀofꢀInfineonꢀTechnologies,ꢀifꢀa  
failureꢀofꢀsuchꢀcomponentsꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀtheꢀfailureꢀofꢀthatꢀlife-support,ꢀautomotive,ꢀaviationꢀand  
aerospaceꢀdeviceꢀorꢀsystemꢀorꢀtoꢀaffectꢀtheꢀsafetyꢀorꢀeffectivenessꢀofꢀthatꢀdeviceꢀorꢀsystem.ꢀLifeꢀsupportꢀdevicesꢀorꢀsystemsꢀare  
intendedꢀtoꢀbeꢀimplantedꢀinꢀtheꢀhumanꢀbodyꢀorꢀtoꢀsupportꢀand/orꢀmaintainꢀandꢀsustainꢀand/orꢀprotectꢀhumanꢀlife.ꢀIfꢀtheyꢀfail,ꢀitꢀis  
reasonableꢀtoꢀassumeꢀthatꢀtheꢀhealthꢀofꢀtheꢀuserꢀorꢀotherꢀpersonsꢀmayꢀbeꢀendangered.  
Final Data Sheet  
11  
Rev.ꢀ2.0,ꢀꢀ2017-07-20  

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