IPB06N03LAG

更新时间:2024-09-18 06:03:14
品牌:INFINEON
描述:OptiMOS㈢2 Power-Transistor

IPB06N03LAG 概述

OptiMOS㈢2 Power-Transistor OptiMOS®2功率三极管

IPB06N03LAG 数据手册

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IPB06N03LA G  
OptiMOS®2 Power-Transistor  
Product Summary  
Features  
V DS  
25  
5.9  
50  
V
• Ideal for high-frequency dc/dc converters  
• Qualified according to JEDEC1) for target applications  
R
DS(on),max (SMD version)  
m  
A
I D  
• N-channel - Logic level  
• Excellent gate charge x R DS(on) product (FOM)  
• Very low on-resistance R DS(on)  
PG-TO263-3-2  
• Superior thermal resistance  
• 175 °C operating temperature  
• dv /dt rated  
• Pb-free lead plating; RoHS compliant  
Type  
Package  
Marking  
IPB06N03LA G  
PG-TO263-3-2  
06N03LA  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol Conditions  
Unit  
T C=25 °C2)  
I D  
Continuous drain current  
50  
50  
A
T C=100 °C  
T C=25 °C3)  
I D,pulse  
Pulsed drain current  
350  
225  
E AS  
I D=45 A, R GS=25 Ω  
Avalanche energy, single pulse  
mJ  
I D=50 A, V DS=20 V,  
di /dt =200 A/µs,  
Reverse diode dv /dt  
dv /dt  
6
kV/µs  
T
j,max=175 °C  
Gate source voltage4)  
V GS  
±20  
83  
V
P tot  
T C=25 °C  
Power dissipation  
W
°C  
T j, T stg  
Operating and storage temperature  
IEC climatic category; DIN IEC 68-1  
-55 ... 175  
55/175/56  
1) J-STD20 and JESD22  
Rev. 1.6  
page 1  
2006-05-10  
IPB06N03LA G  
Values  
typ.  
Parameter  
Symbol Conditions  
Unit  
min.  
max.  
Thermal characteristics  
R thJC  
Thermal resistance, junction - case  
SMD version, device on PCB  
-
-
-
-
-
-
1.8  
62  
40  
K/W  
R thJA  
minimal footprint  
6 cm2 cooling area5)  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V (BR)DSS  
V GS(th)  
V
V
GS=0 V, I D=1 mA  
DS=V GS, I D=40 µA  
Drain-source breakdown voltage  
Gate threshold voltage  
25  
-
-
V
1.2  
1.6  
2
V
DS=25 V, V GS=0 V,  
I DSS  
Zero gate voltage drain current  
-
0.1  
1
µA  
T j=25 °C  
V
DS=25 V, V GS=0 V,  
-
-
-
10  
10  
100  
T j=125 °C  
I GSS  
V
V
GS=20 V, V DS=0 V  
GS=4.5 V, I D=30 A,  
Gate-source leakage current  
100 nA  
R DS(on)  
Drain-source on-state resistance  
7.6  
9.5  
mΩ  
SMD version  
V
GS=10 V, I D=30 A,  
-
-
4.9  
1.2  
58  
5.9  
SMD version  
R G  
g fs  
Gate resistance  
-
-
|V DS|>2|I D|R DS(on)max  
I D=30 A  
,
Transconductance  
29  
S
2) Current is limited by bondwire; with an  
R
thJC
=1.8 K/W the chip is able to carry 91  
3) See figure 3  
4) T j,max=150 °C and duty cycle D <0.25 for  
V
GS
<-5 V  
5) Device on 40 mm x 40 mm x 1.5 mm  
epoxy PCB FR4 with 6 cm
2
(one layer, 70  
Rev. 1.6  
page 2  
2006-05-10  
IPB06N03LA G  
Values  
typ.  
Parameter  
Symbol Conditions  
Unit  
min.  
max.  
Dynamic characteristics  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
C iss  
-
-
-
-
-
-
-
2093  
800  
98  
2653 pF  
1064  
V
GS=0 V, V DS=15 V,  
C oss  
Crss  
t d(on)  
t r  
f =1 MHz  
147  
11  
16  
38  
45  
6.6  
ns  
30  
V
DD=15 V, V GS=10 V,  
I D=25 A, R G=2.7 Ω  
t d(off)  
t f  
Turn-off delay time  
Fall time  
30  
4.4  
Gate Charge Characteristics6)  
Gate to source charge  
Gate charge at threshold  
Gate to drain charge  
Switching charge  
Q gs  
-
-
-
-
-
-
6.7  
3.3  
4.6  
8.0  
17  
9.0  
4.2  
6.9  
11  
22  
-
nC  
Q g(th)  
Q gd  
V
V
DD=15 V, I D=25 A,  
GS=0 to 5 V  
Q sw  
Q g  
Gate charge total  
V plateau  
Gate plateau voltage  
3.2  
V
V
V
DS=0.1 V,  
Q g(sync)  
Q oss  
Gate charge total, sync. FET  
Output charge  
-
-
15  
17  
19  
22  
nC  
GS=0 to 5 V  
V
DD=15 V, V GS=0 V  
Reverse Diode  
I S  
Diode continous forward current  
Diode pulse current  
-
-
-
-
50  
A
T C=25 °C  
I S,pulse  
350  
V
GS=0 V, I F=50 A,  
V SD  
Q rr  
Diode forward voltage  
-
-
0.94  
-
1.2  
10  
V
T j=25 °C  
V R=15 V, I F=I S,  
di F/dt =400 A/µs  
Reverse recovery charge  
nC  
6) See figure 16 for gate charge parameter definition  
Rev. 1.6  
page 3  
2006-05-10  
IPB06N03LA G  
1 Power dissipation  
2 Drain current  
P
tot=f(T C)  
I D=f(T C); V GS10 V  
90  
80  
70  
60  
50  
40  
30  
20  
10  
60  
40  
20  
0
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
T
C [°C]  
T
C [°C]  
3 Safe operating area  
I D=f(V DS); T C=25 °C; D =0  
parameter: t p  
4 Max. transient thermal impedance  
thJC=f(t p)  
Z
parameter: D =t p/T  
1000  
10  
1 µs  
limited by on-state  
resistance  
0.5  
10 µs  
1
100  
0.2  
0.1  
100 µs  
DC  
0.05  
0.1  
0.02  
1 ms  
single pulse  
0.01  
10  
10 ms  
0.01  
1
0.001  
10-6  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
0.1  
1
10  
100  
0
V
DS [V]  
t p [s]  
Rev. 1.6  
page 4  
2006-05-10  
IPB06N03LA G  
5 Typ. output characteristics  
I D=f(V DS); T j=25 °C  
6 Typ. drain-source on resistance  
DS(on)=f(I D); T j=25 °C  
R
parameter: V GS  
parameter: V GS  
25  
100  
3.2 V  
3.5 V  
3.8 V  
10 V  
4.1 V  
4.5 V  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
4.1 V  
3.8 V  
3 V  
20  
15  
10  
5
3.5 V  
3.2 V  
4.5 V  
10 V  
3 V  
2.8 V  
0
0
20  
40  
60  
80  
100  
0
1
2
3
V
DS [V]  
ID [A]  
7 Typ. transfer characteristics  
I D=f(V GS); |V DS|>2|I D|R DS(on)max  
parameter: T j  
8 Typ. forward transconductance  
g fs=f(I D); T j=25 °C  
100  
90  
80  
70  
60  
50  
40  
30  
20  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
175 °C  
25 °C  
10  
0
0
1
2
3
4
5
0
20  
40  
60  
80  
V
GS [V]  
I
D [A]  
Rev. 1.6  
page 5  
2006-05-10  
IPB06N03LA G  
9 Drain-source on-state resistance  
10 Typ. gate threshold voltage  
GS(th)=f(T j); V GS=V DS  
R
DS(on)=f(T j); I D=30 A; V GS=10 V  
V
parameter: I D  
12  
11  
10  
9
2.5  
2
1.5  
1
400 µA  
8
98 %  
7
40 µA  
6
typ  
5
4
3
2
1
0
0.5  
0
-60  
-20  
20  
60  
100  
140  
180  
-60  
-20  
20  
60  
T j [°C]  
100  
140  
180  
T j [°C]  
11 Typ. Capacitances  
12 Forward characteristics of reverse diode  
I F=f(V SD  
C =f(V DS); V GS=0 V; f =1 MHz  
)
parameter: T j  
10000  
1000  
25 °C  
Ciss  
Coss  
1000  
100  
10  
100  
10  
175°C 98%  
175 °C  
Crss  
25°C 98%  
1
0
5
10  
15  
20  
25  
30  
0.0  
0.5  
1.0  
1.5  
2.0  
V
DS [V]  
V
SD [V]  
Rev. 1.6  
page 6  
2006-05-10  
IPB06N03LA G  
13 Avalanche characteristics  
AS=f(t AV); R GS=25 Ω  
14 Typ. gate charge  
GS=f(Q gate); I D=25 A pulsed  
V
I
parameter: Tj(start)  
parameter: V DD  
100  
12  
15 V  
20 V  
25 °C  
10  
8
100 °C  
5 V  
150 °C  
10  
6
4
2
1
1
0
0
10  
100  
1000  
10  
20  
Q gate [nC]  
30  
40  
t
AV [µs]  
15 Drain-source breakdown voltage  
16 Gate charge waveforms  
V
BR(DSS)=f(T j); I D=1 mA  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
V GS  
Q g  
V gs(th)  
Q g(th)  
Q sw  
Q gd  
Q gate  
Q gs  
-60  
-20  
20  
60  
100  
140  
180  
T j [°C]  
Rev. 1.6  
page 7  
2006-05-10  
IPB06N03LA G  
Package Outline  
PG-TO263-3-2  
Rev. 1.6  
page 8  
2006-05-10  
IPB06N03LA G  
Published by  
Infineon Technologies AG  
81726 München, Germany  
© Infineon Technologies AG 2006.  
All Rights Reserved.  
Attention please!  
The information given in this data sheet shall in no event be regarded as a guarantee of conditions or  
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values  
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby  
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of  
non-infringement of intellectual property rights of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices please contact your nearest  
Infineon Technologies Office (www.infineon.com ).  
Warnings  
Due to technical requirements components may contain dangerous substances. For information on the types in  
question please contact your nearest Infineon Technologies Office.  
Infineon Technologies Components may only be used in life-support devices or systems with the express written  
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure  
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support  
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain  
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may  
be endangered.  
Rev. 1.6  
page 9  
2006-05-10  

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