IPD036N04LG [INFINEON]

OptiMOS3 Power-Transistor; OptiMOS3功率三极管
IPD036N04LG
型号: IPD036N04LG
厂家: Infineon    Infineon
描述:

OptiMOS3 Power-Transistor
OptiMOS3功率三极管

文件: 总9页 (文件大小:232K)
中文:  中文翻译
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IPD036N04L G  
OptiMOS®3 Power-Transistor  
Product Summary  
Features  
V DS  
40  
3.6  
90  
V
• Fast switching MOSFET for SMPS  
• Optimized technology for DC/DC converters  
• Qualified according to JEDEC1) for target applications  
R DS(on),max  
I D  
m  
A
• N-channel, logic level  
• Excellent gate charge x R DS(on) product (FOM)  
• Very low on-resistance R DS(on)  
• 100% Avalanche tested  
• Pb-free plating; RoHS compliant  
Type  
IPD036N04L G  
Package  
Marking  
PG-TO252-3  
036N04L  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol Conditions  
Unit  
I D  
V GS=10 V, T C=25 °C  
Continuous drain current  
90  
87  
90  
A
V
V
GS=10 V, T C=100 °C  
GS=4.5 V, T C=25 °C  
V
GS=4.5 V,  
75  
T C=100 °C  
Pulsed drain current2)  
I D,pulse  
I AS  
T C=25 °C  
400  
90  
Avalanche current, single pulse3)  
Avalanche energy, single pulse  
Gate source voltage  
T C=25 °C  
E AS  
V GS  
I D=90 A, R GS=25 Ω  
55  
mJ  
V
±20  
1) J-STD20 and JESD22  
Rev. 1.0  
page 1  
2007-12-06  
IPD036N04L G  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol Conditions  
Unit  
P tot  
T C=25 °C  
Power dissipation  
94  
W
T j, T stg  
Operating and storage temperature  
IEC climatic category; DIN IEC 68-1  
-55 ... 175  
55/175/56  
°C  
Values  
typ.  
Parameter  
Symbol Conditions  
Unit  
min.  
max.  
Thermal characteristics  
R thJC  
Thermal resistance, junction - case  
SMD version, device on PCB  
-
-
-
-
-
-
1.6  
75  
50  
K/W  
R thJA  
minimal footprint  
6 cm² cooling area4)  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V (BR)DSS V GS=0 V, I D=1 mA  
Drain-source breakdown voltage  
Gate threshold voltage  
40  
-
-
-
V
V GS(th)  
V DS=V GS, I D=45 µA  
1.2  
2
V DS=40 V, V GS=0 V,  
T j=25 °C  
I DSS  
Zero gate voltage drain current  
-
-
0.1  
10  
1
µA  
V
DS=40 V, V GS=0 V,  
100  
T j=125 °C  
I GSS  
V GS=20 V, V DS=0 V  
Gate-source leakage current  
-
-
-
-
10  
3.9  
3.0  
1.6  
100 nA  
Drain-source on-state resistance  
R DS(on) V GS=4.5 V, I D=90 A  
V GS=10 V, I D=90 A  
R G  
4.9  
3.6  
-
mΩ  
Gate resistance  
|V DS|>2|I D|R DS(on)max  
,
g fs  
Transconductance  
85  
170  
-
S
I D=90 A  
2) See figure 3 for more detailed information  
3) See figure 13 for more detailed information  
2
4) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
Rev. 1.0  
page 2  
2007-12-06  
IPD036N04L G  
Values  
typ.  
Parameter  
Symbol Conditions  
Unit  
min.  
max.  
Dynamic characteristics  
C iss  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
-
-
-
-
-
-
-
4700  
1000  
54  
6300 pF  
V GS=0 V, V DS=20 V,  
C oss  
Crss  
t d(on)  
t r  
1300  
-
f =1 MHz  
9.3  
-
-
-
-
ns  
5.4  
V DD=20 V, V GS=10 V,  
I D=30 A, R G=1.6 Ω  
t d(off)  
t f  
Turn-off delay time  
Fall time  
37  
6.0  
Gate Charge Characteristics5)  
Gate to source charge  
Gate charge at threshold  
Gate to drain charge  
Switching charge  
Q gs  
-
-
-
-
-
-
14  
7.4  
6.1  
13  
-
-
nC  
Q g(th)  
Q gd  
-
V DD=20 V, I D=30 A,  
V
GS=0 to 10 V  
Q sw  
-
Q g  
Gate charge total  
59  
78  
-
V plateau  
Gate plateau voltage  
3.0  
V
V DD=20 V, I D=30 A,  
GS=0 to 4.5 V  
Q g  
Gate charge total  
-
28  
38  
nC  
V
V DS=0.1 V,  
GS=0 to 10 V  
Q g(sync)  
Gate charge total, sync. FET  
Output charge  
-
-
55  
37  
-
-
V
Q oss  
V DD=20 V, V GS=0 V  
Reverse Diode  
I S  
Diode continuous forward current  
Diode pulse current  
-
-
-
-
78  
A
T C=25 °C  
I S,pulse  
400  
V GS=0 V, I F=90 A,  
T j=25 °C  
V SD  
Diode forward voltage  
-
-
0.92  
45  
1.2  
-
V
V R=20 V, I F=I S,  
di F/dt =400 A/µs  
Q rr  
Reverse recovery charge  
nC  
5) See figure 16 for gate charge parameter definition  
Rev. 1.0  
page 3  
2007-12-06  
IPD036N04L G  
1 Power dissipation  
2 Drain current  
P
tot=f(T C)  
I D=f(T C); V GS10 V  
100  
100  
80  
60  
40  
20  
0
80  
60  
40  
20  
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
T C [°C]  
T C [°C]  
3 Safe operating area  
I D=f(V DS); T C=25 °C; D =0  
parameter: t p  
4 Max. transient thermal impedance  
Z thJC=f(t p)  
parameter: D =t p/T  
103  
10  
1 µs  
limited by on-state  
resistance  
10 µs  
102  
100 µs  
1
DC  
0.5  
1 ms  
101  
0.2  
0.1  
10 ms  
0.05  
0.1  
100  
0.02  
0.01  
single pulse  
10-1  
0
0
0
0
0
0
1
0.01  
10-1  
100  
101  
102  
10-6  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
V DS [V]  
t p [s]  
Rev. 1.0  
page 4  
2007-12-06  
IPD036N04L G  
5 Typ. output characteristics  
I D=f(V DS); T j=25 °C  
6 Typ. drain-source on resistance  
R DS(on)=f(I D); T j=25 °C  
parameter: V GS  
parameter: V GS  
320  
12  
3 V  
5 V  
4.5 V  
3.2 V  
280  
10 V  
10  
240  
8
3.5 V  
200  
160  
120  
80  
4 V  
6
4
2
0
4 V  
4.5 V  
5 V  
3.5 V  
3.2 V  
10 V  
40  
3 V  
2.8 V  
0
0
1
2
3
0
20  
40  
60  
80  
100  
V DS [V]  
ID [A]  
7 Typ. transfer characteristics  
I D=f(V GS); |V DS|>2|I D|R DS(on)max  
parameter: T j  
8 Typ. forward transconductance  
g fs=f(I D); T j=25 °C  
200  
160  
120  
80  
240  
200  
160  
120  
80  
40  
40  
175 °C  
25 °C  
0
0
0
1
2
3
4
5
0
40  
80  
120  
160  
200  
V GS [V]  
ID [A]  
Rev. 1.0  
page 5  
2007-12-06  
IPD036N04L G  
9 Drain-source on-state resistance  
10 Typ. gate threshold voltage  
R
DS(on)=f(T j); I D=90 A; V GS=10 V  
V GS(th)=f(T j); V GS=V DS; I D=250 µA  
8
7
6
2.5  
2
5
1.5  
1
98 %  
4
typ  
3
2
1
0
0.5  
0
-60  
-20  
20  
60  
100  
140  
180  
-60  
-20  
20  
60  
100  
140  
180  
T j [°C]  
T j [°C]  
11 Typ. capacitances  
12 Forward characteristics of reverse diode  
I F=f(V SD  
C =f(V DS); V GS=0 V; f =1 MHz  
)
parameter: T j  
104  
1000  
25 °C, 98%  
Ciss  
175 °C, 98%  
Coss  
103  
102  
101  
100  
25 °C  
175 °C  
10  
Crss  
1
0
10  
20  
V DS [V]  
30  
40  
0.0  
0.5  
1.0  
V SD [V]  
1.5  
2.0  
Rev. 1.0  
page 6  
2007-12-06  
IPD036N04L G  
13 Avalanche characteristics  
AS=f(t AV); R GS=25 Ω  
14 Typ. gate charge  
GS=f(Q gate); I D=30 A pulsed  
V
I
parameter: T j(start)  
parameter: V DD  
100  
12  
20 V  
25 °C  
10  
8
8 V  
100 °C  
32 V  
150 °C  
10  
6
z
4
2
1
10-1  
0
100  
101  
102  
103  
0
10  
20  
30  
40  
50  
60  
70  
t AV [µs]  
Q gate [nC]  
15 Drain-source breakdown voltage  
16 Gate charge waveforms  
V
BR(DSS)=f(T j); I D=1 mA  
45  
V GS  
Q g  
40  
35  
30  
25  
20  
V gs(th)  
Q g(th)  
Q sw  
Q gd  
Q gate  
Q gs  
-60  
-20  
20  
60  
100  
140  
180  
T j [°C]  
Rev. 1.0  
page 7  
2007-12-06  
IPD036N04L G  
Package Outline  
PG-TO252-3  
Rev. 1.0  
page 8  
2007-12-06  
IPD036N04L G  
Published by  
Infineon Technologies AG  
81726 Munich, Germany  
© 2007 Infineon Technologies AG  
All Rights Reserved.  
Legal Disclaimer  
The information given in this document shall in no event be regarded as a guarantee of  
conditions or characteristics. With respect to any examples or hints given herein, any typical  
values stated herein and/or any information regarding the application of the device,  
Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind,  
including without limitation, warranties of non-infringement of intellectual property rights  
of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices, please  
contact the nearest Infineon Technologies Office  
(www.infineon.com).  
Warnings  
Due to technical requirements, components may contain dangerous substances. For information  
on the types in question, please contact the nearest Infineon Technologies Office.  
Infineon Technologies components may be used in life-support devices or systems only with  
the express written approval of Infineon Technologies, if a failure of such components can  
reasonably be expected to cause the failure of that life-support device or system or to affect  
the safety or effectiveness of that device or system. Life support devices or systems are  
intended to be implanted in the human body or to support and/or maintain and sustain  
and/or protect human life. If they fail, it is reasonable to assume that the health of the user  
or other persons may be endangered.  
Rev. 1.0  
page 9  
2007-12-06  

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