IPD050N03LGATMA1 [INFINEON]

Power Field-Effect Transistor, 50A I(D), 30V, 0.0073ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, GREEN, PLASTIC, TO-252, 3 PIN;


型号：	IPD050N03LGATMA1
厂家：	Infineon
描述：	Power Field-Effect Transistor, 50A I(D), 30V, 0.0073ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, GREEN, PLASTIC, TO-252, 3 PIN
文件：	总12页 (文件大小：1000K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Type

IPD050N03L G

IPS050N03L G

IPF050N03L G

IPU050N03L G

OptiMOS^®3 Power-Transistor

Product Summary

Features

V_DS

• Fast switching MOSFET for SMPS

• Optimized technology for DC/DC converters

• Qualified according to JEDEC¹⁾for target applications

R_DS(on),max

I_D

• N-channel, logic level

• Excellent gate charge x R _DS(on)product (FOM)

• Very low on-resistance R _DS(on)

• Avalanche rated

• Pb-free plating; RoHS compliant

Type

IPD050N03L G

IPF050N03L G

IPS050N03L G

IPU050N03L G

Package

Marking

PG-TO252-3-11

050N03L

PG-TO252-3-23

050N03L

PG-TO251-3-11

050N03L

PG-TO251-3-21

050N03L

Maximum ratings, at T _j=25 °C, unless otherwise specified

Value

Parameter

Symbol Conditions

Unit

I _D

V _GS=10 V, T _C=25 °C

Continuous drain current

V _GS=10 V, T _C=100 °C

V _GS=4.5 V, T _C=25 °C

V _GS=4.5 V,

T _C=100 °C

Pulsed drain current²⁾

I _D,pulse

I _AS

T _C=25 °C

350

Avalanche current, single pulse³⁾

Avalanche energy, single pulse

T _C=25 °C

E _AS

I _D=35 A, R _GS=25 W

I _D=50 A, V _DS=24 V,

di /dt =200 A/µs,

T _j,max=175 °C

Reverse diode dv /dt

dv /dt

kV/µs

V _GS

Gate source voltage

¹⁾J-STD20 and JESD22

±20

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Maximum ratings, at T _j=25 °C, unless otherwise specified

Value

Parameter

Symbol Conditions

Unit

P _tot

T _C=25 °C

Power dissipation

T _j, T _stg

Operating and storage temperature

IEC climatic category; DIN IEC 68-1

-55 ... 175

55/175/56

°C

Values

typ.

Parameter

Symbol Conditions

Unit

min.

max.

Thermal characteristics

R _thJC

Thermal resistance, junction - case

SMD version, device on PCB

2.2

K/W

R _thJA

minimal footprint

6 cm² cooling area⁴⁾

Electrical characteristics, at T _j=25 °C, unless otherwise specified

Static characteristics

V _(BR)DSSV _GS=0 V, I _D=1 mA

V _GS(th)V _DS=V _GS, I _D=250 µA

Drain-source breakdown voltage

Gate threshold voltage

2.2

V _DS=30 V, V _GS=0 V,

T _j=25 °C

I _DSS

Zero gate voltage drain current

0.1

µA

V _DS=30 V, V _GS=0 V,

T _j=125 °C

100

I _GSS

V _GS=20 V, V _DS=0 V

Gate-source leakage current

5.8

4.2

1.5

100 nA

Drain-source on-state resistance⁵⁾

R _DS(on)V _GS=4.5 V, I _D=30 A

V _GS=10 V, I _D=30 A

R _G

7.3

Gate resistance

|V _DS|>2|I _D|R _DS(on)max

I _D=30 A

g _fs

Transconductance

²⁾See figure 3 for more detailed information

³⁾See figure 13 for more detailed information

⁴⁾Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain

connection. PCB is vertical in still air.

⁵⁾Measured from drain tab to source pin

Rev. 2.0

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Values

Parameter

Symbol Conditions

Unit

min.

typ.

max.

Dynamic characteristics

C _iss

Input capacitance

Output capacitance

Reverse transfer capacitance

Turn-on delay time

Rise time

2400

920

3200 pF

V _GS=0 V, V _DS=15 V,

f =1 MHz

C _oss

C_rss

t _d(on)

t _r

1200

6.7

V _DD=15 V, V _GS=10 V,

I _D=30 A, R _G,ext=1.6 W

t _d(off)

t _f

Turn-off delay time

Fall time

3.8

Gate Charge Characteristics⁶⁾

Gate to source charge

Gate charge at threshold

Gate to drain charge

Switching charge

Q _gs

7.4

3.8

3.5

7.1

Q _g(th)

Q _gd

V _DD=15 V, I _D=30 A,

V _GS=0 to 4.5 V

Q _sw

Q _g

Gate charge total

V _plateau

Gate plateau voltage

3.1

V _DD=15 V, I _D=30 A,

V _GS=0 to 10 V

Q _g

Gate charge total

V _DS=0.1 V,

V _GS=0 to 4.5 V

Q _g(sync)

Gate charge total, sync. FET

Output charge

Q _oss

V _DD=15 V, V _GS=0 V

Reverse Diode

I _S

Diode continuous forward current

Diode pulse current

T _C=25 °C

I _S,pulse

350

V _GS=0 V, I _F=30 A,

T _j=25 °C

V _SD

Diode forward voltage

0.86

1.1

V _R=15 V, I _F=I _S,

di _F/dt =400 A/µs

Q _rr

Reverse recovery charge

⁶⁾See figure 16 for gate charge parameter definition

Rev. 2.0

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1 Power dissipation

2 Drain current

P _tot=f(T _C)

I _D=f(T _C); V _GS≥10 V

100

150

200

100

150

200

T_C[°C]

3 Safe operating area

I _D=f(V _DS); T _C=25 °C; D =0

parameter: t _p

4 Max. transient thermal impedance

Z _thJC=f(t _p)

parameter: D =t _p/T

10³

1 µs

limited by on-state

resistance

10 µs

10²

0.5

100 µs

0.2

0.1

10¹

1 ms

0.05

10 ms

0.1

0.02

10⁰

0.01

single pulse

10^-1

0.01

10^-1

10⁰

10¹

10²

10^-6

10^-5

10^-4

10^-3

10^-2

10^-1

10⁰

V_DS[V]

t_p[s]

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5 Typ. output characteristics

I _D=f(V _DS); T _j=25 °C

6 Typ. drain-source on resistance

R _DS(on)=f(I _D); T _j=25 °C

parameter: V _GS

150

3.2 V

10 V

120

5 V

4.5 V

3.5 V

4 V

4.5 V

5 V

3.5 V

3.2 V

10 V

11.5 V

3 V

2.8 V

100

V_DS[V]

I_D[A]

7 Typ. transfer characteristics

I _D=f(V _GS); |V _DS|>2|I _D|R _DS(on)max

parameter: T _j

8 Typ. forward transconductance

g _fs=f(I _D); T _j=25 °C

150

120

150

120

175 °C

25 °C

100

V_GS[V]

I_D[A]

Rev. 2.0

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9 Drain-source on-state resistance

10 Typ. gate threshold voltage

R _DS(on)=f(T _j); I _D=30 A; V _GS=10 V

V _GS(th)=f(T _j); V _GS=V _DS; I _D=250 µA

2.5

1.5

98 %

typ

0.5

-60

-20

100

140

180

-60

-20

100

140

180

T_j[°C]

11 Typ. capacitances

12 Forward characteristics of reverse diode

I _F=f(V _SD

C =f(V _DS); V _GS=0 V; f =1 MHz

)

parameter: T _j

10⁴

10³

Ciss

25 °C, 98%

10³

10²

10¹

10²

25 °C

Coss

175 °C

175 °C, 98%

10¹

Crss

10⁰

0.5

1.5

V_DS[V]

V_SD[V]

Rev. 2.0

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13 Avalanche characteristics

14 Typ. gate charge

V _GS=f(Q _gate); I _D=30 A pulsed

parameter: V _DD

I _AS=f(t _AV); R _GS=25 W

parameter: T _j(start)

100

15 V

6 V

24 V

25 °C

150 °C

100 °C

10^-1

10⁰

10¹

t_AV[µs]

10²

10³

Q_gate[nC]

15 Drain-source breakdown voltage

16 Gate charge waveforms

V _BR(DSS)=f(T _j); I _D=1 mA

V _GS

Q_g

V _gs(th)

Q_g(th)

Q_sw

Q_gd

Q_gate

Q_gs

-60

-20

100

140

180

T_j[°C]

Rev. 2.0

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Package Outline

PG-TO252-3-11

Rev. 2.0

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Package Outline

PG-TO252-3-23

PG-TO251-3-11: Outline

PG-TO251-3-21: Outline

Rev. 2.0

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Package Outline

PG-TO251-3-11

PG-TO251-3-11: Outline

PG-TO251-3-21: Outline

Rev. 2.0

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Package Outline

PG-TO251-3-21

PG-TO251-3-11: Outline

PG-TO251-3-21: Outline

Rev. 2.0

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Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of

conditions or characteristics. With respect to any examples or hints given herein, any typical

values stated herein and/or any information regarding the application of the device,

Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind,

including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please

contact the nearest Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances. For information

on the types in question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with

the express written approval of Infineon Technologies, if a failure of such components can

reasonably be expected to cause the failure of that life-support device or system or to affect

the safety or effectiveness of that device or system. Life support devices or systems are

intended to be implanted in the human body or to support and/or maintain and sustain

and/or protect human life. If they fail, it is reasonable to assume that the health of the user

or other persons may be endangered.

Rev. 2.0

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2013-10-28

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