IPD053N06NATMA1 [INFINEON]

Power Field-Effect Transistor, 45A I(D), 60V, 0.0053ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, GREEN, PLASTIC, TO-252, DPAK-3;
IPD053N06NATMA1
型号: IPD053N06NATMA1
厂家: Infineon    Infineon
描述:

Power Field-Effect Transistor, 45A I(D), 60V, 0.0053ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, GREEN, PLASTIC, TO-252, DPAK-3

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中文:  中文翻译
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IPD053N06N  
OptiMOSTM Power-Transistor  
Features  
Product Summary  
• Optimized for high performance SMPS, e.g. sync. rec.  
• 100% avalanche tested  
VDS  
60  
5.3  
45  
V
RDS(on),max  
ID  
mW  
A
• Superior thermal resistance  
• N-channel  
QOSS  
nC  
nC  
32  
27  
• Qualified according to JEDEC1) for target applications  
• Pb-free lead plating; RoHS compliant  
• Halogen-free according to IEC61249-2-21  
QG(0V..10V)  
PG-TO252-3  
Type  
Package  
Marking  
IPD053N06N  
PG-TO252-3  
053N06N  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol Conditions  
Unit  
I D  
V GS=10 V, T C=25 °C  
Continuous drain current  
45  
45  
A
V GS=10 V, T C=100 °C  
V GS=10 V, T C=25 °C,  
R thJA =50K/W  
18  
Pulsed drain current2)  
I D,pulse  
E AS  
T C=25 °C  
180  
60  
Avalanche energy, single pulse3)  
Gate source voltage  
I D=45 A, R GS=25 W  
mJ  
V
V GS  
±20  
1) J-STD20 and JESD22  
2) See figure 3 for more detailed information  
3) See figure 13 for more detailed information  
4) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
Rev.2.2  
page 1  
2012-12-20  
IPD053N06N  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol Conditions  
Unit  
P tot  
T C=25 °C  
Power dissipation  
83  
W
T A=25 °C,  
R thJA=50 K/W  
3.0  
T j, T stg  
Operating and storage temperature  
IEC climatic category; DIN IEC 68-1  
-55 ... 175  
55/175/56  
°C  
Values  
typ.  
Parameter  
Symbol Conditions  
Unit  
min.  
max.  
Thermal characteristics  
R thJC  
R thJA  
Thermal resistance, junction - case  
Device on PCB  
bottom  
-
-
-
-
-
-
1.8  
62  
40  
K/W  
minimal footprint  
6 cm² cooling area4)  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V (BR)DSS V GS=0 V, I D=1 mA  
V GS(th) V DS=V GS, I D=36 µA  
Drain-source breakdown voltage  
Gate threshold voltage  
60  
-
-
V
2.1  
2.8  
3.3  
V DS=60 V, V GS=0 V,  
T j=25 °C  
I DSS  
Zero gate voltage drain current  
-
-
0.5  
10  
1
µA  
V DS=60 V, V GS=0 V,  
T j=125 °C  
100  
I GSS  
V GS=20 V, V DS=0 V  
Gate-source leakage current  
-
-
-
-
10  
4.5  
6.0  
1.5  
100 nA  
Drain-source on-state resistance  
R DS(on) V GS=10 V, I D=45 A  
V GS=6 V, I D=12 A  
R G  
5.3  
8.0  
2.3  
mW  
Gate resistance  
W
|V DS|>2|I D|R DS(on)max  
I D=45 A  
,
g fs  
Transconductance  
38  
75  
-
S
Rev.2.2  
page 2  
2012-12-20  
IPD053N06N  
Values  
typ.  
Parameter  
Symbol Conditions  
Unit  
min.  
max.  
Dynamic characteristics  
C iss  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
-
-
-
-
-
-
-
2000  
490  
22  
2500 pF  
613  
V GS=0 V, V DS=30 V,  
f =1 MHz  
C oss  
Crss  
t d(on)  
t r  
44  
12  
-
-
-
-
ns  
V DD=30 V, V GS=10 V,  
I D=45 A,  
12  
t d(off)  
t f  
Turn-off delay time  
Fall time  
20  
R G,ext,ext=3 W  
7
Gate Charge Characteristics5)  
Gate to source charge  
Gate charge at threshold  
Gate to drain charge  
Switching charge  
Q gs  
-
-
-
-
-
-
9
5
-
-
nC  
Q g(th)  
Q gd  
5
7
-
V DD=30 V, I D=45 A,  
V GS=0 to 10 V  
Q sw  
9
Q g  
Gate charge total  
27  
4.8  
32  
-
V plateau  
Gate plateau voltage  
V
V DS=0.1 V,  
V GS=0 to 10 V  
Q g(sync)  
Gate charge total, sync. FET  
Output charge  
-
-
24  
32  
-
-
nC  
Q oss  
V DD=30 V, V GS=0 V  
Reverse Diode  
I S  
Diode continuous forward current  
Diode pulse current  
-
-
-
-
45  
A
V
T C=25 °C  
I S,pulse  
180  
V GS=0 V, I F=45 A,  
T j=25 °C  
V SD  
Diode forward voltage  
-
1.0  
1.2  
t rr  
Reverse recovery time  
-
-
32  
28  
51  
-
ns  
V R=30 V, I F=45A ,  
di F/dt =100 A/µs  
Q rr  
Reverse recovery charge  
nC  
Rev.2.2  
page 3  
2012-12-20  
IPD053N06N  
1 Power dissipation  
2 Drain current  
P tot=f(T C)  
I D=f(T C); V GS≥10 V  
100  
80  
60  
40  
20  
0
50  
40  
30  
20  
10  
0
0
25  
50  
75 100 125 150 175 200  
0
25  
50  
75 100 125 150 175 200  
TC [°C]  
TC [°C]  
3 Safe operating area  
4 Max. transient thermal impedance  
Z thJC=f(t p)  
I D=f(V DS); T C=25 °C; D =0  
parameter: t p  
parameter: D =t p/T  
103  
10  
limited by on-state  
resistance  
1 µs  
10 µs  
102  
101  
100  
10-1  
1
100 µs  
0.5  
0.2  
0.1  
1 ms  
10 ms  
DC  
0.05  
0.02  
0.1  
0.01  
single pulse  
0.01  
10-1  
100  
101  
102  
0.00001 0.0001  
0.001  
0.01  
0.1  
1
VDS [V]  
tp [s]  
Rev.2.2  
page 4  
2012-12-20  
IPD053N06N  
5 Typ. output characteristics  
I D=f(V DS); T j=25 °C  
6 Typ. drain-source on resistance  
R DS(on)=f(I D); T j=25 °C  
parameter: V GS  
parameter: V GS  
180  
16  
14  
10 V  
7 V  
160  
140  
120  
100  
80  
6 V  
5.5 V  
5 V  
6 V  
12  
10  
8
5.5 V  
6
7 V  
60  
5 V  
10 V  
4
40  
2
20  
0
0
0.0  
0.5  
1.0  
1.5  
VDS [V]  
2.0  
2.5  
3.0  
0
20 40 60 80 100 120 140 160 180  
ID [A]  
7 Typ. transfer characteristics  
I D=f(V GS); |V DS|>2|I D|R DS(on)max  
parameter: T j  
8 Typ. forward transconductance  
g fs=f(I D); T j=25 °C  
180  
160  
140  
120  
100  
80  
80  
70  
60  
50  
40  
30  
20  
10  
0
60  
40  
20  
175 °C  
25 °C  
0
0
2
4
6
8
0
5
10 15 20 25 30 35 40 45  
VGS [V]  
ID [A]  
Rev.2.2  
page 5  
2012-12-20  
IPD053N06N  
9 Drain-source on-state resistance  
10 Typ. gate threshold voltage  
R DS(on)=f(T j); I D=45 A; V GS=10 V  
V GS(th)=f(T j); V GS=V DS  
12  
11  
10  
9
5
4
3
8
7
max  
360 mA  
6
36 µA  
typ  
5
2
4
3
2
1
0
1
0
-60  
-20  
20  
60  
100  
140  
180  
-60  
-20  
20  
60  
100  
140  
180  
Tj [°C]  
Tj [°C]  
11 Typ. capacitances  
12 Forward characteristics of reverse diode  
I F=f(V SD  
C =f(V DS); V GS=0 V; f =1 MHz  
)
parameter: T j  
10000  
104  
103  
Ciss  
1000  
103  
102  
Coss  
100  
102  
101  
25 °C  
175 °C  
Crss  
10  
101  
100  
0
0
20  
40  
60  
0.5  
1
1.5  
VDS [V]  
VSD [V]  
Rev.2.2  
page 6  
2012-12-20  
IPD053N06N  
13 Avalanche characteristics  
14 Typ. gate charge  
V GS=f(Q gate); I D=45 A pulsed  
parameter: V DD  
I AS=f(t AV); R GS=25 W  
parameter: T j(start)  
100  
12  
10  
8
30 V  
12 V  
48 V  
100 °C  
125 °C  
25 °C  
10  
6
4
2
1
0
1
10  
100  
1000  
0
5
10  
15  
20  
25  
30  
tAV [µs]  
Qgate [nC]  
15 Drain-source breakdown voltage  
16 Gate charge waveforms  
V BR(DSS)=f(T j); I D=1 mA  
70  
66  
62  
58  
54  
50  
V GS  
Qg  
V gs(th)  
Qg(th)  
Qsw  
Qgd  
Qgate  
Qgs  
-60  
-20  
20  
60  
100  
140  
180  
Tj [°C]  
Rev.2.2  
page 7  
2012-12-20  
IPD053N06N  
Package Outline  
PG-TO252-3  
Rev.2.2  
page 8  
2012-12-20  
IPD053N06N  
Published by  
Infineon Technologies AG  
81726 Munich, Germany  
© 2011 Infineon Technologies AG  
All Rights Reserved.  
Legal Disclaimer  
The information given in this document shall in no event be regarded as a guarantee of  
conditions or characteristics. With respect to any examples or hints given herein, any typical  
values stated herein and/or any information regarding the application of the device,  
Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind,  
including without limitation, warranties of non-infringement of intellectual property rights  
Information  
For further information on technology, delivery terms and conditions and prices, please  
contact the nearest Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements, components may contain dangerous substances. For information  
on the types in question, please contact the nearest Infineon Technologies Office.  
Infineon Technologies components may be used in life-support devices or systems only with  
the express written approval of Infineon Technologies, if a failure of such components can  
reasonably be expected to cause the failure of that life-support device or system or to affect  
the safety or effectiveness of that device or system. Life support devices or systems are  
intended to be implanted in the human body or to support and/or maintain and sustain  
and/or protect human life. If they fail, it is reasonable to assume that the health of the user  
or other persons may be endangered.  
Rev.2.2  
page 9  
2012-12-20  

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