IPD2547A [INFINEON]
LED Display, 4-Character, 6.4mm;
| 型号： | IPD2547A |
| 厂家： | 
Infineon |
| 描述： | LED Display, 4-Character, 6.4mm |
| 文件： | 总9页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH EFFICIENCY RED IPD2545A
GREEN IPD2547A
YELLOW IPD2548A
0.252" 4-Character 5 x 7 Dot Matrix X-Y Stackable
Industrial Alphanumeric Programmable Display™
with Built-in CMOS Control Functions
Dimensions in inches (mm)
1.200 max.
(30.48)
.170
typ.
(4.32)
.300
typ.
.150 ref.
(3.81)
(7.62)
OSRAM
.490 max.
(12.45)
.252
(6.40)
.50
(12.70)
YYWW
Z
pin 1
indicator
Intensity Code
EIA Data Code
part no.
pin 1.
FEATURES
• Four 0.252" Dot Matrix Characters in Hermetic
Package
.19
(4.83)
.17 (4.32)
• Built-in Memory, Decoders, Multiplexer
and Drivers
• Viewing Angle, X axis 40°, Y axis 75°
• 128 Character ASCII Format (Upper and Lower
Case Characters)
.150 ref.
(3.81)
.18 typ. (4.57)
Tolerance:
.XX=.01 (.254)
.020 x .010 typ.
(.508 x .254)
.10 typ. (2.54)
.XXX=.005 (.127)
• Rugged Ceramic Package, Hermetic Sealed
Flat Glass Window
• Wide Temperature Operating Range for Industrial
Use, –55°C to +100°C
• 8-bit Bidirectional Data BUS
• READ/WRITE Capability
• Built-in Character Generator ROM
• TTL Compatible
• Easily Cascaded for Multidisplay Operation
• Less CPU Time Required
• Software Controlled Features:
– Programmable Highlight Attribute
(Blinking, Non-Blinking)
– Asynchronous Memory Clear Function
– Lamp Test
– Display Blank Function
– Single or Multiple Character Blinking
Function
DESCRIPTION
The IPD2545A (high efficiency red), IPD2547A (green), and IPD2548A
(yellow) are four digit, High Reliability/Industrial, dot matrix, Program-
mable Displays that are aimed at satisfying the most demanding
industrial display requirements.
They are designed for use in harsh environments. The devices are
constructed in a hermetic package using four 0.25-inch high 5 x 7 dot
matrix displays.
The devices incorporate the latest in CMOS technology which is the
heart of the device intelligence. The CMOS controller chip is controlled
by a user supplied eight bit data word on the bidirectional BUS. The
ASCII data and attribute data are word driven. This approach allows
the IPD254XA to interface using the same techniques as a micropro-
cessor peripheral.
Applications include: control panels, night viewing applications (red
light), cockpit monitors, night vision goggle viewable displays (green),
portable and vehicle technology as well as industrial controllers.
– Three Programmable Brightness Levels
2001 OSRAM Opto Semiconductors Inc.• San Jose, CA
www.infineon.com/opto • 408-456-4000
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
1
July 5, 2001-14
Maximum Ratings
Figure 2. Timing Characteristics—Data “Write” Cycle
DC Supply Voltage............................................ –0.5 to +6.0 Vdc
Input Voltage Relative to Ground
2.0 V
0.8 V
CE0,
CE1
*
(all inputs)............................................... –0.5 to V +0.5 Vdc
CC
T
CES
T
CEH
Operating Temperature .....................................–55°C to 100°C
Storage Temperature..........................................–65°C to 125°C
Thermal Resistance (θ )................................................30°C/W
JC
2.0 V
0.8 V
A0, A1
*
*
Important:
T
AS
T
AH
Refer to Appnote 18, “Using and Handling Intelligent Displays”. Since
this is a CMOS device, normal precautions should be taken to avoid
static damage.
2.0 V
0.8 V
D0–D6
T
DS
T
DH
Figure 1. Top View
2.0 V
0.8 V
RD
*
*
T
RS
T
RH
20
11
WR
2.0 V
0.8 V
T
W
T
ACC
DIGIT 3
DIGIT 2
DIGIT 1
DIGIT 0
Pin 1
10
Figure 3. Timing Characteristics—Data “Read” Cycle
2.0 V
0.8 V
CE0,
CE1
Pin Assignments
*
T
T
CEH
1
2
3
4
5
6
7
8
9
RD
Read
11 WR
12 D7
13 D6
14 D5
15 D4
16 D3
Write
Data MSB
Data
CES
CLK I/O Clock I/O
2.0 V
0.8 V
A0–A3
D0–D6
*
*
CLKSEL Clock Select
T
T
AH
AS
RST
CE1
CE0
A2
Reset
Data
2.0 V
0.8 V
DATA OUT
Chip Enable
Chip Enable
Data
T
DH
T
DD
Data
T
RI
2.0 V
0.8 V
Address MSB 17 D2
Address 18 D1
Address LSB 19 D0
20
Data
*
*
WR
RD
T
T
WH
WS
A1
Data
2.0 V
0.8 V
A0
Data LSB
—
T
R
10 GND
—
V
CC
T
RACC
Notes:
1. All input voltages are VIL=0.8 V, V =2.0 V.
IH
2. These waveforms are not edge triggered.
DC Characteristics
Parameter
–55°C
Min. Typ. Max.
+25°C
+100°C
Units
Condition
Min. Typ. Max.
Min. Typ. Max.
I
Blank
—
4.0
10
—
—
2.0
5.0
—
—
1.0
2.5
mA
V
=5.0 V
CC
CC
(A =1
all other inputs low)
2
I
I
—
220
250
160
190
125
160
mA
V
=5.0 V, 20 dots/digit,
CC
CC
(100% brightness)
(all inputs)
—
70
—
—
120
—
—
60
—
—
100
—
—
50
—
—
80
—
µA
V
V
V
V
=5.0 V, V =0.8 V
IL
CC
CC
CC
IH
V
V
(all inputs)
(all inputs)
2.0
—
2.0
—
2.0
—
=5.0 V 0.5 V
=5.0 V 0.5 V
IH
IL
0.8
0.8
0.8
V
2001 OSRAM Opto Semiconductors Inc.• San Jose, CA
www.infineon.com/opto • 408-456-4000
IPD2545A/7A/8A
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
2
July 5, 2001-14
Optical Characteristics
High Efficiency Red IPD2545A
Description
(4)
(4)
(4)
Symbol
Min.
Typ.
Units
Test Condition
V =5.0 V, # sign “ON” on all digits at
CC
(1,3)
(1,3)
(1,3)
Peak Luminous Intensity per LED
(Character Average)
I
75
150
µcd
V
ave
full brightness, T =25°C
A
Peak Wavelength
λ
λ
—
—
635
626
nm
nm
—
—
peak
dom
(2)
Dominant Wavelength
High Efficiency Green IPD2547A
Description
Symbol
Min.
Typ.
Units
Test Condition
Peak Luminous Intensity per LED
(Character Average)
I
75
150
µcd
V
=5.0 V, # sign “ON” on all digits at
V
ave
CC
full brightness, T =25°C
A
Peak Wavelength
λ
λ
—
—
568
574
nm
nm
—
—
peak
dom
(2)
Dominant Wavelength
Yellow IPD2548A
Description
Symbol
Min.
Typ.
Units
Test Condition
Peak Luminous Intensity per LED
(Character Average)
I
75
150
µcd
V
=5.0 V, # sign “ON” on all digits at
V
ave
CC
full brightness, T =25°C
A
Peak Wavelength
λ
λ
—
—
585
590
nm
nm
—
—
peak
dom
(2)
Dominant Wavelength
Notes:
1)
The displays are categorized for luminous intensity with the intensity category designated by a letter code on the bottom of the package.
2)
Dominant wavelength λ
color of the device.
is derived from the CIE chromaticity diagram and represents the single wavelength which defines the
dom
3)
The luminous stearance of the LED may be calculated using the following relationships.
2
2
L (cd/m )= I (Candela)/A (Meter)
V
V
2
L (Footlamberts)= πI (Candela)/A (Foot)
V
V
2
2
–7
–8
A=8.4 x 10 ft , 7.8 x 10
m
4)
All typical values specified at V =5.0 V and T =25°C unless otherwise noted.
CC
A
Pin Definitions
Pin Definitions (continued)
Pin Function Definition
Pin Function Definition
1
RD
Active low, will enable a processor to read
all registers.
9
A0
Address input (LSB).
Ground.
10
11
GND
WR
2
CLK I/O
If CLK SEL (pin 3) is low, then expect an
external clock source into this pin. If CLK
SEL is high, then this pin will be the master
or source for all other devices which have
CLK SEL low.
Write. Active low. If the device is selected,
a low on the write input loads the data into
memory.
12
13
14
15
16
17
18
19
20
D7
D6
D5
D4
D3
D2
D1
D0
Data Bus bit 7 (MSB).
Data Bus bit 6.
3
4
CLKSEL
RST
CLocK SELect determines the action of pin
2, CLK I/O. See section on Cascading for an
example.
Data Bus bit 5.
Data Bus bit 4.
Reset. The Reset pulse should be less than
1 ms. Reset is used only to synchronize
blinking and will not clear the display.
Data Bus bit 3.
Data Bus bit 2.
5
6
7
8
CE1
CE0
A2
Chip enable (active high).
Chip enable (active low).
Address input (MSB).
Address input.
Data Bus bit 1.
Data Bus bit 0 (LSB).
Positive power pin.
V
CC
A1
2001 OSRAM Opto Semiconductors Inc.• San Jose, CA
www.infineon.com/opto • 408-456-4000
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
IPD2545A/7A/8A
July 5, 2001-14
3
Switching Specifications (V =4.5 V)
CC
Write Cycle Timing
Parameter
Description
Specification Minimum
–55°C
1.0
1.0
10
0
+25°C
1.0
1.0
10
+100°C
1.0
1.0
10
Units
µs
µs
ns
(1)
T
T
Clear RAM
CLR
(1)
Clear RAM Disable
Address Setup
Chip Enable Setup
Read Enable Setup
Data Setup
CLRD
T
AS
T
0
0
ns
CES
RS
DS
W
T
T
T
10
20
60
20
20
0
10
10
ns
30
50
ns
Write Pulse
70
90
ns
T
Address Hold
Data Hold
30
40
ns
AH
T
30
40
ns
DH
T
Chip Enable Hold
Read Enable Hold
0
0
ns
CEH
RH
T
20
90
30
40
ns
T
Total Access Time=Setup Time+ Write
Time+Hold Time
110
140
ns
ACC
Switching specifications (V =4.5 V)
CC
Read Cycle Timing
Parameter
Description
Specification Minimum
–55°C
0
+25°C
0
+100°C
0
Units
ns
T
Address Setup
Chip Enable
AS
T
T
T
T
0
0
0
ns
CES
WS
DD
R
Write Enable Setup
Data Delay Time
Read Pulse
20
100
150
0
30
150
175
0
40
175
200
0
ns
ns
ns
T
Address Hold
ns
AH
T
Data Hold
0
0
0
ns
DH
T
T
T
T
Time to Tristate (Max. time)
Chip Enable Hold
Write Enable Hold
30
0
40
0
50
0
ns
TRI
ns
CEH
WH
RACC
30
200
40
245
50
290
ns
Total Access Time=Setup Time+ Read
Time+Time to Tristate
ns
(1)
T
Wait Time between Reads
0
0
0
ns
WAIT
Notes:
1)
Wait 1.0 µs between any Reads or Writes after writing a Control Word with a Clear (D7=1). Wait 1.0 µs
between any Reads or Writes after Clearing a Control Word with a Clear (D7=0). All other Reads and
Writes can be back to back.
2)
3)
All input voltages are (V =0.8 V, V =2.0 V)
IL
IH
Data out voltages are measured with 100 pF on the data bus and the ability to source=–40 µA and
sink=1.6 mA The rise and fall times are 60 ns. V =0.4 V, V =2.4 V.
OL
OH
2001 OSRAM Opto Semiconductors Inc.• San Jose, CA
www.infineon.com/opto • 408-456-4000
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
IPD2545A/7A/8A
July 5, 2001-14
4
Figure 4. Block Diagram
The Control Logic dictates all of the features of the display
device and is discussed in the Control Word section of this
data sheet.
14
8
Display Memory
8
Control
Reg
1x8
The Character Generator converts the 7-bit ASCII data into the
proper dot pattern for the 128 characters shown in the charac-
ter set chart.
D0-D7
(RAM) 4x8
128 Char
ROM
The Clock Source can originate either from the internal oscillator
clock or from an external source–usually from the output of
another IPD2545/7/8A in a multiple module display.
4
15
Output
Control
Logic
Decode
and
Mux
1
7
CE0,CE1
A0-A2
RD, WR
The Display Multiplexer controls all display output to the digit
drivers so no additional logic is required for a display system.
5
Output
Latch
1
The Column Drivers are connected directly to the display.
20
The Display has four digits. Each of the four digits is comprised
of 35 LEDs in a 5 x 7 dot array which makes up the alphanu-
meric characters.
3
OSC
Logic
Display
Multiplexer
Column
Drivers
CLK SEL
XCLK
RST
3
The intensity of the display can be varied by the Control Word in
steps of 0% (Blank), 25%, 50%, and full brightness.
3
20
Row
Drivers
The Reset pin when activated clears the internal counter. A reset is
usually done after power up and is of very short duration-nanosec-
onds or microseconds. If the reset pin is held low for a longer time
(milliseconds) some or all LEDs in the bottom row may light up.
The appearance of lit LEDs during a “reset” is not an indication of a
malfunctioning part. It is advisable to keep the reset pulse as short
as possible to avoid displaying a row of lit LEDs.
Display
Functional Description
The block diagram (Figure 4) includes 5 major blocks and inter-
nal registers (indicated by dotted lines).
Microprocessor Interface
Display Memory consists of a 5 x 8 bit RAM block. Each of the
four 8-bit words holds the 7-bits of ASCII data (bits D0–D6) and
an attribute select bit (Bit D7). The fifth 8-bit memory word is
used as a control word register. A detailed description of the
control register and its functions can be found under the head-
ing Control Word. Each 8-bit word is addressable and can be
read from or written to.
The interface to the microprocessor is through the address lines.
(A0–A2), the data bus (D0–D7), two chip select lines (CE0, CE1),
and read (RD) and write (WR) lines.
The CE0 should be held low when executing a read, or write
operation. CE1 must be held high.
The read and write lines are both active low. During a valid read
the data lines (D0–D7) become outputs. A valid write will enable
the data lines as inputs.
Mode Selection
CEO
CE1
1
RD
0
WR
0
Operation
None
Input Buffering
0
1
X
X
If a cable length of 6 inches or more is used, all inputs to the dis-
play should be buffered with a tri-state non-inverting buffer
mounted as close to the display as conveniently possible. Recom-
mended buffers are: 74LS245 for the data lines and 74LS244 for
the control lines.
X
X
X
None
0
X
X
None
X
1
1
None
0=Low logic level, 1=High logic level, X=Don’t care
Data Input Commands
CEO CE1 RD
WR A2
A1
X
0
A0
X
0
D7
X
X
0
D6
X
X
0
D5
X
X
1
D4
X
X
0
D3
X
X
0
D2
X
X
1
D1
X
X
0
D0
X
X
0
Operation
1
0
0
0
0
0
0
0
1
1
1
1
1
1
X
0
1
1
1
1
1
X
1
0
0
0
0
0
X
1
1
1
1
1
1
No Change
Read Digit 0 Data to Bus
($) Written to Digit 0
(W) Written to Digit 1
(f) Written to Digit 2
(3) Written to Digit 3
0
0
0
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
X
X
X
X
X
X
X
Char. Written to Digit 0
and Cursor Enabled
2001 OSRAM Opto Semiconductors Inc.• San Jose, CA
www.infineon.com/opto • 408-456-4000
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
IPD2545A/7A/8A
July 5, 2001-14
5
Programming the IPD2545/7/8A
Control Word
There are five registers within the IPD2545/7/8A display. Four
of these registers are used to hold the ASCII/attribute code of
the four display characters. The fifth register is the Control
Word, which is used to blink, blank, clear, or dim the entire dis-
play, or to change the presentation (attributes) of individual
characters.
When address bit A2 is taken low, the Control Word is
accessed. The same Control Word appears in all four of the
lower address spaces of the display. Through the Control Word,
the display can be cleared, the lamps can be tested, display
brightness can be selected, and attributes can be set for any
characters which have been loaded with their most significant
bit (D7) set high.
Addressing
Brightness (D0, D1): The state of the lower two bits of the
Control Word are used to set the brightness of the entire dis-
play, from 0% to 100%. The table below shows the correspon-
dence of these bits to the brightness.
The addresses within the display device are shown below. Digit
0 is the rightmost digit of the display, while Digit 3 is on the left.
Although there is only one Control Word, it is duplicated at the
four address locations 0-3. Data can be read from any of these
locations. When one of these locations is written to, all of them
will change together.
D7 D6 D5 D4 D3 D2 D1 D0 Operation
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
1
1
0
1
0
1
Blank
Address
Contents
25% brightness
50% brightness
Full brightness
A2
0
A1
X
A0
X
Control Word
Digit 0 (rightmost)
Digit 1
1
0
0
X=don't care
Attributes (D2–D4): Bits D2, D3, and D4 control the visual
attributes (i.e., blinking, alternate) of those display digits which
have been written with bit D7 set high. In order to use any of
the four attributes, the Cursor Enable bit (D4 in the Control
Word) must be set. When the Cursor Enable bit is set, and bit
D7 in a character location is set, the character will take on one
of the following display attributes.
1
0
1
1
1
0
Digit 2
1
1
1
Digit 3 (leftmost)
Bit D7 of any of the display digit locations is used to allow an
attribute to be assigned to that digit. The attributes are dis-
cussed in the next section. If Bit D7 is set to a one, that charac-
ter will be displayed using the attribute. If bit D7 is cleared, the
character will display normally.
Figure 5. Control Word Format
D7
D6
D5
D4
D3
Attributes
D2
D1
Brightness
D1 D0 Brightness
D0
Attribute
enable
Lamp
test
Blink
Clear
0
0
1
1
0
1
0
1
0% (blank)
25%
D3 D2 Attributes
50%
100%
0
0
Display Cursor instead
of Character
0
1
1
0
Blink Character
Display Blinking Cursor
instead of Character
Alternate Character
with Cursor
1
1
D4 Attribute enable
0
1
Disable above Attributes
Enable above Attributes
D5 Blink
0
1
Blink Attribute Disabled
Blink Entire Display
D6 Lamp test
0
1
Standard Operation
Display All Dots at 50% Brightness
D7 Clear
0
1
Standard Operation
Clear Entire Display
2001 OSRAM Opto Semiconductors Inc.• San Jose, CA
www.infineon.com/opto • 408-456-4000
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
IPD2545A/7A/8A
July 5, 2001-14
6
D7 D6 D5 D4 D3 D2 D1 D0 Operation
D7 D6 D5 D4 D3 D2 D1 D0 Operation
Lamp test
0
0
0
0
X
X
B
B
Disable highlight
attribute
0
1
0
0
X
X
X
X
Clear Data (D7): When D7 (D7=1) is set in the Control Word,
all display memory bits are reset to zero. A second Control
Word must be written into the chip with D7 (D7=0) reset to set
up attributes and brightness levels.
0
0
0
1
0
0
B
B
Display cursor*
instead of
character
0
0
0
0
0
0
1
1
0
1
1
0
B
B
B
B
Blink single
character
D7 D6 D5 D4 D3 D2 D1 D0 Operation
Display blinking
cursor* instead
of character
1
0
X
X
X
X
X
X
Clear
Cascading
0
0
0
1
1
1
B
B
Alternate charac-
ter with cursor*
Cascading the display (Figure 6) is a simple operation. The
requirements for cascading are: 1) decoding the correct
address to determine the chip select for each additional device,
2) assuring that all devices are reset simultaneously, and
3) selecting one display as the clock source and setting all oth-
ers to accept clock input (the reason for cascading the clock is
to synchronize the flashing of multiple displays). One display as
a source is capable of driving six other displays. If more dis-
plays are required, a buffer will be necessary. The source dis-
play must have pin 3 tied high to output clock signals. All other
displays must have pin 3 tied low.
*“Cursor”=all dots in a single character space lit to half brightness
X=don't care
B=depends on the selected brightness
Attributes are non-destructive. If a character with bit D7 set is
replaced by a cursor (Control Word bit D4 is set, and D3=D2=0)
the character will remain in memory and can be revealed again
by clearing D4 in the Control Word.
Blink (D5): The entire display can be caused to blink at a rate of
approximately 2.0 Hz by setting bit D5 in the Control Word. This
blinking is independent of the state of D7 in all character locations.
Voltage Transients
To synchronize the blink rate in a bank of these devices, it is
necessary to tie all devices' clocks and resets together as
described in a later section of this data sheet.
It has become common practice to provide 0.01 µF bypass
capacitors liberally in digital systems. Like other CMOS cir-
cuitry, the Intelligent Display controller chip has very low power
consumption and the usual 0.01 µF would be adequate were it
not for the LEDs. To prevent power supply transients, capaci-
tors with low inductance and high capacitance at high frequen-
cies are required. This suggests a solid tantalum or ceramic
disc for high frequency bypass. For larger displays, distribute
the bypass capacitors evenly, keeping capacitors as close to
the power pins as possible. We recommend a 10 µF and
0.01 µF for every Intelligent Display to decouple the displays
themselves, at the display.
D7 D6 D5 D4 D3 D2 D1 D0 Operation
0
0
1
X
X
X
B
B
Blinking display
Lamp Test (D6): When the Lamp Test bit is set, all dots in the
entire display are lit at half brightness. When this bit is cleared,
the display returns to the characters that were showing before
the lamp test.
Figure 6. Cascading the Display
10µF
.01µF
V
CC
10µF
.01µF
V
CC
.01µF
V
CC
.01µF
V
CC
20
20
20
20
CE1
CE1
CE1
CE1
10
10
10
10
H
L
L
L
RESET
D0-D7
A0-A2
WR
RD
V
CC
V
CC
6
16
12
74LS138
13
14
15
A3
A4
A5
1
2
3
4
8
5
2001 OSRAM Opto Semiconductors Inc.• San Jose, CA
www.infineon.com/opto • 408-456-4000
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
IPD2545A/7A/8A
July 5, 2001-14
7
How to Load Information into the IPD25545/7/8A
Initiate Four Character Blinking
Information loaded into the IPD2545/7/8A can be either ASCII
data or Control Word data. The following procedure (see also
Typical Loading Sequence) will demonstrate a typical loading
sequence and the resulting visual display. The word STOP is
used in all of the following examples.
(Regardless of Control Bit setting)
Step 10 Load enable display blinking. The display now
should show the entire word “STOP” blinking.
Electrical and Mechanical Considerations
Set Brightness
The CMOS IC of the IPD2545/7/8A are designed to provide
resistance to both Electrostatic and Discharge Damage and
Latch Up due to voltage or current surges. Several precautions
are strongly recommended for the user, to avoid overstressing
these built-in safeguards.
Step 1
Set the brightness level of the entire display to your
preference (example: 100%).
Load Four Characters
Step 2
Step 3
Step 4
Step 5
Load a “S” in the left hand digit.
Load a “T” in the next digit.
Load an “O” in the next digit.
ESD Protection
Users of the IPD2545/7/8A should be careful to handle the
devices consistent with standard ESD protection procedures.
Operators should wear appropriate wrist, ankle or feet ground
straps and avoid clothing that collects static charges. Work sur-
faces, tools and transport carriers that come into contact with
unshielded devices or assemblies also should be appropriately
grounded.
Load a “P” in the right hand digit. If you loaded the
information correctly, the IPD2545A now should
show the word “STOP.”
Blink a Single Character
Step 6
Into the digit, second from the right, load the hex
code “CF,” which is the code for an “O” with the
D7 bit added as a control bit.
Latch up Protection
Latch up is condition that occurs in CMOS ICs after the input
protection diodes have been broken down. These diodes can
be reversed through several means.
Note:
The “O” is the only digit which has the control bit (D7)
added to normal ASCII data.
V <GND, V >V +0.5 V, or through excessive currents begin
forced on the inputs. When these situations exist, the IC may
develop the response of an SCR and begin conducting as much
IN
IN
CC
Step 7
Step 8
Load enable blinking character into the control word
register. The display now should show “STOP”
with a flashing “O”.
as one amp through the V pin. This destructive condition will
CC
Add Another Blinking Character
persist (latched) until device failure or the device is turned off.
Into the left hand digit, load the hex code “D3”
which gives an “S” with the D7 bit added as a
control bit. The display should show “STOP” with
flashing “O” and a flashing “S.”
The Voltage Transient Suppression Techniques and buffer inter-
faces for longer cable runs help considerably to prevent latch
conditions from occurring. Additionally, the following Power Up
and Power Down sequence should be observed.
Alternate Character/Cursor Enable
Step 9
Load enable alternate character/cursor into the
control word register. The display now should show
“STOP” with the “O” and the “S” alternating
between the letter and cursor (all dots lit).
Typical Loading Sequence
CEO CE1 RD
WR A2
A1
X
A0
X
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
1
D0
1
Display
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
L
H
H
L
H
L
0
1
0
1
0
0
1
1
S
0
1
0
1
0
1
0
0
ST
H
L
0
1
0
0
1
1
1
1
STO
L
0
1
0
1
0
0
0
0
STOP
STOP
STO*P
S*TO*P
S†TO†P
S*T*O*P*
L
H
X
1
1
0
0
1
1
1
1
X
0
0
0
1
0
1
1
1
H
L
H
X
H
X
1
1
0
1
0
0
1
1
0
0
0
1
1
1
1
1
L
X
X
0
0
1
0
0
0
1
1
* Blinking character, † Character alternating with cursor (all dots lit)
2001 OSRAM Opto Semiconductors Inc.• San Jose, CA
www.infineon.com/opto • 408-456-4000
IPD2545A/7A/8A
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
8
July 5, 2001-14
Power up Sequence
1. Float all active signals by tri-stating the inputs to the
displays.
2. Apply V and GND to the display.
CC
3. Apply active signals to the displays by enabling all input
signals per applications.
Power Down Sequence
1. Float all active signals by tri-stating the inputs to the
displays.
2. Turn off the power to the display.
Figure 7. Character Set
D0
D1
D2
D3
0
0
0
0
0
1
0
0
0
1
0
1
0
0
2
1
1
0
0
3
0
0
1
0
4
1
0
1
0
5
0
1
1
0
6
1
1
1
0
7
0
0
0
1
8
1
0
0
1
9
0
1
0
1
A
1
1
0
1
B
0
0
1
1
C
1
0
1
1
D
0
1
1
1
E
1
1
1
1
F
ASCII
CODE
D6 D5 D4 HEX
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
Notes:
1. High=1 level
2. Low=0 level
3. Upon power up, the device will initialize in a random state.
4. A2 must be held high for ASCII data.
5. Bit D7=1 enables attributes for the assigned digit.
2001 OSRAM Opto Semiconductors Inc.• San Jose, CA
www.infineon.com/opto • 408-456-4000
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
IPD2545A/7A/8A
July 5, 2001-14
9
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