IPD50N08S413ATMA1 [INFINEON]

Power Field-Effect Transistor, 50A I(D), 80V, 0.0132ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252, TO252-3-313, 3/2 PIN;
IPD50N08S413ATMA1
型号: IPD50N08S413ATMA1
厂家: Infineon    Infineon
描述:

Power Field-Effect Transistor, 50A I(D), 80V, 0.0132ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252, TO252-3-313, 3/2 PIN

脉冲 晶体管
文件: 总9页 (文件大小:271K)
中文:  中文翻译
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IPD50N08S4-13  
OptiMOS-T2 Power-Transistor  
Product Summary  
VDS  
80  
13.2  
50  
V
RDS(on),max  
ID  
mW  
A
Features  
PG-TO252-3-313  
• N-channel - Enhancement mode  
• AEC Q101 qualified  
• MSL1 up to 260°C peak reflow  
• 175°C operating temperature  
• Green Product (RoHS compliant)  
• 100% Avalanche tested  
Type  
Package  
Marking  
IPD50N08S4-13  
PG-TO252-3-313 4N0813  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
50  
Parameter  
Symbol  
Conditions  
Unit  
Continuous drain current1)  
I D  
T C=25°C, V GS=10V  
A
T C=100°C, V GS=10V2)  
50  
Pulsed drain current2)  
I D,pulse  
E AS  
T C=25°C  
200  
Avalanche energy, single pulse2)  
Avalanche current, single pulse  
Gate source voltage  
I D=25A  
76  
31  
mJ  
A
I AS  
-
V GS  
-
±20  
V
P tot  
T C=25°C  
Power dissipation  
72  
W
°C  
T j, T stg  
Operating and storage temperature  
-
-55 ... +175  
Rev. 1.0  
page 1  
2014-06-30  
IPD50N08S4-13  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Thermal characteristics2)  
R thJC  
R thJA  
Thermal resistance, junction - case  
SMD version, device on PCB  
-
-
-
-
-
-
-
2.1  
62  
40  
K/W  
minimal footprint  
6 cm2 cooling area3)  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V (BR)DSS V GS=0V, I D= 1mA  
V GS(th) V DS=V GS, I D=33µA  
Drain-source breakdown voltage  
Gate threshold voltage  
80  
-
-
V
2.0  
3.0  
4.0  
V DS=80V, V GS=0V,  
T j=25°C  
I DSS  
Zero gate voltage drain current  
-
-
0.01  
5
1
µA  
V DS=80V, V GS=0V,  
T j=125°C2)  
100  
I GSS  
V GS=20V, V DS=0V  
Gate-source leakage current  
-
-
-
100 nA  
R DS(on) V GS=10V, I D=50A  
Drain-source on-state resistance  
11.2  
13.2  
mW  
Rev. 1.0  
page 2  
2014-06-30  
IPD50N08S4-13  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Dynamic characteristics2)  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
C iss  
C oss  
Crss  
t d(on)  
t r  
-
-
-
-
-
-
-
1316  
511  
29  
1711 pF  
664  
V GS=0V, V DS=25V,  
f =1MHz  
58  
5.0  
-
-
-
-
ns  
3.6  
V DD=40V, V GS=10V,  
I D=50A, R G=3.5W  
t d(off)  
t f  
Turn-off delay time  
Fall time  
6.4  
11.8  
Gate Charge Characteristics2)  
Gate to source charge  
Gate to drain charge  
Gate charge total  
Q gs  
-
-
-
-
6.9  
4.5  
19  
9.0  
9
nC  
Q gd  
V DD=64V, I D=50A,  
V GS=0 to 10V  
Q g  
30  
-
V plateau  
Gate plateau voltage  
5.0  
V
A
Reverse Diode  
Diode continous forward current2)  
Diode pulse current1)  
I S  
-
-
-
-
50  
T C=25°C  
I S,pulse  
200  
V GS=0V, I F=50A,  
T j=25°C  
V SD  
Diode forward voltage  
Reverse recovery time1)  
Reverse recovery charge1)  
-
-
-
0.9  
74  
49  
1.3  
V
V R=50V, I F=I S,  
di F/dt =100A/µs  
t rr  
-
-
ns  
nC  
Q rr  
1) Current is limited by bondwire; with an R thJC = 2.1K/W the chip is able to carry 85A at 25°C.  
2) Specified by design. Not subject to production test.  
3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
Rev. 1.0  
page 3  
2014-06-30  
IPD50N08S4-13  
1 Power dissipation  
2 Drain current  
P tot = f(T C); V GS ≥ 6 V  
I D = f(T C); V GS = 10 V  
80  
70  
60  
50  
40  
30  
20  
10  
0
60  
50  
40  
30  
20  
10  
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
TC [°C]  
TC [°C]  
3 Safe operating area  
4 Max. transient thermal impedance  
Z thJC = f(t p)  
I D = f(V DS); T C = 25 °C; D = 0  
parameter: t p  
parameter: D =t p/T  
101  
1000  
100  
10  
1 µs  
100  
0.5  
10 µs  
100 µs  
1 ms  
0.1  
0.05  
10-1  
0.01  
single pulse  
10-2  
1
0.1  
1
10  
100  
VDS [V]  
tp [s]  
Rev. 1.0  
page 4  
2014-06-30  
IPD50N08S4-13  
5 Typ. output characteristics  
I D = f(V DS); T j = 25 °C  
parameter: V GS  
6 Typ. drain-source on-state resistance  
R DS(on) = f(I D); T j = 25 °C  
parameter: V GS  
200  
30  
5 V  
5.5 V  
180  
10 V  
160  
140  
120  
100  
80  
25  
20  
15  
7V  
6 V  
6 V  
7 V  
60  
5.5 V  
5 V  
40  
20  
10 V  
0
10  
0
0
2
4
6
20  
40  
VDS [V]  
ID [A]  
7 Typ. transfer characteristics  
I D = f(V GS); V DS = 6V  
parameter: T j  
8 Typ. drain-source on-state resistance  
R DS(on) = f(T j); I D = 50 A; V GS = 10 V  
200  
180  
160  
140  
120  
100  
80  
22  
18  
14  
10  
6
-55 °C  
25 °C  
175 °C  
60  
40  
20  
0
2.5  
4.5  
6.5  
-60  
-20  
20  
60  
100  
140  
180  
VGS [V]  
Tj [°C]  
Rev. 1.0  
page 5  
2014-06-30  
IPD50N08S4-13  
9 Typ. gate threshold voltage  
V GS(th) = f(T j); V GS = V DS  
parameter: I D  
10 Typ. capacitances  
C = f(V DS); V GS = 0 V; f = 1 MHz  
104  
3.5  
3.25  
3
Ciss  
103  
330 µA  
Coss  
2.75  
33 µA  
102  
2.5  
Crss  
2.25  
2
1.75  
1.5  
101  
0
20  
40  
VDS [V]  
60  
80  
-60  
-20  
20  
60  
100  
140  
180  
Tj [°C]  
11 Typical forward diode characteristicis  
12 Avalanche characteristics  
I A S= f(t AV  
IF = f(VSD)  
)
parameter: T j  
parameter: Tj(start)  
103  
100  
102  
25 °C  
100 °C  
150 °C  
10  
175 °C  
101  
25 °C  
100  
1
1
0
0.4  
0.8  
1.2  
1.6  
2
10  
100  
1000  
VSD [V]  
tAV [µs]  
Rev. 1.0  
page 6  
2014-06-30  
IPD50N08S4-13  
13 Avalanche energy  
14 Drain-source breakdown voltage  
E AS = f(T j); I D = 15 A  
V BR(DSS) = f(T j); I D = 1 mA  
90  
88  
86  
84  
82  
80  
78  
76  
74  
72  
70  
400  
350  
300  
7.5 A  
250  
200  
150  
15 A  
100  
31 A  
50  
0
-55  
-15  
25  
65  
105  
145  
185  
25  
75  
125  
175  
Tj [°C]  
Tj [°C]  
15 Typ. gate charge  
16 Gate charge waveforms  
V GS = f(Q gate); I D = 50 A pulsed  
parameter: V DD  
10  
9
8
7
6
5
4
3
2
1
0
V GS  
Q g  
16 V  
64 V  
V gs(th)  
Q g(th)  
Q sw  
Q gd  
Q gate  
Q gs  
0
3
6
9
12  
15  
18  
Qgate [nC]  
Rev. 1.0  
page 7  
2014-06-30  
IPD50N08S4-13  
Published by  
Infineon Technologies AG  
81726 Munich, Germany  
© Infineon Technologies AG 2014  
All Rights Reserved.  
Legal Disclaimer  
The information given in this document shall in no event be regarded as a guarantee of conditions  
or characteristics. With respect to any examples or hints given herein, any typical values stated  
herein and/or any information regarding the application of the device, Infineon Technologies hereby  
disclaims any and all warranties and liabilities of any kind, including without limitation, warranties  
of non-infringement of intellectual property rights of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices, please contact  
the nearest Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements, components may contain dangerous substances.  
For information on the types in question, please contact the nearest Infineon Technologies Office.  
Infineon Technologies components may be used in life-support devices or systems only with the  
express written approval of Infineon Technologies, if a failure of such components can reasonably be  
expected to cause the failure of that life-support device or system or to affect the safety or  
effectiveness of that device or system. Life support devices or systems are intended to be implanted  
in the human body or to support and/or maintain and sustain and/or protect human life.  
If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.  
Rev. 1.0  
page 8  
2014-06-30  
IPD50N08S4-13  
Revision History  
Version  
Date  
Changes  
Revision 1.0  
30.06.2014 Final data sheet  
Rev. 1.0  
page 9  
2014-06-30  

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