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IPD90P03P4L-04 [INFINEON]

OptiMOS-P2 Power-Transistor; 的OptiMOS -P2功率三极管
IPD90P03P4L-04
型号： IPD90P03P4L-04
厂家： Infineon    Infineon
描述：

OptiMOS-P2 Power-Transistor
的OptiMOS -P2功率三极管
文件： 总9页 (文件大小：166K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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IPD90P03P4L-04  
OptiMOS®-P2 Power-Transistor  
Product Summary  
VDS  
R DS(on)  
I D  
-30  
4.1  
-90  
V
mΩ  
A
Features  
• P-channel - Logic Level - Enhancement mode  
• AEC qualified  
PG-TO252-3-11  
• MSL1 up to 260°C peak reflow  
• 175°C operating temperature  
• Green package (RoHS compliant)  
• 100% Avalanche tested  
• Intended for reverse battery protection  
Type  
Package  
Marking  
IPD90P03P4L-04  
PG-TO252-3-11 4P03L04  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol  
Conditions  
Unit  
T C=25°C,  
GS=-10V  
Continuous drain current1)  
I D  
-90  
-90  
A
V
T C=100°C,  
GS=-10V2)  
V
Pulsed drain current2)  
I D,pulse  
EAS  
I AS  
T C=25°C  
-360  
370  
I D=-45A  
Avalanche energy, single pulse  
Avalanche current, single pulse  
Gate source voltage  
mJ  
A
-
-90  
VGS  
Ptot  
-
+5/-16  
137  
V
T C=25 °C  
Power dissipation  
W
°C  
T j, T stg  
-
Operating and storage temperature  
IEC climatic category; DIN IEC 68-1  
-
-
-55 ... +175  
55/175/56  
Rev. 1.0  
page 1  
2008-07-30  
IPD90P03P4L-04  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Thermal characteristics2)  
R thJC  
R thJA  
Thermal resistance, junction - case  
SMD version, device on PCB  
-
-
-
-
-
-
-
1.1  
62  
40  
K/W  
minimal footprint  
6 cm2 cooling area3)  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V(BR)DSS  
VGS(th)  
V
V
GS=0V, I D= -1mA  
Drain-source breakdown voltage  
Gate threshold voltage  
-30  
-
-
V
DS=VGS, I D=-253µA  
-1.0  
-1.5  
-2.0  
V
DS=-24V, VGS=0V,  
I DSS  
Zero gate voltage drain current  
-
-
-0.05  
-20  
-1  
µA  
T j=25°C  
V
DS=-24V, VGS=0V,  
-200  
T j=125°C2)  
I GSS  
V
V
V
GS=-16V, VDS=0V  
GS=-4.5V, I D=-90A  
GS=-10V, I D=-90A  
Gate-source leakage current  
-
-
-
-
-100 nA  
R DS(on)  
Drain-source on-state resistance  
5.1  
3.3  
6.8  
4.1  
mΩ  
Rev. 1.0  
page 2  
2008-07-30  
IPD90P03P4L-04  
Values  
Parameter  
Symbol  
Conditions  
Unit  
min.  
typ.  
max.  
Dynamic characteristics2)  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
C iss  
C oss  
Crss  
t d(on)  
t r  
-
-
-
-
-
-
-
8670  
2350  
65  
11300 pF  
3050  
V
GS=0V, VDS=-25V,  
f =1MHz  
130  
17  
-
-
-
-
ns  
V
V
DD=-15V,  
GS=-10V, I D=-90A,  
11  
t d(off)  
t f  
Turn-off delay time  
Fall time  
140  
40  
R G=3.5Ω  
Gate Charge Characteristics2)  
Gate to source charge  
Gate to drain charge  
Gate charge total  
Q gs  
-
-
-
-
29  
15  
38  
30  
160  
-
nC  
Q gd  
V
V
DD=-24V, I D=-90A,  
GS=0 to -10V  
Q g  
125  
-3.3  
Vplateau  
Gate plateau voltage  
V
A
Reverse Diode  
Diode continous forward current2)  
Diode pulse current2)  
I S  
-
-
-
-
-90  
T C=25°C  
I S,pulse  
-360  
V
GS=0V, I F=-90A,  
VSD  
Diode forward voltage  
-
-
-1.3  
V
T j=25°C  
Reverse recovery time2)  
Reverse recovery charge2)  
t rr  
-
-
50  
70  
-
-
ns  
VR=-15V, I F=-50A,  
diF/dt =-100A/µs  
Q rr  
nC  
1) Current is limited by bondwire; with an R thJC = 1.1K/W the chip is able to carry -150A at 25°C.  
2) Defined by design. Not subject to production test.  
3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
Rev. 1.0  
page 3  
2008-07-30  
IPD90P03P4L-04  
1 Power dissipation  
2 Drain current  
P
tot = f(T C); VGS ≤ -6V  
I D = f(T C); VGS ≤ -6V  
160  
140  
120  
100  
80  
100  
80  
60  
40  
20  
0
60  
40  
20  
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
T
C [°C]  
T
C [°C]  
3 Safe operating area  
4 Max. transient thermal impedance  
thJC = f(t p)  
I D = f(VDS); T C = 25 °C; D = 0  
parameter: t p  
Z
parameter: D =t p/T  
101  
1000  
100  
10  
1 µs  
10 µs  
100  
100 µs  
1 ms  
0.5  
0.1  
10-1  
0.05  
0.01  
10-2  
single pulse  
10-3  
1
10-6  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
0.1  
1
10  
100  
t p [s]  
-V DS [V]  
Rev. 1.0  
page 4  
2008-07-30  
IPD90P03P4L-04  
5 Typ. output characteristics  
I D = f(VDS); T j = 25 °C  
parameter: VGS  
6 Typ. drain-source on-state resistance  
DS(on) = (I D); T j = 25 °C  
R
parameter: VGS  
18  
360  
10V  
5V  
-4V  
4.5V  
-4.5V  
15  
12  
9
270  
180  
90  
4V  
6
3.5V  
3V  
-5V  
-10V  
3
0
0
0
90  
180  
-I D [A]  
270  
360  
0
1
2
3
4
5
6
-V DS [V]  
7 Typ. transfer characteristics  
I D = f(VGS); VDS = -6V  
parameter: T j  
8 Typ. drain-source on-state resistance  
R
DS(on) = f(T j); I D = -90 A; VGS = -10 V  
320  
6
25 °C  
-55 °C  
175 °C  
5
4
3
2
240  
160  
80  
0
-60  
-20  
20  
60  
T j [°C]  
100  
140  
180  
1
2
3
4
5
6
-V GS [V]  
Rev. 1.0  
page 5  
2008-07-30  
IPD90P03P4L-04  
9 Typ. gate threshold voltage  
GS(th) = f(T j); VGS = VDS  
10 Typ. capacitances  
V
C = f(VDS); VGS = 0 V; f = 1 MHz  
parameter: -I D  
105  
104  
103  
102  
101  
2
2530µA  
1.5  
1
Ciss  
253µA  
Coss  
0.5  
Crss  
0
0
5
10  
15  
20  
25  
30  
-60  
-20  
20  
60  
T j [°C]  
100  
140  
180  
-V DS [V]  
11 Typical forward diode characteristicis  
12 Avalanche characteristics  
AS = f(t AV  
IF = f(VSD)  
I
)
parameter: T j  
parameter: Tj(start)  
103  
100  
25 °C  
100 °C  
150 °C  
102  
10  
25 °C  
175 °C  
101  
100  
1
1
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
10  
100  
1000  
-V SD [V]  
t
AV [µs]  
Rev. 1.0  
page 6  
2008-07-30  
IPD90P03P4L-04  
13 Avalanche energy  
AS = f(T j)  
14 Drain-source breakdown voltage  
E
V
BR(DSS) = f(T j); I D = -1 mA  
parameter: I D  
33  
800  
22.5 A  
32  
31  
30  
29  
28  
600  
400  
45 A  
200  
90 A  
0
-60  
-20  
20  
60  
100  
140  
180  
25  
75  
125  
175  
T j [°C]  
T j [°C]  
15 Typ. gate charge  
16 Gate charge waveforms  
V
GS = f(Q gate); I D = -90 A pulsed  
parameter: VDD  
12  
VGS  
10  
8
Qg  
-6V  
-24V  
6
4
Qgate  
2
Qgd  
Qgs  
0
0
20  
40  
60  
80  
100  
120  
140  
Q
gate [nC]  
Rev. 1.0  
page 7  
2008-07-30  
IPD90P03P4L-04  
Published by  
Infineon Technologies AG  
81726 Munich, Germany  
© Infineon Technologies AG 2008  
All Rights Reserved.  
Legal Disclaimer  
The information given in this document shall in no event be regarded as a guarantee of conditions  
or characteristics. With respect to any examples or hints given herein, any typical values stated  
herein and/or any information regarding the application of the device, Infineon Technologies hereby  
disclaims any and all warranties and liabilities of any kind, including without limitation, warranties  
of non-infringement of intellectual property rights of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices, please contact  
the nearest Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements, components may contain dangerous substances.  
For information on the types in question, please contact the nearest Infineon Technologies Office.  
Infineon Technologies components may be used in life-support devices or systems only with the  
express written approval of Infineon Technologies, if a failure of such components can reasonably be  
expected to cause the failure of that life-support device or system or to affect the safety or  
effectiveness of that device or system. Life support devices or systems are intended to be implanted  
in the human body or to support and/or maintain and sustain and/or protect human life.  
If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.  
Rev. 1.0  
page 8  
2008-07-30  
IPD90P03P4L-04  
Revision History  
Version  
Date  
Changes  
Rev. 1.0  
page 9  
2008-07-30  

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