IPD90P04P405ATMA2 [INFINEON]

Power Field-Effect Transistor,;


型号：	IPD90P04P405ATMA2
厂家：	Infineon
描述：	Power Field-Effect Transistor,
文件：	总9页 (文件大小：415K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IPD90P04P4-05

OptiMOS^®-P2 Power-Transistor

Product Summary

V_DS

R_DS(on)

I_D

-40

4.7

-90

Features

• P-channel - Normal Level - Enhancement mode

• AEC qualified

PG-TO252-3-313

Tab

• MSL1 up to 260°C peak reflow

• 175°C operating temperature

• Green package (RoHS compliant)

• 100% Avalanche tested

Source

pin 3

Gate

pin 1

Type

Package

Marking

Drain

pin 2/Tab

IPD90P04P4-05

PG-TO252-3-313 4P0405

Maximum ratings, at T _j=25 °C, unless otherwise specified

Value

Parameter

Symbol

Conditions

Unit

T _C=25°C,

V_GS=-10V

Continuous drain current¹⁾

I _D

-90

T _C=100°C,

V_GS=-10V²⁾

-90

Pulsed drain current²⁾

I _D,pulse

E_AS

I _AS

T _C=25°C

-360

I _D=-45A

Avalanche energy, single pulse

Avalanche current, single pulse

Gate source voltage

-90

±20

125

V_GS

P_tot

T _C=25 °C

Power dissipation

°C

T _j, T _stg

Operating and storage temperature

IEC climatic category; DIN IEC 68-1

-55 ... +175

55/175/56

Rev. 1.2

page 1

2019-04-23

IPD90P04P4-05

Values

Parameter

Symbol

Conditions

Unit

min.

typ.

max.

Thermal characteristics²⁾

R _thJC

R _thJA

Thermal resistance, junction - case

SMD version, device on PCB

1.2

K/W

minimal footprint

6 cm²cooling area³⁾

Electrical characteristics, at T _j=25 °C, unless otherwise specified

Static characteristics

V_(BR)DSSV_GS=0V, I _D= -1mA

V_GS(th)V_DS=V_GS, I _D=-250µA

Drain-source breakdown voltage

Gate threshold voltage

-40

-2.0

-3.0

-4.0

V_DS=-32V, V_GS=0V,

T _j=25°C

I _DSS

Zero gate voltage drain current

-0.05

-20

-1

µA

V_DS=-32V, V_GS=0V,

T _j=125°C²⁾

-200

I _GSS

V_GS=-20V, V_DS=0V

Gate-source leakage current

-100 nA

R _DS(on)V_GS=-10V, I _D=-90A

Drain-source on-state resistance

3.5

4.7

Rev. 1.2

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2019-04-23

IPD90P04P4-05

Values

Parameter

Symbol

Conditions

Unit

min.

typ.

max.

Dynamic characteristics²⁾

Input capacitance

Output capacitance

Reverse transfer capacitance

Turn-on delay time

Rise time

C _iss

C _oss

C_rss

t _d(on)

t _r

7900

2800

10300 pF

3600

V_GS=0V, V_DS=-25V,

f =1MHz

150

V_DD=-20V,

V_GS=-10V, I _D=-90A,

R _G=3.5W

t _d(off)

t _f

Turn-off delay time

Fall time

Gate Charge Characteristics²⁾

Gate to source charge

Gate to drain charge

Gate charge total

Q _gs

154

Q _gd

V_DD=-32V, I _D=-90A,

V_GS=0 to -10V

Q _g

118

-5.3

V_plateau

Gate plateau voltage

Reverse Diode

Diode continous forward current²⁾

Diode pulse current²⁾

I _S

-90

T _C=25°C

I _S,pulse

-360

V_GS=0V, I _F=-90A,

T _j=25°C

V_SD

Diode forward voltage

-1

-1.3

Reverse recovery time²⁾

t _rr

V_R=-20V, I _F=-50A,

di_F/dt =-100A/µs

Reverse recovery charge²⁾

Q _rr

¹⁾Current is limited by bondwire; with an R _thJC= 1.2K/W the chip is able to carry -138A at 25°C.

²⁾Defined by design. Not subject to production test.

³⁾Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm²(one layer, 70 µm thick) copper area for drain

connection. PCB is vertical in still air.

Rev. 1.2

page 3

2019-04-23

IPD90P04P4-05

1 Power dissipation

2 Drain current

P_tot= f(T _C); V_GS≤ -6V

I _D= f(T _C); V_GS≤ -6V

140

120

100

150

200

100

150

200

T_C[°C]

3 Safe operating area

4 Max. transient thermal impedance

Z _thJC= f(t _p)

I _D= f(V_DS); T _C= 25 °C; D = 0

parameter: t _p

parameter: D =t _p/T

10¹

1000

100

1 µs

10 µs

10⁰

0.5

100 µs

1 ms

0.1

10^-1

0.05

0.01

10^-2

single pulse

10^-3

0.1

100

10^-6

10^-5

10^-4

10^-3

10^-2

10^-1

10⁰

-V_DS[V]

t_p[s]

Rev. 1.2

page 4

2019-04-23

IPD90P04P4-05

5 Typ. output characteristics

I _D= f(V_DS); T _j= 25 °C

parameter: V_GS

6 Typ. drain-source on-state resistance

R _DS(on)= (I _D); T _j= 25 °C

parameter: V_GS

360

-8V

-10V

-7V

-5V

270

180

-6V

-7V

-5V

-8V

-10V

-I_D[A]

-V_DS[V]

7 Typ. transfer characteristics

I _D= f(V_GS); V_DS= -6V

parameter: T _j

8 Typ. drain-source on-state resistance

R _DS(on)= f(T _j); I _D= -90 A; V _GS= -10 V

360

270

180

175 °C

-55 °C

25 °C

-60

-20

100

140

180

T_j[°C]

-V_GS[V]

Rev. 1.2

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2019-04-23

IPD90P04P4-05

9 Typ. gate threshold voltage

V_GS(th)= f(T _j); V_GS= V_DS

parameter: -I _D

10 Typ. capacitances

C = f(V_DS); V_GS= 0 V; f = 1 MHz

10⁵

10⁴

10³

10²

10¹

3.5

Ciss

Coss

2500µA

250µA

2.5

Crss

1.5

-60

-20

100

140

180

T_j[°C]

-V_DS[V]

11 Typical forward diode characteristicis

12 Drain-source breakdown voltage

V_BR(DSS)= f(Tj); I_D= -1 mA

parameter: T_j(start)

I_F= f(V_SD)

parameter: T _j

10³

10²

175 °C

25 °C

10¹

10⁰

0.2

0.4

0.6

0.8

1.2

1.4

-60

-20

100

140

180

-V_SD[V]

T_j[°C]

Rev. 1.2

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2019-04-23

IPD90P04P4-05

13 Typ. gate charge

14 Gate charge waveforms

V_GS= f(Q _gate); I _D= -90 A pulsed

parameter: V_DD

V_GS

Q_g

-8V

-32V

Q_gate

Q_gd

Q_gs

100

120

Q_gate[nC]

Rev. 1.2

page 7

2019-04-23

IPD90P04P4-05

Published by

Infineon Technologies AG

81726 Munich, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions

or characteristics. With respect to any examples or hints given herein, any typical values stated

herein and/or any information regarding the application of the device, Infineon Technologies hereby

disclaims any and all warranties and liabilities of any kind, including without limitation, warranties

of non-infringement of intellectual property rights of any third party.

Information

For further information on technology, delivery terms and conditions and prices, please contact

the nearest Infineon Technologies Office (www.infineon.com).

Warnings

Due to technical requirements, components may contain dangerous substances.

For information on the types in question, please contact the nearest Infineon Technologies Office.

Infineon Technologies components may be used in life-support devices or systems only with the

express written approval of Infineon Technologies, if a failure of such components can reasonably be

expected to cause the failure of that life-support device or system or to affect the safety or

effectiveness of that device or system. Life support devices or systems are intended to be implanted

in the human body or to support and/or maintain and sustain and/or protect human life.

If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

Rev. 1.2

page 8

2019-04-23

IPD90P04P4-05

Revision History

Version

Date

Changes

Revision 1.0

21.05.2010 Final Data Sheet

Diagramme 6 scaling

14.03.2011 Switching times

Revision 1.1

Revision 1.2

23.04.2019 Q_GSchanged

Rev. 1.2

page 9

2019-04-23

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