IPF09N03LA [INFINEON]

OptiMOS 2 Power-Transistor; 的OptiMOS 2功率三极管
IPF09N03LA
型号: IPF09N03LA
厂家: Infineon    Infineon
描述:

OptiMOS 2 Power-Transistor
的OptiMOS 2功率三极管

文件: 总9页 (文件大小:224K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
IPF09N03LA  
OptiMOS®2 Power-Transistor  
Product Summary  
Features  
V DS  
25  
8.9  
50  
V
• Ideal for high-frequency dc/dc converters  
• N-channel  
R DS(on),max  
I D  
m  
A
• Logic level  
• Excellent gate charge x R DS(on) product (FOM)  
• Very low on-resistance R DS(on)  
P-TO252-3-23  
• Superior thermal resistance  
• 175 °C operating temperature  
• dv /dt rated  
Type  
Package  
Ordering Code Marking  
Q67042-S4199 09N03LA  
IPF09N03LA  
P-TO252-3-23  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol Conditions  
Unit  
T C=25 °C1)  
I D  
Continuous drain current  
50  
46  
A
T C=100 °C  
T C=25 °C2)  
I D,pulse  
Pulsed drain current  
350  
75  
E AS  
I D=45 A, R GS=25 Ω  
Avalanche energy, single pulse  
mJ  
I D=50 A, V DS=20 V,  
di /dt =200 A/µs,  
Reverse diode dv /dt  
dv /dt  
6
kV/µs  
T
j,max=175 °C  
Gate source voltage3)  
V GS  
±20  
63  
V
P tot  
T C=25 °C  
Power dissipation  
W
°C  
T j, T stg  
Operating and storage temperature  
IEC climatic category; DIN IEC 68-1  
-55 ... 175  
55/175/56  
Rev. 1.2  
page 1  
2003-12-19  
IPF09N03LA  
Values  
typ.  
Parameter  
Symbol Conditions  
Unit  
min.  
max.  
Thermal characteristics  
R thJC  
Thermal resistance, junction - case  
SMD version, device on PCB  
-
-
-
-
-
-
2.4  
75  
50  
K/W  
R thJA  
minimal footprint  
6 cm2 cooling area4)  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V (BR)DSS V GS=0 V, I D=1 mA  
V GS(th) V DS=V GS, I D=20 µA  
Drain-source breakdown voltage  
Gate threshold voltage  
25  
-
-
V
1.2  
1.6  
2
V DS=25 V, V GS=0 V,  
T j=25 °C  
I DSS  
Zero gate voltage drain current  
-
0.1  
1
µA  
V
DS=25 V, V GS=0 V,  
-
-
-
10  
10  
100  
T j=125 °C  
I GSS  
V GS=20 V, V DS=0 V  
Gate-source leakage current  
100 nA  
R DS(on) V GS=4.5 V, I D=30 A  
Drain-source on-state resistance  
12.1  
15.1  
mΩ  
V
GS=10 V, I D=30 A  
-
-
7.5  
1
8.9  
-
R G  
g fs  
Gate resistance  
|V DS|>2|I D|R DS(on)max  
I D=30 A  
,
Transconductance  
21  
42  
-
S
1) Current is limited by bondwire; with an R thJC=2.4 K/W the chip is able to carry 65 A.  
2) See figure 3  
3)  
T
=150 °C and duty cycle D <0.25 for V GS<-5 V  
j,max  
4) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
Rev. 1.2  
page 2  
2003-12-19  
IPF09N03LA  
Values  
typ.  
Parameter  
Symbol Conditions  
Unit  
min.  
max.  
Dynamic characteristics  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
C iss  
-
-
-
-
-
-
-
1240  
530  
81  
1649 pF  
704  
V
GS=0 V, V DS=15 V,  
C oss  
Crss  
t d(on)  
t r  
f =1 MHz  
122  
8.7  
8.5  
22  
13  
14  
33  
6.2  
ns  
V
DD=15 V, V GS=10 V,  
I D=25 A, R G=2.7 Ω  
t d(off)  
t f  
Turn-off delay time  
Fall time  
4.2  
Gate Charge Characteristics5)  
Gate to source charge  
Gate charge at threshold  
Gate to drain charge  
Switching charge  
Q gs  
-
-
-
-
-
-
4
6
2.6  
4.7  
8
nC  
Q g(th)  
Q gd  
2.0  
3.1  
5
V
V
DD=15 V, I D=25 A,  
GS=0 to 5 V  
Q sw  
Q g  
Gate charge total  
10  
3.5  
14  
-
V plateau  
Gate plateau voltage  
V
V DS=0.1 V,  
GS=0 to 5 V  
Q g(sync)  
Gate charge total, sync. FET  
Output charge  
-
-
9
12  
15  
nC  
V
Q oss  
V DD=15 V, V GS=0 V  
11  
Reverse Diode  
I S  
Diode continous forward current  
Diode pulse current  
-
-
-
-
50  
A
T C=25 °C  
I S,pulse  
350  
V GS=0 V, I F=50 A,  
T j=25 °C  
V SD  
Diode forward voltage  
-
-
1.0  
-
1.2  
10  
V
V R=15 V, I F=I S,  
di F/dt =400 A/µs  
Q rr  
Reverse recovery charge  
nC  
5) See figure 16 for gate charge parameter definition  
Rev. 1.2  
page 3  
2003-12-19  
IPF09N03LA  
1 Power dissipation  
2 Drain current  
P tot=f(T C)  
I D=f(T C); V GS10 V  
70  
60  
50  
40  
30  
20  
10  
0
60  
50  
40  
30  
20  
10  
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
T C [°C]  
T C [°C]  
3 Safe operation area  
I D=f(V DS); T C=25 °C; D =0  
parameter: t p  
4 Max. transient thermal impedance  
Z thJC=f(t p)  
parameter: D =t p/T  
1000  
10  
1 µs  
limited by on-state  
resistance  
0.5  
1
10 µs  
0.2  
100  
0.1  
100 µs  
1 ms  
0.05  
0.1  
DC  
0.02  
0.01  
10  
single pulse  
0.01  
10 ms  
1
0.001  
-6  
-3  
-2  
10  
10  
10-1  
0.1  
1
10  
100  
10  
-5  
10  
-4  
10  
0
10  
V DS [V]  
t p [s]  
Rev. 1.2  
page 4  
2003-12-19  
IPF09N03LA  
5 Typ. output characteristics  
I D=f(V DS); T j=25 °C  
6 Typ. drain-source on resistance  
R DS(on)=f(I D); T j=25 °C  
parameter: V GS  
parameter: V GS  
60  
28  
4.1 V  
3.2 V  
3.5 V  
3.8 V  
10 V  
4.5 V  
24  
20  
16  
12  
8
50  
40  
30  
20  
10  
0
4.1 V  
3.8 V  
4.5 V  
3.5 V  
3.2 V  
10 V  
4
3 V  
2.8 V  
0
0
1
2
3
0
20  
40  
60  
V DS [V]  
I D [A]  
7 Typ. transfer characteristics  
I D=f(V GS); |V DS|>2|I D|R DS(on)max  
parameter: T j  
8 Typ. forward transconductance  
g fs=f(I D); T j=25 °C  
100  
90  
80  
70  
60  
50  
40  
30  
20  
60  
50  
40  
30  
20  
10  
0
175 °C  
25 °C  
10  
0
0
1
2
3
4
5
0
10  
20  
30  
40  
50  
60  
V GS [V]  
I D [A]  
Rev. 1.2  
page 5  
2003-12-19  
IPF09N03LA  
9 Drain-source on-state resistance  
10 Typ. gate threshold voltage  
V GS(th)=f(T j); V GS=V DS  
parameter: I D  
R
DS(on)=f(T j); I D=30 A; V GS=10 V  
16  
14  
12  
2.5  
2
200 µA  
98 %  
10  
1.5  
1
20 µA  
typ  
8
6
4
2
0
0.5  
0
-60  
-20  
20  
60  
100  
140  
180  
-60  
-20  
20  
60  
T j [°C]  
100  
140  
180  
T j [°C]  
11 Typ. Capacitances  
12 Forward characteristics of reverse diode  
I F=f(V SD  
C =f(V DS); V GS=0 V; f =1 MHz  
)
parameter: T j  
10000  
1000  
25 °C  
25 °C, 98 %  
175 °C, 98 %  
1000  
Ciss  
100  
Coss  
175 °C  
Crss  
100  
10  
10  
1
0
0
5
10  
15  
20  
25  
30  
0.5  
1
1.5  
2
V DS [V]  
V SD [V]  
Rev. 1.2  
page 6  
2003-12-19  
IPF09N03LA  
13 Avalanche characteristics  
14 Typ. gate charge  
V GS=f(Q gate); I D=25 A pulsed  
parameter: V DD  
I AS=f(t AV); R GS=25 Ω  
parameter: Tj(start)  
100  
12  
10  
8
15 V  
100 °C  
25 °C  
150 °C  
5 V  
20 V  
10  
6
4
2
1
0
1
10  
100  
1000  
0
5
10  
15  
20  
t AV [µs]  
Q gate [nC]  
15 Drain-source breakdown voltage  
16 Gate charge waveforms  
V
BR(DSS)=f(T j); I D=1 mA  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
V GS  
Q g  
V gs(th)  
Q g(th)  
Q sw  
Q gd  
Q gate  
Q gs  
-60  
-20  
20  
60  
100  
140  
180  
T j [°C]  
Rev. 1.2  
page 7  
2003-12-19  
IPF09N03LA  
Package Outline  
P-TO252-3-23  
Dimensions in inch [mm]  
Footprint  
Dimensions in mm  
Rev. 1.2  
page 8  
2003-12-19  
IPF09N03LA  
Published by  
Infineon Technologies AG  
Bereich Kommunikation  
St.-Martin-Straße 53  
D-81541 München  
© Infineon Technologies AG 1999  
All Rights Reserved.  
Attention please!  
The information herein is given to describe certain components and shall not be considered as  
warranted characteristics.  
Terms of delivery and rights to technical change reserved.  
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement,  
regarding circuits, descriptions and charts started herein.  
Infineon Technologies is an approved CECC manufacturer.  
Information  
For further information on technology, delivery terms and conditions and prices, please contact your  
nearest Infineon Technologies office in Germany or our Infineon Technologies representatives worldwide  
(see address list).  
Warnings  
Due to technical requirements, components may contain dangerous substances.  
For information on the types in question, please contact your nearest Infineon Technologies office.  
Infineon Technologies' components may only be used in life-support devices or systems with the  
expressed written approval of Infineon Technologies if a failure of such components can reasonably  
be expected to cause the failure of that life-support device or system, or to affect the safety or  
effectiveness of that device or system. Life support devices or systems are intended to be implanted  
in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail,  
it is reasonable to assume that the health of the user or other persons may be endangered.  
Rev. 1.2  
page 9  
2003-12-19  

相关型号:

IPF09N03LAG

OptiMOS㈢2 Power-Transistor
INFINEON

IPF09N03LBG

OptiMOS㈢2 Power-Transistor
INFINEON

IPF105N03LG

OptiMOS3 Power-Transistor
INFINEON

IPF10N03LA

OptiMOS2 Power-Transistor
INFINEON

IPF10N03LAG

OptiMOS㈢2 Power-Transistor
INFINEON

IPF12N03LBG

OptiMOS㈢2 Power-Transistor
INFINEON

IPF135N03LG

OptiMOS 3 Power-Transistor Features Optimized technology for DC/DC converters
INFINEON

IPF13N03LA

OptiMOS 2 Power-Transistor
INFINEON

IPF13N03LAG

OptiMOS㈢2 Power-Transistor
INFINEON

IPFF4

Superfast Axial Rectifier. 400 V. Io=1.7 A
ETC

IPFH6N03LAG

OptiMOS㈢2 Power-Transistor
INFINEON

IPG15N06S3L-45

OptiMOS-T Power-Transistor
INFINEON