IPI80N04S2H4AKSA2 [INFINEON]

Power Field-Effect Transistor, 80A I(D), 40V, 0.004ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-262AA, TO-262-3-1, 3 PIN;
IPI80N04S2H4AKSA2
型号: IPI80N04S2H4AKSA2
厂家: Infineon    Infineon
描述:

Power Field-Effect Transistor, 80A I(D), 40V, 0.004ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-262AA, TO-262-3-1, 3 PIN

脉冲 晶体管
文件: 总9页 (文件大小:192K)
中文:  中文翻译
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IPB80N04S2-H4  
IPP80N04S2-H4, IPI80N04S2-H4  
OptiMOS® Power-Transistor  
Product Summary  
VDS  
40  
3.7  
80  
V
R
DS(on),max (SMD version)  
m  
A
I D  
Features  
• N-channel - Enhancement mode  
PG-TO263-3-2  
PG-TO262-3-1  
PG-TO220-3-1  
• Automotive AEC Q101 qualified  
• MSL1 up to 260°C peak reflow  
• 175°C operating temperature  
• Ultra low Rds(on)  
• 100% Avalanche tested  
• Green product (RoHS compliant)  
Type  
Package  
Marking  
2N04H4  
2N04H4  
2N04H4  
IPB80N04S2-H4  
IPP80N04S2-H4  
IPI80N04S2-0H4  
PG-TO263-3-2  
PG-TO220-3-1  
PG-TO262-3-1  
Maximum ratings, at T j=25 °C, unless otherwise specified  
Value  
Parameter  
Symbol  
Conditions  
Unit  
Continuous drain current1)  
I D  
T C=25 °C, VGS=10 V  
T C=100 °C,  
80  
80  
A
V
GS=10 V2)  
Pulsed drain current2)  
I D,pulse  
EAS  
T C=25 °C  
I D=80A  
320  
660  
±20  
300  
Avalanche energy, single pulse  
Gate source voltage  
mJ  
V
VGS  
Ptot  
T C=25 °C  
Power dissipation  
W
T j, T stg  
Operating and storage temperature  
IEC climatic category; DIN IEC 68-1  
-55 ... +175  
55/175/56  
°C  
Rev. 1.1  
page 1  
2008-02-22  
IPB80N04S2-H4  
IPP80N04S2-H4, IPI80N04S2-H4  
Values  
typ.  
Parameter  
Symbol  
Conditions  
Unit  
min.  
max.  
Thermal characteristics2)  
R thJC  
R thJA  
R thJA  
Thermal resistance, junction - case  
-
-
-
-
0.5  
62  
K/W  
Thermal resistance, junction -  
ambient, leaded  
SMD version, device on PCB  
minimal footprint  
-
-
-
-
62  
40  
6 cm2 cooling area3)  
Electrical characteristics, at T j=25 °C, unless otherwise specified  
Static characteristics  
V(BR)DSS  
VGS(th)  
V
V
GS=0 V, I D= 1 mA  
Drain-source breakdown voltage  
Gate threshold voltage  
40  
-
-
V
DS=VGS, I D=250 µA  
2.1  
3.0  
4.0  
V
DS=40 V, VGS=0 V,  
I DSS  
Zero gate voltage drain current  
-
-
0.01  
1
1
µA  
T j=25 °C  
V
DS=40 V, VGS=0 V,  
100  
T j=125 °C2)  
I GSS  
V
V
GS=20 V, VDS=0 V  
GS=10 V, I D=80 A  
Gate-source leakage current  
-
-
1
100 nA  
RDS(on)  
Drain-source on-state resistance  
3.5  
4.0  
m  
V
GS=10 V, I D=80 A,  
-
3.2  
3.7  
SMD version  
Rev. 1.1  
page 2  
2008-02-22  
IPB80N04S2-H4  
IPP80N04S2-H4, IPI80N04S2-H4  
Values  
typ.  
Parameter  
Symbol  
Conditions  
Unit  
min.  
max.  
Dynamic characteristics2)  
Input capacitance  
Output capacitance  
Reverse transfer capacitance  
Turn-on delay time  
Rise time  
C iss  
C oss  
Crss  
t d(on)  
t r  
-
-
-
-
-
-
-
4400  
1800  
480  
23  
-
-
-
-
-
-
-
pF  
ns  
V
GS=0 V, VDS=25 V,  
f =1 MHz  
63  
V
DD=20 V, VGS=10 V,  
I D=80 A, R G=1.3 Ω  
t d(off)  
t f  
Turn-off delay time  
Fall time  
46  
22  
Gate Charge Characteristics2)  
Gate to source charge  
Gate to drain charge  
Gate charge total  
Q gs  
-
-
-
-
21  
38  
29  
70  
148  
-
nC  
Q gd  
V
V
DD=32 V, I D=80 A,  
GS=0 to 10 V  
Q g  
103  
4.9  
Vplateau  
Gate plateau voltage  
V
A
Reverse Diode  
Diode continous forward current2)  
Diode pulse current2)  
I S  
-
-
-
-
80  
T C=25 °C  
I S,pulse  
320  
V
GS=0 V, I F=80 A,  
VSD  
Diode forward voltage  
Reverse recovery time2)  
Reverse recovery charge2)  
-
-
-
0.9  
195  
370  
1.3  
V
T j=25 °C  
VR=20 V, I F=I S,  
diF/dt =100 A/µs  
t rr  
-
-
ns  
nC  
VR=20 V, I F=I S,  
diF/dt =100 A/µs  
Q rr  
1) Current is limited by bondwire; with an R thJC = 0.5K/W the chip is able to carry 200A at 25°C. For detailed  
information see Application Note ANPS071E at www.infineon.com/optimos  
2) Defined by design. Not subject to production test.  
3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain  
connection. PCB is vertical in still air.  
Rev. 1.1  
page 3  
2008-02-22  
IPB80N04S2-H4  
IPP80N04S2-H4, IPI80N04S2-H4  
1 Power dissipation  
2 Drain current  
P
tot = f(T C); VGS 6 V  
I D = f(T C); VGS 10 V  
350  
300  
250  
200  
150  
100  
50  
100  
80  
60  
40  
20  
0
0
0
50  
100  
150  
200  
0
50  
100  
150  
200  
T
C [°C]  
T
C [°C]  
3 Safe operating area  
4 Max. transient thermal impedance  
thJC = f(t p)  
I D = f(VDS); T C = 25 °C; D = 0  
parameter: t p  
Z
parameter: D =t p/T  
100  
1000  
100  
10  
10 µs  
0.5  
100 µs  
10-1  
1 ms  
0.1  
0.05  
10-2 0.01  
single pulse  
10-3  
1
10-7  
10-6  
10-5  
10-4  
10-3  
10-2  
10-1  
100  
0.1  
1
10  
100  
V
DS [V]  
t
p [s]  
Rev. 1.1  
page 4  
2008-02-22  
IPB80N04S2-H4  
IPP80N04S2-H4, IPI80N04S2-H4  
5 Typ. output characteristics  
I D = f(VDS); T j = 25 °C  
parameter: VGS  
6 Typ. drain-source on-state resistance  
DS(on) = (I D); T j = 25 °C  
R
parameter: VGS  
300  
10 V  
6.5 V  
7 V  
5.5 V  
6 V  
18  
250  
200  
150  
100  
50  
6 V  
6.5 V  
14  
10  
6
5.5 V  
5 V  
7 V  
10 V  
0
2
0
0
2
4
6
8
10  
80  
160  
240  
320  
I
D [A]  
V
DS [V]  
7 Typ. transfer characteristics  
I D = f(VGS); VDS = 6V  
parameter: T j  
8 Typ. Forward transconductance  
g fs = f(I D); T j = 25°C  
parameter: g fs  
320  
280  
240  
200  
160  
120  
80  
200  
175  
150  
125  
100  
75  
50  
175 °C  
40  
25  
25 °C  
-55 °C  
0
0
2
3
4
5
6
7
0
50  
100  
150  
V
GS [V]  
I D [A]  
Rev. 1.1  
page 5  
2008-02-22  
IPB80N04S2-H4  
IPP80N04S2-H4, IPI80N04S2-H4  
9 Typ. Drain-source on-state resistance  
DS(ON) = f(T j)  
10 Typ. gate threshold voltage  
GS(th) = f(T j); VGS = VDS  
R
V
parameter: I D = 80 A; VGS = 10 V  
parameter: I D  
6
4
3.5  
3
5
4
3
2
1250 µA  
250 µA  
2.5  
2
1.5  
1
-60  
-20  
20  
60  
100  
140  
180  
-60  
-20  
20  
60  
100  
140  
180  
T j [°C]  
T j [°C]  
11 Typ. capacitances  
12 Typical forward diode characteristicis  
C = f(VDS); VGS = 0 V; f = 1 MHz  
IF = f(VSD)  
parameter: T j  
103  
104  
103  
102  
102  
Ciss  
Coss  
25 °C  
175 °C  
101  
Crss  
100  
0
5
10  
15  
20  
25  
30  
0
0.2  
0.4  
0.6  
0.8  
1
1.2  
1.4  
V
DS [V]  
V
SD [V]  
Rev. 1.1  
page 6  
2008-02-22  
IPB80N04S2-H4  
IPP80N04S2-H4, IPI80N04S2-H4  
13 Avalanche energy  
AS = f(T j)  
14 Typ. gate charge  
GS = f(Q gate); I D = 80 A pulsed  
E
V
parameter: I D  
3000  
12  
10  
8
20 A  
32 V  
8 V  
2500  
2000  
1500  
1000  
500  
6
40 A  
80 A  
4
2
0
0
25  
75  
125  
175  
0
20  
40  
60  
80  
100  
120  
T j [°C]  
Q
gate [nC]  
15 Drain-source breakdown voltage  
16 Gate charge waveforms  
V
BR(DSS) = f(T j); I D = 1 mA  
48  
46  
44  
42  
40  
38  
36  
VGS  
Qg  
Qgate  
Qgd  
Qgs  
-60  
-20  
20  
60  
100  
140  
180  
T j [°C]  
Rev. 1.1  
page 7  
2008-02-22  
IPB80N04S2-H4  
IPP80N04S2-H4, IPI80N04S2-H4  
Published by  
Infineon Technologies AG  
81726 Munich, Germany  
© Infineon Technologies AG 2008  
All Rights Reserved.  
Legal Disclaimer  
The information given in this document shall in no event be regarded as a guarantee of conditions  
or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein,  
any typical values stated herein and/or any information regarding the application of the device,  
Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including  
without limitation warranties of noninfringement of intellectual property rights of any third party.  
Information  
For further information on technology, delivery terms and conditions and prices please  
contact your nearest Infineon Technologies Office (www.infineon.com).  
Warnings  
Due to technical requirements components may contain dangerous substances. For information  
on the types in question please contact your nearest Infineon Technologies Office.  
Infineon Technologies Components may only be used in life-support devices or systems with the  
express written approval of Infineon Technologies, if a failure of such components can reasonably  
be expected to cause the failure of that life-support device or system, or to affect the safety or  
effectiveness of that device or system. Life support devices or systems are intended to be  
implanted in the human body, or to support and/or maintain and sustain and/or protect human life.  
If they fail, it is reasonable to assume that the health of the user or other persons may be  
endangered.  
Rev. 1.1  
page 8  
2008-02-22  
IPB80N04S2-H4  
IPP80N04S2-H4, IPI80N04S2-H4  
Revision History  
Version  
Date  
Changes  
Update of side 1 and 10 according  
to new template  
Revision 1.1  
Revision 1.1  
22.02.2008  
22.02.2008  
Update of SOA diagram, labelling  
Rev. 1.1  
page 9  
2008-02-22  

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