IPSH5N03LAG [INFINEON]
OptiMOS㈢2 Power-Transistor; OptiMOS®2功率三极管
| 型号： | IPSH5N03LAG |
| 厂家： | 
Infineon |
| 描述： | OptiMOS㈢2 Power-Transistor |
| 文件： | 总10页 (文件大小：325K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IPDH5N03LA G IPSH5N03LA G
OptiMOS®2 Power-Transistor
Product Summary
V DS
Features
25
5.2
50
V
• Ideal for high-frequency dc/dc converters
• Qualified according to JEDEC1) for target application
R
DS(on),max (SMD version)
mΩ
A
I D
• N-channel, logic level
• Excellent gate charge x R DS(on) product (FOM)
• Superior thermal resistance
• 175 °C operating temperature
• Pb-free lead plating; RoHS compliant
Type
IPDH5N03LA
IPSH5N03LA
Package
Marking
P-TO252-3-11
H5N03LA
P-TO251-3-11
H5N03LA
Maximum ratings, at T j=25 °C, unless otherwise specified
Value
Parameter
Symbol Conditions
Unit
T C=25 °C2)
I D
Continuous drain current
50
50
A
T C=100 °C
T C=25 °C3)
I D,pulse
Pulsed drain current
350
225
E AS
I D=45 A, R GS=25 Ω
Avalanche energy, single pulse
mJ
I D=50 A, V DS=20 V,
di /dt =200 A/µs,
Reverse diode dv /dt
dv /dt
6
kV/µs
T
j,max=175 °C
Gate source voltage4)
V GS
±20
83
V
P tot
T C=25 °C
Power dissipation
W
°C
T j, T stg
Operating and storage temperature
IEC climatic category; DIN IEC 68-1
-55 ... 175
55/175/56
Rev. 1.3
page 1
2006-05-11
IPDH5N03LA G IPSH5N03LA G
Values
typ.
Parameter
Symbol Conditions
Unit
min.
max.
Thermal characteristics
R thJC
Thermal resistance, junction - case
SMD version, device on PCB
-
-
-
-
-
-
1.8
75
50
K/W
R thJA
minimal footprint
6 cm2 cooling area5)
Electrical characteristics, at T j=25 °C, unless otherwise specified
Static characteristics
V (BR)DSS
V GS(th)
V
V
GS=0 V, I D=1 mA
DS=V GS, I D=35 µA
Drain-source breakdown voltage
Gate threshold voltage
25
-
-
V
1.2
1.6
2
V
DS=25 V, V GS=0 V,
I DSS
Zero gate voltage drain current
-
-
0.1
10
1
µA
T j=25 °C
V
DS=25 V, V GS=0 V,
100
T j=125 °C
I GSS
V
V
GS=20 V, V DS=0 V
GS=4.5 V, I D=30 A
Gate-source leakage current
-
-
10
100 nA
R DS(on)
Drain-source on-state resistance
7.0
8.7
8.5
5.4
5.2
-
mΩ
V
GS=4.5 V, I D=30 A,
-
-
6.8
4.5
4.3
1
SMD version
V
GS=10 V, I D=50 A
V
GS=10 V, I D=50 A,
-
SMD version
R G
g fs
Gate resistance
-
Ω
|V DS|>2|I D|R DS(on)max
I D=50 A
,
Transconductance
38
76
-
S
1) J-STD20 and JESD22
2) Current is limited by bondwire; with anR thJC=1.8 K/W the chip is able to carry 94 A.
3) See figure 3
4) T j,max=150 °C and duty cycle D <0.25 for V GS<-5 V
5) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
2
Rev. 1.3
page 2
2006-05-11
IPDH5N03LA G IPSH5N03LA G
Values
typ.
Parameter
Symbol Conditions
Unit
min.
max.
Dynamic characteristics
Input capacitance
Output capacitance
Reverse transfer capacitance
Turn-on delay time
Rise time
C iss
-
-
-
-
-
-
-
2093
800
98
2653 pF
1064
V
GS=0 V, V DS=15 V,
C oss
Crss
t d(on)
t r
f =1 MHz
147
10
14
11
43
6.9
ns
7.2
29
V
DD=15 V, V GS=10 V,
I D=25 A, R G=2.7 Ω
t d(off)
t f
Turn-off delay time
Fall time
4.6
Gate Charge Characteristics6)
Gate to source charge
Gate charge at threshold
Gate to drain charge
Switching charge
Q gs
-
-
-
-
-
-
6.7
3.3
4.6
8.0
17
9.0
4.2
6.9
11
22
-
nC
Q g(th)
Q gd
V
V
DD=15 V, I D=25 A,
GS=0 to 5 V
Q sw
Q g
Gate charge total
V plateau
Gate plateau voltage
3.2
V
V
V
DS=0.1 V,
Q g(sync)
Q oss
Gate charge total, sync. FET
Output charge
-
-
15
17
19
23
nC
GS=0 to 5 V
V
DD=15 V, V GS=0 V
Reverse Diode
I S
Diode continous forward current
Diode pulse current
-
-
-
-
50
A
T C=25 °C
I S,pulse
350
V
GS=0 V, I F=50 A,
V SD
Q rr
Diode forward voltage
-
-
0.92
-
1.2
10
V
T j=25 °C
V R=15 V, I F=I S,
di F/dt =400 A/µs
Reverse recovery charge
nC
6) See figure 16 for gate charge parameter definition
Rev. 1.3
page 3
2006-05-11
IPDH5N03LA G IPSH5N03LA G
2 Drain current
1 Power dissipation
P
tot=f(T C)
I D=f(T C); V GS≥10 V
90
80
70
60
50
40
30
20
10
60
50
40
30
20
10
0
0
0
50
100
150
200
0
50
100
150
200
T
C [°C]
T
C [°C]
3 Safe operating area
I D=f(V DS); T C=25 °C; D =0
parameter: t p
4 Max. transient thermal impedance
thJC=f(t p)
Z
parameter: D =t p/T
1000
10
1 µs
limited by on-state
resistance
10 µs
100
0.5
1
100 µs
0.2
0.1
DC
1 ms
0.05
10
10 ms
0.1
0.02
0.01
single pulse
1
0
0
0
0
0
0
1
0.01
10-6
10-5
10-4
10-3
p [s]
10-2
10-1
100
0.1
1
10
100
t
V
DS [V]
Rev. 1.3
page 4
2006-05-11
IPDH5N03LA G IPSH5N03LA G
5 Typ. output characteristics
I D=f(V DS); T j=25 °C
6 Typ. drain-source on resistance
DS(on)=f(I D); T j=25 °C
R
parameter: V GS
parameter: V GS
100
20
3 V
18
4.5 V
10 V
90
4.1 V
4.1 V
3.8 V
3.8 V
3.5 V
3.2 V
80
70
60
50
40
30
20
10
0
16
14
12
10
8
4.5 V
10 V
3.5 V
3.2 V
6
4
3 V
2
2.8 V
0
0
1
2
3
0
20
40
60
80
100
V
DS [V]
I
D [A]
7 Typ. transfer characteristics
I D=f(V GS); |V DS|>2|I D|R DS(on)max
parameter: T j
8 Typ. forward transconductance
g fs=f(I D); T j=25 °C
100
80
70
60
50
40
30
20
10
0
80
60
40
20
175 °C
25 °C
0
0
1
2
3
4
5
0
10
20
30
40
50
60
I
D [A]
V
GS [V]
Rev. 1.3
page 5
2006-05-11
IPDH5N03LA G IPSH5N03LA G
9 Drain-source on-state resistance
10 Typ. gate threshold voltage
GS(th)=f(T j); V GS=V DS
R
DS(on)=f(T j); I D=50 A; V GS=10 V
V
parameter: I D
10
9
2.5
8
2
1.5
1
7
350 µA
98 %
6
35 µA
5
typ
4
3
2
1
0
0.5
0
-60
-20
20
60
100
140
180
-60
-20
20
60
100
140
180
T j [°C]
T j [°C]
11 Typ. Capacitances
12 Forward characteristics of reverse diode
I F=f(V SD
C =f(V DS); V GS=0 V; f =1 MHz
)
parameter: T j
104
1000
10000
25 °C
Ciss
Coss
103
1000
100
10
175 °C, 98%
175 °C
Crss
25 °C, 98%
102
100
10
1
0
5
10
15
20
25
30
0.0
0.5
1.0
SD [V]
1.5
2.0
V
DS [V]
V
Rev. 1.3
page 6
2006-05-11
IPDH5N03LA G IPSH5N03LA G
13 Avalanche characteristics
AS=f(t AV); R GS=25 Ω
14 Typ. gate charge
GS=f(Q gate); I D=25 A pulsed
V
I
parameter: Tj(start)
parameter: V DD
100
12
15 V
10
8
5 V
100 °C
25 °C
150 °C
20 V
10
6
4
2
1
1
0
0
10
100
1000
10
20
30
Q
gate [nC]
t
AV [µs]
15 Drain-source breakdown voltage
16 Gate charge waveforms
V
BR(DSS)=f(T j); I D=1 mA
29
28
27
26
25
24
23
22
21
20
V GS
Q g
V gs(th)
Q g(th)
Q sw
Q gd
Q gate
Q gs
-60
-20
20
60
100
140
180
T j [°C]
Rev. 1.3
page 7
2006-05-11
IPDH5N03LA G IPSH5N03LA G
Package Outline
PG-TO252-3-11
Rev. 1.3
page 8
2006-05-11
IPDH5N03LA G IPSH5N03LA G
Package Outline
PG-TO251-3-11
Rev. 1.3
page 9
2006-05-11
IPDH5N03LA G IPSH5N03LA G
Published by
Infineon Technologies AG
81726 München, Germany
© Infineon Technologies AG 2006.
All Rights Reserved.
Attention please!
The information given in this data sheet shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com ).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Rev. 1.3
page 10
2006-05-11
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