IQE050N08NM5CGSC [INFINEON]
英飞凌推出了创新型 源极底置 技术系列扩展的新产品， PQFN 3.3x3.3 源极底置 DSC 封装OptiMOSTM 5 80 V：IQE050N08NM5CGSC。革命性的源极底置技术引入了倒置式硅芯片，该芯片在组件内部上下颠倒。这种调整使得源极电位（而不是漏极电位）可以通过导热垫与 PCB 连接。因此，它具有几点优势，如热能力增强，先进的功率密度，或具有改善板上布局的可能性。;
| 型号： | IQE050N08NM5CGSC |
| 厂家： | 
Infineon |
| 描述： | 英飞凌推出了创新型 源极底置 技术系列扩展的新产品， PQFN 3.3x3.3 源极底置 DSC 封装OptiMOSTM 5 80 V：IQE050N08NM5CGSC。革命性的源极底置技术引入了倒置式硅芯片，该芯片在组件内部上下颠倒。这种调整使得源极电位（而不是漏极电位）可以通过导热垫与 PCB 连接。因此，它具有几点优势，如热能力增强，先进的功率密度，或具有改善板上布局的可能性。 PC |
| 文件： | 总13页 (文件大小：1592K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IQE050N08NM5CGSC
MOSFET
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ80ꢀV
PG-WHTFN-9
5
6
Features
7
8
•ꢀOptimizedꢀforꢀsynchronousꢀrectification
•ꢀN-channel,ꢀnormalꢀlevel
•ꢀVeryꢀlowꢀon-resistanceꢀRDS(on)
•ꢀSuperiorꢀthermalꢀresistance
9
Pin 1
4
2
3
3
2
4
1
•ꢀ100%ꢀavalancheꢀtested
•ꢀPb-freeꢀleadꢀplating;ꢀRoHSꢀcompliant
•ꢀHalogen-freeꢀaccordingꢀtoꢀIEC61249-2-21
Productꢀvalidation
FullyꢀqualifiedꢀaccordingꢀtoꢀJEDECꢀforꢀIndustrialꢀApplications
Drain
Pin 5-8
Tableꢀ1ꢀꢀꢀꢀꢀKeyꢀPerformanceꢀParameters
*1
Gate
Pin 9
Parameter
Value
Unit
Source
Pin 1-4
VDS
80
V
*1: Internal body diode
RDS(on),max
ID
5.0
99
mΩ
A
Qoss
40
nC
nC
QGꢀ(0V...10V)
35
Typeꢀ/ꢀOrderingꢀCode
Package
Marking
RelatedꢀLinks
IQE050N08NM5CGSC
PG-WHTFN-9
R
-
Final Data Sheet
1
Rev.ꢀ2.0,ꢀꢀ2022-05-02
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ80ꢀV
IQE050N08NM5CGSC
TableꢀofꢀContents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Final Data Sheet
2
Rev.ꢀ2.0,ꢀꢀ2022-05-02
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ80ꢀV
IQE050N08NM5CGSC
1ꢀꢀꢀꢀꢀMaximumꢀratings
atꢀTA=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified
Tableꢀ2ꢀꢀꢀꢀꢀMaximumꢀratings
Values
Typ.
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
-
-
-
-
-
-
-
-
99
70
54
16
VGS=10ꢀV,ꢀTC=25ꢀ°C
VGS=10ꢀV,ꢀTC=100ꢀ°C
Continuous drain current1)
ID
A
VGS=6ꢀV,ꢀTC=100ꢀ°C
VGS=10V,TA=25°C,RthJA=60°C/W2)
Pulsed drain current3)
Avalanche energy, single pulse4)
ID,pulse
EAS
-
-
-
-
396
184
20
A
TA=25ꢀ°C
-
mJ
V
ID=20ꢀA,ꢀRGS=25ꢀΩ
Gate source voltage
VGS
-20
-
-
-
-
-
100
2.5
TC=25ꢀ°C
Power dissipation
Ptot
W
TA=25ꢀ°C,ꢀRthJA=60ꢀ°C/W2)
IEC climatic category; DIN IEC 68-1:
55/175/56
Operating and storage temperature
Tj,ꢀTstg
-55
-
175
°C
2ꢀꢀꢀꢀꢀThermalꢀcharacteristics
Tableꢀ3ꢀꢀꢀꢀꢀThermalꢀcharacteristics
Values
Typ.
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Thermal resistance, junction - case,
bottom
RthJC
RthJC
RthJA
-
0.9
0.7
-
1.5
°C/W -
°C/W -
°C/W -
Thermal resistance, junction - case,
top
-
-
-
Thermal resistance, junction - ambient,
6 cm² cooling area2)
60
1) Rating refers to the product only with datasheet specified absolute maximum values, maintaining case temperature
as specified. For other case temperatures please refer to Diagram 2. De-rating will be required based on the actual
environmental conditions.
2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
3) See Diagram 3 for more detailed information
4) See Diagram 13 for more detailed information
Final Data Sheet
3
Rev.ꢀ2.0,ꢀꢀ2022-05-02
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ80ꢀV
IQE050N08NM5CGSC
3ꢀꢀꢀꢀꢀElectricalꢀcharacteristics
atꢀTj=25ꢀ°C,ꢀunlessꢀotherwiseꢀspecified
Tableꢀ4ꢀꢀꢀꢀꢀStaticꢀcharacteristics
Values
Typ.
-
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
80
Max.
-
Drain-source breakdown voltage
Gate threshold voltage
V(BR)DSS
VGS(th)
V
V
VGS=0ꢀV,ꢀID=1ꢀmA
VDS=VGS,ꢀID=49ꢀµA
2.2
3.0
3.8
-
-
0.1
10
1.0
100
VDS=80ꢀV,ꢀVGS=0ꢀV,ꢀTj=25ꢀ°C
VDS=80ꢀV,ꢀVGS=0ꢀV,ꢀTj=125ꢀ°C
Zero gate voltage drain current
Gate-source leakage current
Drain-source on-state resistance
IDSS
µA
nA
IGSS
-
10
100
VGS=20ꢀV,ꢀVDS=0ꢀV
-
-
4.3
6.1
5.0
8.5
VGS=10ꢀV,ꢀID=20ꢀA
VGS=6ꢀV,ꢀID=5ꢀA
RDS(on)
mΩ
Gate resistance
RG
gfs
-
-
0.62
50
-
-
Ω
-
Transconductance
S
|VDS|≥2|ID|RDS(on)max,ꢀID=20ꢀA
Tableꢀ5ꢀꢀꢀꢀꢀDynamicꢀcharacteristics
Values
Typ.
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Input capacitance1)
Output capacitance1)
Reverse transfer capacitance1)
Ciss
Coss
Crss
-
-
-
2200 2900 pF
VGS=0ꢀV,ꢀVDS=40ꢀV,ꢀf=1ꢀMHz
VGS=0ꢀV,ꢀVDS=40ꢀV,ꢀf=1ꢀMHz
VGS=0ꢀV,ꢀVDS=40ꢀV,ꢀf=1ꢀMHz
370
21
480
37
pF
pF
VDD=40ꢀV,ꢀVGS=10ꢀV,ꢀID=20ꢀA,
RG,ext=1.6ꢀΩ
Turn-on delay time
Rise time
td(on)
tr
td(off)
tf
-
-
-
-
9.4
4.6
16.1
4.0
-
-
-
-
ns
ns
ns
ns
VDD=40ꢀV,ꢀVGS=10ꢀV,ꢀID=20ꢀA,
RG,ext=1.6ꢀΩ
VDD=40ꢀV,ꢀVGS=10ꢀV,ꢀID=20ꢀA,
RG,ext=1.6ꢀΩ
Turn-off delay time
Fall time
VDD=40ꢀV,ꢀVGS=10ꢀV,ꢀID=20ꢀA,
RG,ext=1.6ꢀΩ
Tableꢀ6ꢀꢀꢀꢀꢀGateꢀchargeꢀcharacteristics2)ꢀ
Values
Typ.
10
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Max.
Gate to source charge
Gate charge at threshold
Gate to drain charge1)
Switching charge
Qgs
-
-
-
-
-
-
-
-
-
nC
nC
nC
nC
nC
V
VDD=40ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV
VDD=40ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV
VDD=40ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV
VDD=40ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV
VDD=40ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV
VDD=40ꢀV,ꢀID=20ꢀA,ꢀVGS=0ꢀtoꢀ10ꢀV
VDS=0.1ꢀV,ꢀVGS=0ꢀtoꢀ10ꢀV
Qg(th)
Qgd
6.7
-
8.8
13.2
Qsw
12.1
35
-
Gate charge total1)
Qg
44
-
Gate plateau voltage
Gate charge total, sync. FET
Output charge1)
Vplateau
Qg(sync)
Qoss
4.5
29
-
nC
nC
40
53
VDS=40ꢀV,ꢀVGS=0ꢀV
1) Defined by design. Not subject to production test.
2) See ″Gate charge waveforms″ for parameter definition
Final Data Sheet
4
Rev.ꢀ2.0,ꢀꢀ2022-05-02
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ80ꢀV
IQE050N08NM5CGSC
Tableꢀ7ꢀꢀꢀꢀꢀReverseꢀdiode
Values
Parameter
Symbol
Unit Noteꢀ/ꢀTestꢀCondition
Min.
Typ.
-
Max.
75
Diode continuous forward current
Diode pulse current
IS
-
-
-
-
-
A
TC=25ꢀ°C
IS,pulse
VSD
trr
-
396
1.1
74
A
TC=25ꢀ°C
Diode forward voltage
0.83
37
30
V
VGS=0ꢀV,ꢀIF=20ꢀA,ꢀTj=25ꢀ°C
VR=40ꢀV,ꢀIF=20ꢀA,ꢀdiF/dt=100ꢀA/µs
VR=40ꢀV,ꢀIF=20ꢀA,ꢀdiF/dt=100ꢀA/µs
Reverse recovery time1)
Reverse recovery charge1)
ns
nC
Qrr
60
1) Defined by design. Not subject to production test.
Final Data Sheet
5
Rev.ꢀ2.0,ꢀꢀ2022-05-02
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ80ꢀV
IQE050N08NM5CGSC
4ꢀꢀꢀꢀꢀElectricalꢀcharacteristicsꢀdiagrams
Diagramꢀ1:ꢀPowerꢀdissipation
Diagramꢀ2:ꢀDrainꢀcurrent
120
120
100
80
60
40
20
0
100
80
60
40
20
0
0
25
50
75
100
125
150
175
200
0
25
50
75
100
125
150
175
200
TCꢀ[°C]
TCꢀ[°C]
Ptot=f(TC)
ID=f(TC);ꢀVGS≥10ꢀV
Diagramꢀ3:ꢀSafeꢀoperatingꢀarea
Diagramꢀ4:ꢀMax.ꢀtransientꢀthermalꢀimpedance
103
102
single pulse
0.01
1 µs
0.02
0.05
0.1
0.2
0.5
10 µs
102
101
101
100 µs
100
10-1
10-2
10-3
10 ms
1 ms
100
DC
10-1
10-2
10-1
100
101
102
10-6
10-5
10-4
10-3
10-2
10-1
100
VDSꢀ[V]
tpꢀ[s]
ID=f(VDS);ꢀTC=25ꢀ°C;ꢀD=0;ꢀparameter:ꢀtp
ZthJC=f(tp);ꢀparameter:ꢀD=tp/T
Final Data Sheet
6
Rev.ꢀ2.0,ꢀꢀ2022-05-02
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ80ꢀV
IQE050N08NM5CGSC
Diagramꢀ5:ꢀTyp.ꢀoutputꢀcharacteristics
Diagramꢀ6:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance
400
14
10 V
8 V
350
12
300
250
200
150
100
50
7 V
5 V
10
6 V
8
7 V
6
4
2
0
8 V
6 V
10 V
5 V
4.5 V
0
0
1
2
3
4
5
0
25
50
75
100
125
150
175
200
VDSꢀ[V]
IDꢀ[A]
ID=f(VDS),ꢀTj=25ꢀ°C;ꢀparameter:ꢀVGS
RDS(on)=f(ID),ꢀTj=25ꢀ°C;ꢀparameter:ꢀVGS
Diagramꢀ7:ꢀTyp.ꢀtransferꢀcharacteristics
Diagramꢀ8:ꢀTyp.ꢀdrain-sourceꢀonꢀresistance
350
14
300
250
200
150
100
50
12
10
8
25 °C
175 °C
6
175 °C
4
25 °C
2
0
0
0
1
2
3
4
5
6
7
0
3
6
9
12
15
VGSꢀ[V]
VGSꢀ[V]
ID=f(VGS),ꢀ|VDS|>2|ID|RDS(on)max;ꢀparameter:ꢀTj
RDS(on)=f(VGS),ꢀID=20ꢀA;ꢀparameter:ꢀTj
Final Data Sheet
7
Rev.ꢀ2.0,ꢀꢀ2022-05-02
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ80ꢀV
IQE050N08NM5CGSC
Diagramꢀ9:ꢀNormalizedꢀdrain-sourceꢀonꢀresistance
Diagramꢀ10:ꢀTyp.ꢀgateꢀthresholdꢀvoltage
2.4
4.0
3.5
3.0
2.5
2.0
2.0
1.6
1.2
0.8
0.4
0.0
490 µA
49 µA
1.5
1.0
0.5
0.0
-75 -50 -25
0
25 50 75 100 125 150 175 200
-75 -50 -25
0
25 50 75 100 125 150 175 200
Tjꢀ[°C]
Tjꢀ[°C]
RDS(on)=f(Tj),ꢀID=20ꢀA,ꢀVGS=10ꢀV
VGS(th)=f(Tj),ꢀVGS=VDS;ꢀparameter:ꢀID
Diagramꢀ11:ꢀTyp.ꢀcapacitances
Diagramꢀ12:ꢀForwardꢀcharacteristicsꢀofꢀreverseꢀdiode
104
103
25 °C
25 °C, max
175 °C
175 °C, max
Ciss
103
102
101
102
101
100
Coss
Crss
0
10
20
30
40
50
60
70
80
0.00
0.25
0.50
0.75
1.00
1.25
1.50
VDSꢀ[V]
VSDꢀ[V]
C=f(VDS);ꢀVGS=0ꢀV;ꢀf=1ꢀMHz
IF=f(VSD);ꢀparameter:ꢀTj
Final Data Sheet
8
Rev.ꢀ2.0,ꢀꢀ2022-05-02
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ80ꢀV
IQE050N08NM5CGSC
Diagramꢀ13:ꢀAvalancheꢀcharacteristics
Diagramꢀ14:ꢀTyp.ꢀgateꢀcharge
102
10
16 V
40 V
64 V
8
6
4
2
0
101
25 °C
100 °C
150 °C
100
10-1
100
101
102
103
0
5
10
15
20
25
30
35
tAVꢀ[µs]
Qgateꢀ[nC]
IAS=f(tAV);ꢀRGS=25ꢀΩ;ꢀparameter:ꢀTj,start
VGS=f(Qgate),ꢀID=20ꢀAꢀpulsed,ꢀTj=25ꢀ°C;ꢀparameter:ꢀVDD
Diagramꢀ15:ꢀDrain-sourceꢀbreakdownꢀvoltage
Diagram Gate charge waveforms
88
86
84
82
80
78
76
-75 -50 -25
0
25 50 75 100 125 150 175 200
Tjꢀ[°C]
VBR(DSS)=f(Tj);ꢀID=1ꢀmA
Final Data Sheet
9
Rev.ꢀ2.0,ꢀꢀ2022-05-02
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ80ꢀV
IQE050N08NM5CGSC
5ꢀꢀꢀꢀꢀPackageꢀOutlines
PACKAGE - GROUP
NUMBER:
PG-WHTFN-9-U01
MILLIMETERS
DIMENSIONS
MIN.
---
MAX.
0.75
0.05
0.40
0.30
3.40
2.51
2.25
0.93
1.78
3.40
1.70
2.23
1.485
A
A1
b
0
0.20
0.10
3.20
2.31
1.95
0.73
1.58
3.20
1.50
1.93
1.285
c
D
D1
D2
D3
D4
E
E1
E2
E3
e
0.65
L
0.40
0.35
0.32
0.60
0.55
0.52
L1
L2
Figureꢀ1ꢀꢀꢀꢀꢀOutlineꢀPG-WHTFN-9,ꢀdimensionsꢀinꢀmm
Final Data Sheet
10
Rev.ꢀ2.0,ꢀꢀ2022-05-02
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ80ꢀV
IQE050N08NM5CGSC
1.629
1.059
0.15
0.35
8x
0.595
1.1
0.3
6x
0.975
0.3
4x
1.06
2x
1.6
0.42
2x
0.65
6x
0.3
4x
0.475
0.65
6x
1.1
4x
Pin 1
0.365
0.055
2x
1.35
1.15
0.975
0.615
copper
solder mask
All dimensions are in units mm
stencil apertures
Figureꢀ2ꢀꢀꢀꢀꢀOutlineꢀFootprintꢀ(PG-WHTFN-9-1),ꢀdimensionsꢀinꢀmm
Final Data Sheet
11
Rev.ꢀ2.0,ꢀꢀ2022-05-02
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ80ꢀV
IQE050N08NM5CGSC
3.6
12
Figureꢀ3ꢀꢀꢀꢀꢀOutlineꢀTapeꢀ(PG-WHTFN-9-1),ꢀdimensionsꢀinꢀmm
Final Data Sheet
12
Rev.ꢀ2.0,ꢀꢀ2022-05-02
OptiMOSTMꢀ5ꢀPower-Transistor,ꢀ80ꢀV
IQE050N08NM5CGSC
RevisionꢀHistory
IQE050N08NM5CGSC
Revision:ꢀ2022-05-02,ꢀRev.ꢀ2.0
Previous Revision
Revision Date
Subjects (major changes since last revision)
Release of final version
2.0
2022-05-02
Trademarks
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automotive,ꢀaviationꢀandꢀaerospaceꢀapplicationsꢀorꢀsystemsꢀonlyꢀwithꢀtheꢀexpressꢀwrittenꢀapprovalꢀofꢀInfineonꢀTechnologies,ꢀifꢀa
failureꢀofꢀsuchꢀcomponentsꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀtheꢀfailureꢀofꢀthatꢀlife-support,ꢀautomotive,ꢀaviationꢀand
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intendedꢀtoꢀbeꢀimplantedꢀinꢀtheꢀhumanꢀbodyꢀorꢀtoꢀsupportꢀand/orꢀmaintainꢀandꢀsustainꢀand/orꢀprotectꢀhumanꢀlife.ꢀIfꢀtheyꢀfail,ꢀitꢀis
reasonableꢀtoꢀassumeꢀthatꢀtheꢀhealthꢀofꢀtheꢀuserꢀorꢀotherꢀpersonsꢀmayꢀbeꢀendangered.
Final Data Sheet
13
Rev.ꢀ2.0,ꢀꢀ2022-05-02
相关型号：
IQE065N10NM5
IQE65N10NM5 是英飞凌对创新性 源极底置 技术的延伸。 OptiMOS™ 5 30 V PQFN 3.3x3.3 源极底置具有 30 V 和极低 0.85 mOhm RDS(on)。革命性的源极底置技术使硅片倒置在元件内部。调整后，源极电位（而非漏极电位）即可通过导热垫连接到 PCB。这样就能提供多项优势，如增强热性能、高功率密度和改善布局。此外，更高的效率、更低的主动散热要求及有效的热管理布局有利于实现系统级优势。RDS(on) 新标杆和创新布局能力使 源极底置 概念在温度管理方面处于领先地位。源极底置产品组合解决了各种应用问题，包括 电机驱动、 电信、 SMPS 或 服务器。目前，有两种不同的产品尺寸采用了这项新技术：源极底置标准栅极和源极底置置中栅极（并行优化）。
INFINEON
IQE065N10NM5CG
IQE065N10NM5CG 是英飞凌对创新性 源极底置 技术的延伸。 OptiMOS™ 5 30 V PQFN 3.3x3.3 源极底置具有 30 V 和极低 0.85 mOhm RDS(on)。革命性的源极底置技术使硅片倒置在元件内部。调整后，源极电位（而非漏极电位）即可通过导热垫连接到 PCB。这样就能提供多项优势，如增强热性能、高功率密度和改善布局。此外，更高的效率、更低的主动散热要求及有效的热管理布局有利于实现系统级优势。RDS(on) 新标杆和创新布局能力使 源极底置 概念在温度管理方面处于领先地位。源极底置产品组合解决了各种应用问题，包括 电机驱动、 电信、 SMPS 或 服务器。目前，有两种不同的产品尺寸采用了这项新技术：源极底置标准栅极和源极底置置中栅极（并行优化）。
INFINEON
IQE065N10NM5SC
英飞凌推出了创新型 源极底置 技术系列扩展的新产品， PQFN 3.3x3.3 源极底置 DSC 封装OptiMOSTM 5 100 V: IQE065N10NM5SC。革命性的源极底置技术引入了倒置式硅芯片，该芯片在组件内部上下颠倒。这种调整使得源极电位（而不是漏极电位）可以通过导热垫与 PCB 连接。因此，它具有几点优势，如热能力增强，先进的功率密度，或具有改善板上布局的可能性。
INFINEON
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