IR1176 [INFINEON]

SYNCHRONOUS RECTIFIER DRIVER; 同步整流驱动器


型号：	IR1176
厂家：	Infineon
描述：	SYNCHRONOUS RECTIFIER DRIVER 同步整流驱动器驱动器 MOSFET驱动器驱动程序和接口接口集成电路光电二极管
文件：	总12页 (文件大小：419K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Preliminary Data Sheet PD60185-C

IR1176

SYNCHRONOUS RECTIFIER DRIVER

Product Summary

Features

•

Provides constant and proper gate drive to power

MOSFETs regardless of transformer output

Minimizes loss due to power MOSFET body

drain diode conduction

5Vdc

•

4A/4A

2MHz

O+/- (peak)

Stand alone operation - no ties to primary side

Schmitt trigger input with double pulse suppress-

ion allows operation in noisy environments

High peak current drive capability - 4A

High speed operation - 2MHz

•

max

•

Max lead time

500nsec

Adaptable to multiple topologies

Description

Packages

The IR1176 is a high speed CMOS controller designed

to drive N-channel power MOSFETs used as synchro-

nous rectifiers in high current, high frequency forward

converters with output voltages equal or below 5VDC.

Schmitt trigger inputs with double pulse suppression

allow the controller to operate in noisy environments.

The circuit does not require any ties to the primary

side and derives its operating power directly from

the secondary. The circuit functions by anticipating

transformer output transitions, then turns the power

MOSFETs on or off before the transitions of the trans-

former to minimize body drain diode conduction and

reduce associated losses. Turn on/off lead time can

be adjusted to accommodate a variety of power

MOSFET sizes and circuit conditions. The IR1176 also

provides gate drive overlap/dead-time control via

external components to further minimize diode con-

duction by nulling effects of secondary loop and de-

vice package inductance.

IR1176S

20 Lead Surface Mount

(SSOP-20)

IR1176SS

20 Lead SOIC (MS-013AC)

IR1176

20 Lead PDIP

(MS-001AD)

IR1176

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur.

Symbol

Definition

Min.

—

Max.

Units

V_DC

mA_DC

—

Supply voltage

Input clamp current

Power dissipation

—

+/- 10

400

—

(SSOP-20)

(SOIC)

—

(PDIP)

—

Rth

Thermal resistance (SSOP-20) junction-to-case

(SOIC) junction-to-case

—

28.5

—

(PDIP) junction-to-case

—

28.1

90.5

°C/W

Thermal resistance (SSOP-20) junction-to-ambient

(SOIC) junction-to-ambient

—

(PDIP) junction-to-ambient

—

62.4

150

Junction temperature

—

Storage temperature

-55

°C

Lead temperature (soldering, 10 seconds)

—

300

Recommended Operating Conditions

Symbol

Definition

Min.

—

Typ.

Max.

—

Units

V_DC

°C

Vdd

Supply voltage operating range

Ambient temperature

−40

250

—

Freq

Rbias

Operating frequency

—

500

—

KHz

KΩ

Required bias resistor (+/- 1%)

Voltage at UVSET pin

34.0

—

1.75

—

2.25

5.6

V_DC

Xin

Maximum voltage at X1 and X2 inputs

Capacitance at pins DTIN1 and DTIN2

—

Cd1/Cd2

—

100

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IR1176

Dynamic Electrical Characteristics

Vdd=5V, T = 25^oC, Rbias = 34.0K unless otherwise specified.

Symbol

Vdd

Definition

Min.

4.0

—

Typ.

—

Max.

Units

V_DC

Supply voltage operating range

Vdd quiescent current (x1 = x2 = 0V or 5V, Iout = 0)

Operating frequency

5.25

Iqdd

Freq

100

1.10

0.8

—

2000

1.4

1.1

—

KHz

UVSET+

UVSET-

Vxth+

Vxth-

Tadv

UVSET positive going threshold

UVSET negative going threshold

X1/X2 Input positive going threshold

X1/X2 Input negative going threshold

Externally adjustable lead time (advance)

Externally adjustable dead-time for Q1 and Q2

Q1,Q2 output sink current (Vdd=5.0V,

pulsed, 10 usec)

—

1.4

1.0

—

V_DC

nsec

—

500

—

Isink

—

(peak)

Isource

(peak)

VOH

Q1,Q2 output source current (Vdd=5.0V,

pulsed, 10 usec)

—

Q1, Q2 High level voltage (Iout = 20mA)

Q1, Q2 Low level voltage (Iout = 20mA)

Input to output delay (PLL bypassed, cross coupled

mode)

—

0.20

—

VOL

0.10

tio

nsec

Gate turn-on rise time (C1=1000pf, Vdd=5V)

Gate turn-off fall time (C1=1000pf, Vdd=5V)

Cross-over voltage (Vdd=5Vdc, DTIN shorted to

DTOUT, C1=1000pf) Fig. 3

—

nsec

V_DC

Vtr

2.5

Rbias

Vbias

Required bias resistor (1%)

—

34.0

1.25

—

KΩ

V_DC

Voltage at Rbias pin

Tjitter

Phase-lock loop output jitter

-20

—

nsec

µA_DC

V_DC

Ichgpump

Charge pump output current (at VFLTR pin)

Vchgpump Charge pump output voltage (at VFLTR pin)

1.3

—

1.5

1.7

—

Kvco_dc

PLL Vco DC gain (per design)

KHz/

Volt

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IR1176

Lead Definitions and Assignments

Symbol Description

AVDD

Power - + 5 V_DCto MOSFET drivers

Output - gate drive for Q1 power MOSFET

DTOUT1 Output - sets dead time for Q1 output - used with DTIN1

DTIN1

Input - sets dead time for Q1 - used with DTOUT1

Output - sets lead time (advance) for Q1

RADV1

VFLTR1 Output - PLL loop filter for Q1 output

RVCO1

Output - sets PLL center frequency for Q1 output

Input - transformer input for Q1

VDD

Power - +5 Vdc for internal logic

UVSET

Input - sets UVLO+

If this pin is pulled below 1.25VDC externally, then both Q1 and Q2

outputs will be at Vss (disabled)

RBIAS

AVSS

Output - connected to 34.0K +/- 1% resistor - sets operating current

Ground for MOSFET driver supply (VDD)

Input - transformer input for Q2

RVCO2

Output - sets PLL center frequency for Q2 output

VFLTR2 Output - PLL loop filter for Q2

RADV2

DTIN2

Output - sets lead time (advance) for Q2

Input - sets dead time for Q2 - used with DTOUT2

DTOUT2 Output - sets dead time for Q2 - used with DTIN2

VSS

Ground for logic supply (AVDD)

Output - gate drive for Q2 power MOSFET

1_*VDD

VSS 19

3_DTOUT2

4_DTIN2

5_RADV1

6_VFLTRI

7_RVCO1

3_DTOUT2

4_DTIN2

5_RADV1

6_VFLTRI

7_RVCO1

DTOUT1

3_DTOUT2

4_DTIN2

5_RADV1

6_VFLTRI

7_RVCO1

DTOUT1

DTIN1 17

RADV2 16

DTIN1

DTIN1 17

RADV2 16

VFLTR2

RVCO2

9_AVDD

AVSS

RBIAS

9_AVDD

AVSS

10UVSET

RBIAS 11

UVSET

10UVSET

RBIAS 11

IR1176S

(SSOP-20)

IR1176SS

SOIC (wide body)

IR1176

PDIP

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IR1176

Fig. 1 Typical application circuit when supply Vout < 5.0 V_DC

Fig. 2 Typical application circuit when supply Vout = 5.0 V_DC

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IR1176

Fig. 3 Gate drive characteristics and definitions

Phase Lock Loop Design Equations:

1 - Resistor to set VCO Ceter Frequency:

Rvco (KΩ) = [1E2 x Vchgpump(V_DC) / fvco(KHz)] x Kvco _ dc(KHz/Volt)

Example (A): Choose Vchgpump = 1.5V, desired frequency (fvco) = 300KHz

Rvco = [1E2 x 1.5 /300] x 62 Hz = 31 KΩ

2 - Small Signal gain for VCO:

Kvco_ac (KHz/Volt) = 1E2 x Kvco_dc (KHz/Volt)/Rvco(KΩ)

Example (B): Choosing same conditions as in example A:

Kvco_ac = 1E2 x 62 / 31 = 200 KHz/volt

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IR1176

3-PLLNaturalfrequency:

wn =2pfn(KHz)= Ichpump(uA) x Kvco_ac(KHz/V) / C(nF)

ChooseCfsuchthat Cf=C/16

4-PLLDampingfactorcalculations:

P = pE-3 x Rf (KOhms) x C(nF) x fn(KHz)

TypicalvalueforPis0.707.(Criticallydamped)

5-Advancetiming:

Tadv(nsec) = RADV (KOhms)*10 -+160

WhereRADVisresistancefromRADV1orRADV2toground.

ExampleC:RADV=10Kohms willresultinTadv=10*10+-160==19006nsnescec..

6-Deadtimecalculations:

Td(nsec)=0.69*Cdt(pF)*(Rdt(KΩ)+0.15) (For Vdd=5V)

Td(nsec)=0.69*Rdt(KOhms)*Cdt(pF) + 5 (For Vdd=5 V)

WhereRdtisresistancebetweenpinsDTIN1andDTOUT1orDTIN2and

DTOUT2.CdtiscapacitancefromDTIN1orDTIN2toground.

Example D: Rd=2KW and Cdt=100pF will result in Td=148.35nsec.

Fig. 4 PLL loop filter component definitions

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IR1176

Fig. 5 IR1176 Block Diagram

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IR1176

500

400

300

200

100

500

400

300

200

100

T_DT (ns)@R=1K

T_DT (ns)@R=5K

T_DT (ns)@R=10K

8K 10K

-60 -30

90 120

resistance

temperature

Response at 25^oC

T_DT vs R_DT, C = 100pF

Temperature Response

T_DT vs R_DT, C = 100pF

500

400

300

200

100

500

400

300

200

100

T_ADV (ns)R=5K

T_ADV (ns)R=10K

T_ADV (ns)R=20K

T_ADV (ns)R=45K

10K 20K 30K 40K 50K

resistance

-60 -30

120

temperature

Response at 25^oC

Temperature Response

T_ADV vs R_ADV

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IR1176

Case Outline

01-6057 00

20 Lead Surface Mount (SSOP-20)

01-3078 00 (MS013AC)

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IR1176

Case Outline

01-6070 00

01-3080 00 (MS013AC)

20 Lead SOIC

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IR1176

Case Outline

01-6069 00

20 Lead PDIP

01-3079 00 (MS001AD)

WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105

Data and specifications subject to change without notice. 1/7/2002

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