IR2101STR [INFINEON]

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型号：	IR2101STR
厂家：	Infineon
描述：	暂无描述驱动器 MOSFET驱动器驱动程序和接口接口集成电路光电二极管 PC
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Data Sheet No. PD-6.043C

IR2101

HIGH AND LOW SIDE DRIVER

Features

Product Summary

n Floating channel designed for bootstrap operation

Fully operational to +600V

Tolerant to negative transient voltage

dV/dt immune

n Gate drive supply range from 10 to 20V

n Undervoltage lockout

600V max.

100 mA / 210 mA

10 - 20V

OFFSET

I +/-

OUT

n 5V Schmitt-triggered input logic

n Matched propagation delay for both channels

n Outputs in phase with inputs

(typ.)

130 & 90 ns

30 ns

on/off

Delay Matching

Description

Packages

The IR2101 is a high voltage, high speed power

MOSFET and IGBT driver with independent high and

low side referenced output channels. Proprietary HVIC

and latch immune CMOS technologies enable rugge-

dized monolithic construction. The logic input is com-

patible with standard CMOS or LSTTL outputs. The

output drivers feature a high pulse current buffer stage

designed for minimum driver cross-conduction. The

floating channel can be used to drive an N-channel

power MOSFET or IGBT in the high side configura-

tion which operates up to 600 volts.

Typical Connection

up to 600V

V_CC

HIN

LIN

V_B

V_S

HIN

LIN

LOAD

COM

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL

B-1

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IR2101

Absolute Maximum Ratings

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur.All voltage param-

eters are absolute voltages referenced to COM.The Thermal Resistance and Power Dissipation ratings are measured

under board mounted and still air conditions.

Parameter

Definition

Value

Symbol

Min.

Max.

Units

High Side Floating Supply Voltage

High Side Floating Supply Offset Voltage

High Side Floating Output Voltage

Low Side and Logic Fixed Supply Voltage

Low Side Output Voltage

-0.3

625

- 25

V + 0.3

- 0.3

+ 0.3

-0.3

—

+ 0.3

Logic Input Voltage (HIN & LIN)

dV /dt

Allowable Offset Supply Voltage Transient

V/ns

Package Power Dissipation @ T ≤ +25°C

(8 Lead DIP)

(8 Lead SOIC)

(8 Lead DIP)

(8 Lead SOIC)

—

1.0

0.625

125

200

150

300

—

θJA

Thermal Resistance, Junction to Ambient

—

°C/W

°C

—

Junction Temperature

—

Storage Temperature

-55

—

Lead Temperature (Soldering, 10 seconds)

Recommended Operating Conditions

The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the

recommended conditions. The V offset rating is tested with all supplies biased at 15V differential.

Parameter

Definition

Value

Symbol

Min.

Max.

Units

High Side Floating Supply Absolute Voltage

High Side Floating Supply Offset Voltage

High Side Floating Output Voltage

Low Side and Logic Fixed Supply Voltage

Low Side Output Voltage

+ 10

V + 20

Note 1

600

Logic Input Voltage (HIN & LIN)

Ambient Temperature

°C

-40

125

Note 1: Logic operational for V of -5 to +600V. Logic state held for V of -5V to -V

B-2

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IR2101

Dynamic Electrical Characteristics

(V , V ) = 15V, C = 1000 pF andT = 25°C unless otherwise specified.

BIAS CC BS L A

Parameter

Definition

Value

Min. Typ. Max. Units Test Conditions

Symbol

Turn-On Propagation Delay

Turn-Off Propagation Delay

Turn-On RiseTime

—

130

200

120

V = 0V

off

V = 600V

Turn-Off FallTime

Delay Matching, HS & LSTurn-On/Off

—

Static Electrical Characteristics

(V , V ) = 15V andT = 25°C unless otherwise specified.TheV , V and I parameters are referenced to COM.

BIAS CC BS A IN TH IN

TheV and I parameters are referenced to COM and are applicable to the respective output leads:HO or LO.

Parameter

Definition

Value

Symbol

Min. Typ. Max. Units Test Conditions

Logic“1”InputVoltage

2.7

—

8.8

—

0.8

100

= 10V to 20V

Logic“0”InputVoltage

—

= 10V to 20V

High Level OutputVoltage, V

- V

—

= 0A

BIAS

Low Level OutputVoltage, V

—

Offset Supply Leakage Current

QuiescentV Supply Current

—

V =V = 600V

B S

140

—

= 0V or 5V

QBS

QuiescentV Supply Current

240

µA

QCC

Logic “1” Input Bias Current

Logic “0” Input Bias Current

= 5V

= 0V

IN+

1.0

9.8

IN-

Supply Undervoltage Positive Going

9.3

CCUV+

Threshold

Supply Undervoltage Negative Going

7.5

100

210

8.2

125

250

8.6

—

CCUV-

Threshold

Output High Short Circuit Pulsed Current

V = 0V,V =5V

O IN

O+

PW ≤10µs

Output Low Short Circuit Pulsed Current

—

=15V,V =0V

O-

O IN

PW ≤10µs

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-3

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IR2101

Functional Block Diagram

V_B

LEVEL

SHIFT

PULSE

FILTER

HIN

PULSE

GEN

V_S

DETECT

V_CC

LIN

COM

Lead Definitions

Lead

Symbol Description

HIN

Logic input for high side gate driver output (HO), in phase

Logic input for low side gate driver output (LO), in phase

High side floating supply

LIN

High side gate drive output

High side floating supply return

Low side and logic fixed supply

Low side gate drive output

COM

Low side return

Lead Assignments

8 Lead DIP

SO-8

IR2101

IR2101S

B-4

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IR2101

Device Information

Process & Design Rule

Transistor Count

Die Size

HVDCMOS 4.0 µm

168

67 X 91 X 26 (mil)

Die Outline

Thickness of Gate Oxide

Connections

First

800Å

Poly Silicon

4 µm

Material

Width

Layer

Spacing

Thickness

Material

Width

Spacing

Thickness

6 µm

5000Å

Al - Si (Si: 1.0% ±0.1%)

6 µm

Second

Layer

9 µm

20,000Å

Contact Hole Dimension

Insulation Layer

5 µm X 5 µm

PSG (SiO₂)

1.5 µm

PSG (SiO₂)

1.5 µm

Material

Thickness

Material

Passivation

Thickness

Method of Saw

Method of Die Bond

Wire Bond

Full Cut

Ablebond 84 - 1

Thermo Sonic

Au (1.0 mil / 1.3 mil)

Method

Material

Die Area

Leadframe

Lead Plating

Types

Materials

Pb : Sn (37 : 63)

8 Lead PDIP / SO-8

EME6300 / MP150 / MP190

Package

Remarks:

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-5

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IR2101

50%

HIN

LIN

HIN

LIN

off

90%

10%

Figure 1. Input/Output Timing Diagram

Figure 2. Switching Time Waveform Definitions

50%

HIN

LIN

10%

90%

Figure 3. Delay Matching Waveform Definitions

To Order

B-6

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL

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