IR2151PBF [INFINEON]
SELF-OSCILLATING HALF-BRIDGE DRIVER; 自振荡半桥驱动器
| 型号： | IR2151PBF |
| 厂家： | 
Infineon |
| 描述： | SELF-OSCILLATING HALF-BRIDGE DRIVER |
| 文件： | 总6页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Data Sheet No. PD60034-J
(NOTE: For new designs, we
IR2151
recommend IR’s new products IR2153 and IR21531)
SELF-OSCILLATING HALF-BRIDGE DRIVER
Features
Product Summary
• Floating channel designed for bootstrap operation
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
• Undervoltage lockout
• Programmable oscillator frequency
V
600V max.
50%
OFFSET
Duty Cycle
I +/-
100 mA / 210 mA
10 - 20V
O
1
V
OUT
f =
1.4 ×(RT + 75Ω)× CT
Deadtime (typ.)
1.2 µs
• Matched propagation delay for both channels
• Low side output in phase with RT
Packages
Description
The IR2151 is a high voltage, high speed, self-os-
cillating power MOSFET and IGBT driver with both
high and low side referenced output channels. Pro-
prietary HVIC and latch immune CMOS technologies
enable ruggedized monolithic construction. The front
end features a programmable oscillator which is simi-
lar to the 555 timer. The output drivers feature a high
pulse current buffer stage and an internal deadtime
designed for minimum driver cross-conduction. Propa-
gation delays for the two channels are matched to sim-
plify use in 50% duty cycle applications. The floating
channel can be used to drive an N-channel power
MOSFET or IGBT in the high side configuration that
operates off a high voltage rail up to 600 volts.
8 Lead PDIP
8 Lead SOIC
Typical Connection
up to 600V
VCC
RT
VB
HO
VS
TO
LOAD
CT
COM
LO
(Refer to Lead Assignment diagram for correct pin configuration)
1
IR2151
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
V
High side floating supply voltage
High side floating supply offset voltage
High side floating output voltage
Low side output voltage
-0.3
625
B
S
V
V
- 25
V + 0.3
B
B
V
HO
V
- 0.3
V + 0.3
B
S
V
LO
-0.3
V
+ 0.3
+ 0.3
+ 0.3
CC
CC
V
V
RT
R voltage
T
-0.3
-0.3
—
V
V
CT
C voltage
T
V
CC
I
Supply current (note 1)
25
CC
mA
V/ns
W
I
R
output current
T
-5
5
RT
dV /dt
Allowable offset supply voltage transient
—
50
1.0
s
P
Package power dissipation @ T ≤ +25°C
(8 lead DIP)
—
D
A
(8 lead SOIC)
(8 lead DIP)
(8 lead SOIC)
—
—
0.625
125
R
θJA
Thermal resistance, junction to ambient
°C/W
°C
—
—
200
150
T
Junction temperature
J
T
T
Storage temperature
-55
—
150
300
S
L
Lead temperature (soldering, 10 seconds)
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The V offset rating is tested with all supplies biased at 15V differential.
S
Symbol
Definition
High side sloating supply absolute voltage
High side floating supply offset voltage
High side floating output voltage
Low side output voltage
Min.
Max.
Units
V
B
V
S
+ 10
V + 20
S
V
S
—
600
V
V
HO
V
S
V
B
V
LO
0
V
CC
I
Supply current (note 1)
—
5
mA
°C
CC
T
Ambient temperature
-40
125
A
Note 1:
Because of the IR2151’s application specificity toward off-line supply systems, this IC contains a zener clamp
structure between the chip V and COM which has a nominal breakdown voltage of 15.6V. Therefore, the IC
CC
supply voltage is normally derived by forcing current into the supply lead (typically by means of a high value
resistor connected between the chip V and the rectified line voltage and a local decoupling capacitor from
CC
V
CC
to COM) and allowing the internal zener clamp circuit to determine the nominal supply voltage. There-
fore, this circuit should not be driven by a DC, low impedance power source of greater than V
.
CLAMP
2
IR2151
Dynamic Electrical Characteristics
V
(V , V ) = 12V, C = 1000 pF and T = 25°C unless otherwise specified.
BIAS CC BS
L
A
Symbol
Definition
Min. Typ. Max. Units Test Conditions
t
Turn-on rise time
Turn-off fall time
Deadtime
—
80
120
r
ns
t
f
—
40
70
DT
D
0.50
48
1.20 2.25
50 52
µs
%
R duty cycle
T
Static Electrical Characteristics
V
(V , V ) = 12V, C = 1000 pF, C = 1 nF and T = 25°C unless otherwise specified. The V , V and I
BIAS CC BS L T A IN TH IN
parameters are referenced to COM. The V and I parameters are referenced to COM and are applicable to the
O
O
respective output leads: HO or LO.
Symbol
Definition
Min. Typ. Max. Units Test Conditions
f
Oscillator frequency
19.4
94
14.4
7.8
3.8
—
20.0
100
15.6
8.0
4.0
20
20.6
106
16.8
8.2
4.2
50
R = 35.7 kΩ
T
OSC
kHz
R = 7.04 kΩ
T
V
V
CC
zener shunt clamp voltage
I
= 5 mA
CLAMP
CC
V
V
2/3 V threshold
CC
CT+
V
1/3 V threshold
CC
CT-
V
CTUV
C undervoltage lockout
T
2.5V<V <V
CC CCUV+
V
R
R
R
high level output voltage, V - R
—
0
100
300
50
I
= -100 µA
RT+
T
T
T
CC
T
RT
—
200
20
I
= -1 mA
RT
V
Low Level Output Voltage
—
I
=100 µA
RT-
RT
mV
—
200
0
300
100
100
100
50
I
= 1 mA
RT
V
RTUV
Undervoltage Lockout, V
- R
—
2.5V<V <V
CC CCUV+
CC
T
V
High Level Output Voltage, V
- V
—
—
I
= 0A
O
OH
BIAS
O
V
Low Level Output Voltage, V
—
—
I
= 0A
O
OL
LK
O
I
Offset Supply Leakage Current
Quiescent V Supply Current
—
—
V = V = 600V
B S
I
—
10
50
QBS
BS
µA
V
I
Quiescent V
Supply Current
—
400
0.001
8.4
950
1.0
9.2
QCC
CC
I
CT
C
T
Input Current
—
V
V
CC
Supply Undervoltage Positive Going
7.7
CCUV+
Threshold
Supply Undervoltage Negative Going
V
CCUV-
V
CC
7.4
8.1
8.9
Threshold
Supply Undervoltage Lockout Hysteresis
V
V
CC
200
100
210
500
125
250
—
—
—
mV
mA
CCUVH
I
Output High Short Circuit Pulsed Current
Output Low Short Circuit Pulsed Current
V = 0V
O
O+
I
O-
V = 15V
O
3
IR2151
Functional Block Diagram
VB
R
Q
HV
LEVEL
SHIFT
HO
R
S
PULSE
FILTER
RT
-
+
R
S
Q
Q
PULSE
GEN
DEAD
TIME
VS
R
VCC
15.6V
-
CT
+
DEAD
TIME
LO
UV
DETECT
DELAY
R
COM
Lead Definitions
Symbol Description
R
T
Oscillator timing resistor input,in phase with LO for normal IC operation
C
T
Oscillator timing capacitor input, the oscillator frequency according to the following equation:
1
f =
1.4 ×(RT + 75Ω)× CT
where 75Ω is the effective impedance of the R output stage
T
V
High side floating supply
High side gate drive output
High side floating supply return
Low side and logic fixed supply
Low side gate drive output
Low side return
B
HO
V
S
V
CC
LO
COM
Lead Assignments
8 Lead DIP
8 Lead SOIC
IR2151
IR2151S
4
IR2151
8 Lead PDIP
01-3003 01
8 Lead SOIC
01-0021 08
5
IR2151
VCLAMP
VCCUV
+
VCC
RT (HO)
RT (LO)
RT
50%
50%
t
CT
t
f
r
HO
LO
90%
90%
LO
HO
10%
10%
Figure 1. Input/Output Timing Diagram
Figure 2. Switching Time Waveform Definitions
RT
50%
50%
90%
10%
HO
LO
DT
90%
10%
Figure 3. Deadtime Waveform Definitions
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
http://www.irf.com/ Data and specifications subject to change without notice.
3/30/2001
6
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