IR2161STRPBF [INFINEON]
HALOGEN CONVERTOR CONTROL IC;
| 型号： | IR2161STRPBF |
| 厂家： | 
Infineon |
| 描述： | HALOGEN CONVERTOR CONTROL IC |
| 文件： | 总20页 (文件大小：466K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No. PD60219 rev C
IR2161(S) & (PbF)
HALOGEN CONVERTOR CONTROL IC
Packages
Features
Intelligent half-bridge driver
•
Auto Resetting Short Circuit Protection
Auto Resetting Overload Protection
•
•
• Externally Triggerable Latching Shutdown
• Latching Overtemperature Protection
• Frequency Modulation dither (for lower EMI)
• Micropower Startup (<300 μA)
8-Lead SOIC
IR2161S
8-Lead PDIP
IR2161
• Phase Cut dimmable for leading / trailing edge
• Output Voltage Shift Compensation.
• Real Softstart
• Adaptive Dead Time
• Small 8 Pin DIP/SOIC Package
• Also available LEAD-FREE (PbF)
Description
The IR2161 is a dedicated Intelligent Half bridge Driver IC for a Halogen convertor (electronic transformer). It
includes all necessary protection features and also allows the Convertor to be dimmed externally with a
standard phase cut dimmer with both leading or trailing edge types. This IC provides the advantage of reduced
thermal stress in the lamp due to softstart. There is also compensation of the output voltage for load regulation.
It enables the convertor to operate with extremely low harmonic distortion over the full range of loads. The
IR2161 includes adaptive deadtime to allow cool running MOSFETs and improves the EMI behaviour due to
frequency modulation (dither). All the features are integrated in a small 8 pin DIP/SOIC package to allow for a
size reduction in the next generation of convertors.
Typical Connections
RD
C1
RS
R1
DCP1
CD
DB
DCP2
DS
Q1
D1
D2
CSNUB
VCC
VB
HO
VS
LO
LF
1
2
3
4
8
7
6
5
CVCC1
COM
CSD
CS
CVCC2
T1
AC LINE
INPUT
CB
CLF
VZ
C3
C4
Q2
D3
D4
R2
C2
RL
12VAC
OUTPUT
CSD
CCS
RCS
Note: Throughout this data sheet convertor is spelled in accordance with standard IEC 61047 DC or AC supplied convertors
for filament lamps Performance requirements.
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IR2161( )&(PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters
are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power
dissipation ratings are measured under board mounted and still air conditions.
Symbol Definition
Min.
Max.
Units
V
High side floating supply voltage
High side floating supply offset voltage
High side floating output voltage
Low side output voltage
-0.3
625
B
S
V
V
- 25
V
V
+ 0.3
+ 0.3
B
S
B
B
V
V
HO
V
- 0.3
V
LO
-0.3
V
+ 0.3
CC
IO
Maximum allowable output current (HO,LO) due to external
power transistor miller effect
CSD pin voltage
-500
500
MAX
mA
V
V
-0.3
-0.3
-5
V
V
+ 0.3
+ 0.3
CSDMAX
CC
V
Current sense pin voltage
CS
CC
I
Current sense pin current
5
CS
mA
I
Supply current (Note 1)
-20
-50
—
20
50
CC
dV/dt
Allowable offset voltage slew rate
V/ns
P
Maximum power dissipation @ T ≤ +25°C (8 Lead DIP)
1
D
A
W
PD = (T
-T )/Rth
JA
(8 Lead SOIC)
(8 Lead DIP)
(8 Lead SOIC)
—
0.625
125
200
150
150
300
JMAX
A
Rth
Thermal resistance, junction to ambient
—
JA
°C/W
—
T
T
T
Junction temperature
-55
-55
—
J
Storage temperature
°C
S
L
Lead temperature (soldering, 10 seconds)
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions.
Symbol Definition
Min.
Max.
Units
V
High side floating supply voltage
Minimum required VBS voltage for proper HO functionality
Steady state high-side floating supply offset voltage
Supply voltage
V
- 0.7
V
BS
CC
CLAMP
—
V
4.3
-1
BSMIN
V
V
600
S
V
CC
V
V
CCUV+
CLAMP
I
Supply current
(Note 2)
47
10
mA
nF
mA
°C
CC
C
CSD pin external capacitor
—
1
SD
I
Current sense pin current
-1
CS
T
Junction temperature
-25
125
J
Note 1:
Note 2:
This IC contains a zener clamp structure between the chip V
and COM which has a nominal breakdown
CC
voltage of 15.6V. Please note that this supply pin should not be driven by a DC, low impedance power source
greater than the V specified in the Electrical Characteristics section.
CLAMP
Enough current should be supplied into the V
pin to keep the internal 15.6V zener clamp diode on this pin
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CC
regulating its voltage, V
.
CLAMP
2
IR2161(S)&(PbF)
Electrical Characteristics
V
CC
= V = V
= 14V, +/- 0.25V, VCSD = 5.0V, C
C
= 1000 pF, and T = 25°C unless otherwise specified.
BS
BIAS
LO = HO A
Supply Characteristics
Symbol Definition
Min. Typ.
Max. Units Test Conditions
V
V
CC
V
CC
V
CC
supply undervoltage positive going
threshold
supply undervoltage negative going
threshold
CCUV+
11.5
12.1
10.5
12.7
11
V
rising from 0V
CC
CC
V
CCUV-
V
10
V
falling from 14V
V
supply softstart reset negative going
CCUVL-
threshold
—
—
—
250
1.4
5.5
300
2.0
V
- V
(-2V)
CC
CCUV-
μA
I
UVLO mode quiescent current
Fault-mode quiescent current
VCC current (low frequency)
VCC current (high frequency)
V
= 11V
CC
QCCUV
I
—
CS=8V, VCSD=0V
VCC=14V,VCSD=5.2V
VCC=14V,VCSD=0V
CCFLT
I
—
2.0
3.0
CC
mA
LF
I
—
4.0
7.0
CC
HF
V
V
CC
zener clamp voltage
14.5
15.4
16.5
V
I
= 5mA
CC
CLAMP
Floating Supply Characteristics
Symbol Definition
Min. Typ.
Max. Units Test Conditions
V
Minimum V to start oscillation at HO
3.0
—
3.6
3.0
4.3
—
V
BSMIN
BSHF
BS
I
V
high frequency supply current
VCC=14V,VBS=14V,
VCSD=0V
BS
mA
I
V
low frequency supply current
BS
—
—
0.8
—
—
VCC=14V,VBS=14V,
VCSD=5.2V
BSLF
I
Offset supply leakage current
50
μA
V = V = 600V
B S
LEAK
Voltage Compensation Characteristics (Run Mode)
Symbol Definition
Min. Typ.
Max. Units Test Conditions
V
V
Min CSD voltage (in Run Mode)
Max CSD voltage (in Run Mode)
—
—
0
—
—
V
V
VCS = 0V
CSD (min)
CSD (max)
5.5
VCS = 0.4V
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IR2161( )&(PbF)
Electrical Characteristics (cont’d)
V
= V = V
= 14V, +/- 0.25V, VCSD = 5.0V, C
C
= 1000 pF, and T = 25°C unless otherwise specified.
CC
BS
BIAS
LO = HO A
Shutdown Circuit Characteristics
Symbol Definition
Min. Typ.
Max. Units Test Conditions
V
Overload threshold (CS PID)
CSD short circuit threshold (CS PID)
CSD overload charging current
CSD short circuit charging current
CSD shutdown reset current
Latched shutdown threshold
Latched shutdown delay
0.47
0.56
1.2
9
0.64
CSOL
V
V
1
6
1.4
CSSC
I
12
120
VCS=0.8V,VCSD=7V
VCS=1.5V,VCSD=7V
VCSD=14V
OL
uA
I
75
0.1
100
0.7
9
SC
I
RESET
V
V
CSLATCH
CSLATCH
T
1
μsec
VCS>VCSLATCH
VCS>VCSOL
V
Begin fault timing
5
CSDOL
V
Positive going threshold for oscillator
shutdown
12
VCS > VCSOL
CSDSD
V
Negative going threshold for oscillator restart
2.4
VCSDRS
Thermal Shutdown Characteristics
Symbol Definition
Min. Typ.
Max.
Units Test Conditions
oC
T
Latched over temperature limit
135
SD
Oscillator Characteristics
Symbol Definition
Min. Typ.
Max.
Units Test Conditions
f
Minimum oscillator frequency
34
VCSD = 5.3V
(min)
kHz
f
Maximum oscillator frequency in RUN mode
Oscillator duty cycle
Maximum LO output deadtime
(run mode default)
70
50
VCSD = 0V
(max)
%
D
DT
LO(max)
1.0
μsec
no reset from ADT
DT
Maximum HO output deadtime
(run mode default)
1.0
HO(max)
Adaptive Dead-Time System Characteristics
Symbol Definition
Min. Typ.
Max.
Units Test Conditions
Minimum propagation
delay from ADT to
output drivers
DT
DT
Minimum LO output deadtime
Minimum HO output deadtime
700
700
LO(min)
nsec
HO(min)
4
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IR2161(S)&(PbF)
Electrical Characteristics (cont.)
V
CC
= V = V
= 14V, +/- 0.25V, VCSD = 5.0V, C
C
= 1000 pF, and T = 25°C unless otherwise specified.
BS
BIAS
LO = HO
A
Soft Start Characteristics
Symbol Definition
Min.
Typ. Max. Units Test Conditions
I
Soft start CSD charge current
Soft start frequency
0.5
mA
SS
f
115
kHz
VCC>VCCUV+
SS
Gate Driver Output Characteristics
Symbol Definition
Min.
Typ. Max. Units Test Conditions
V
LO voltage when LO is low
HO voltage when HO is low
LO voltage when LO is high
HO voltage when HO is high
—
—
—
—
COM
COM
VCC
VCC
—
—
—
—
LO=LOW
V
HO=LOW
V
LO=HIGH
V
HO=HIGH
t
Turn-on rise time
—
—
—
—
110
60
250
140
—
RISE
ns
C =C =1nF
HO LO
t
Turn-off fall time
FALL
IO+
HO, LO source current
HO, LO sink current
200
300
mA
IO-
—
Lead Assignments
Lead Definitions
Symbol Description
V
Supply voltage
CC
1
2
3
4
8
7
6
5
VB
HO
VS
LO
VCC
COM
CSD
CS
COM
CSD
CS
IC power and signal ground
Shutdown timing and compensation capacitor
Current sensing input
LO
Low-side gate driver output
V
High-side floating return
S
HO
High side gate driver output
V
B
High side gate driver floating supply
* Recommended value for CSD is 100nF (all performance data relates to this value)
NOTE: The recommended value for RL is 1K Ohm and CCS is 1nF.
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IR2161( )&(PbF)
Power Turned On
VCC < 5.5V (VCCUVL-)
(Power Turned Off)
VCC < 5.5V (VCCUVL-)
(Power Turned Off)
UVLO Mode
1
/
-Bridge Off
2
IQCC
≅
μA
300
Oscillator Off
CSD = 0V
VCC > 12.1V(VCCUV+)
o
TJ
(T
)
<135 C
Oscillator On
jmax
STANDBY Mode
FAULT Mode
1
1
/
/
-Bridge Off
-Bridge Off
2
VCC > 12.1V (VCCUV+)
2
≅
o
IQCC
μ
Oscillator Off
A
300
TJ
(T
)
<135 C
jmax
Oscillator Off
Oscillator On
VCC < 10.5V (VCCUV-
)
(Phase Cut Dimming)
SOFTSTART
Fault Detected
(Vpk at VCS > 0.56V)(VCSOL
Mode
)
1
/
2 - Bridge On
o
TJ
(T
)
<135 C
jmax
Initial frequency 130kHz
CSD charged from Isource
Frequency ramps down to
f(min)
(Over-Temperature)
VCSD > 5.2V
(End of SOFTSTART Mode)
CSD switched to Comp function
Fault Detected
(Vpk at VCS > 9V)
(VCSLATCH)
VCC < 10.5V (VCCUV-
(Phase Cut Dimming)
)
<135oC
TJ
(T
)
jmax
RUN Mode
(Over-Temperature)
Voltage compensation active
Auto-Restart Timeout
CSD switched to
run mode
(VCSD < 2.4V) (VCSDRS)
CSD varies between
VCSD (min) = 0 for f(min)
CSD switched to run mode
to VCSD(max) = 5.5V for f(max)
Fault Detected (Vpk at VCS > 0.56V (VCSOL ))
CSD switched to Shutdown Circuit
CSD discharged to 0V
Frequency defaults to f(min)
Fault Timing Mode
SHUTDOWN Mode
1
/
- Bridge On
2
Fault Confirmed
(VCSD > 12V)
(VCSDSD)
Fault Removed
1
Delay
CSD is slowly
discharged to 2.4V
(VCSDRS)
/
CSD initialized to 5V (VCSDOL)
VCS >0.56V(VCSOL)=Overload:CSD slow charge
VCS > 1.2V (VCSSC) = Short Circuit : CSD
fast charge
-Bridge Off
2
(Vpk at VCS < 0.5V)
(VCSOL
)
CSD is slowly discharged
All values are typical
o
NOTE: If the IR2161 die temperature exceeds 135 at any time the system will enter FAULT Mode. At a typical frequency of
40kHz, the die temperature is approximately 12oC above the ambient air temperature
6
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IR2161(S)&(PbF)
Block Diagram
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IR2161( )&(PbF)
be rated at 1.3W). The resistor RD in series with CD is
necessary if the convertor is required to operate from a
triac based (leading edge) phase cut dimmer. When the
triac fires at a point during the mains half-cycle the high dv/
dt allows a large current to flow through this path to instantly
charge CVCC to the maximum Vcc voltage.
Halogen Convertor Controller
Functional Description
Under-voltage Lock-Out Mode (UVLO)
The under-voltage lockout mode (UVLO) is defined as the
state the IC is in when VCC is below the turn-on threshold.
To identify the different modes of operation, refer to the
State Diagram shown on page 7 of this data sheet. The
IR2161 under voltage lock-out is designed to maintain an
ultra low supply current of less than 300uA, and to guaran-
tee the IC is fully functional before the high and low side
output drivers are activated. Figure 1 shows a simple VCC
supply arrangement that will work effectively, also when
the convertor is being dimmed from a conventional triac
based wall dimmer
The external zener (DZ) will prevent possible damage to
the IC by shunting excess current to COM.
Once the capacitor voltage on VCC reaches the start-up
threshold the IC turns on and HO and LO begin to
oscillate.
The supply resistor (RS) and RD/CD must be selected such
that enough supply current is available over all ballast
operating conditions. A bootstrap diode (DB) and supply
capacitor (CB) comprise the supply voltage for the high
side driver circuitry. To guarantee that the high-side supply
is charged up before the first pulse on pin HO, the first
pulse from the output drivers comes from the LO pin. During
under voltage lock-out mode, the high and low-side driver
outputs HO and LO are both low.
RD
RS
CD
BR
DS
DB
M1
M2
VCC
VB
HO
VS
LO
1
2
3
4
8
LF
CVCC
COM
CSD
CS
7
6
5
CB
CF
DZ
Soft Start Mode
RL
CSD
CCS
OUTPUT
RCS
The soft start mode is defined as the state the IC is in at
system switch on when the lamp filament is cold. As with
any type of filament lamp, the Dichroic Halogen lamp has a
positive temperature coefficient of resistance such that the
cold resistance (at switch on when the lamp has been off
long enough to cool) is much lower than the hot resistance
when the lamp is running. This normally results in a high
inrush current occurring at switch on. Under worst-case
conditions this could potentially trigger the convertors shut
down circuit. To overcome this problem the IR2161
incorporates the soft start function.
Figure 1, Halogen Convertor.
The start-up capacitor (CVCC) is charged by current through
supply resistor (RS) minus the start-up current drawn by
the IC. This resistor is chosen to provide sufficient current
to supply the IR2161 from the DC bus. In a Halogen conver-
tor it is important to consider that the DC bus is completely
unsmoothed and has a full wave rectified shape. CVCC should
be large enough to hold the voltage at Vcc above the UVLO
threshold for one half cycle of the line voltage as it will only
be charged at the peak. A charge pump consisting of two
diodes (DCP1 and DCP2) connected to CSNUB is recom-
mended to supply VCC as this allows RS to be a large value
since it is only needed at startup. IF RS is required to supply
the circuit without a charge pump it needs to be a relatively
low value and consequently dissipates 1 to 2W, which is
undesirable.
When the IC starts oscillating the frequency is initially very
high (about 130kHz). This causes the output voltage of the
convertor to be lower since the HF transformer in the system
has a fixed primary leakage inductance that will present a
higher impedance at higher frequency and thus allowing
less AC voltage to appear across the primary. The reduced
output voltage will naturally result in a reduced current in
the lamp which eases the inrush current thus avoiding
tripping of the shutdown circuit and will ease the stress on
the lamp filament as well as reducing the current in the half
bridge MOSFETs (M1 and M2).
An external 16V zener diode DZ has been added to avoid
the need for the internal zener to dissipate power (it should
The frequency sweeps down gradually from 130kHz to the
8
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IR2161(S)&(PbF)
minimum frequency over a period of around 1s (assuming
CSD=100nF). During this time the external capacitor at the
CSD pin charges from 0V to 5V, controlling the oscillator
frequency through the internal voltage controlled oscillator
(VCO). The value of CSD will determine the duration of the
soft start sweep. However, since it also governs the shut
down circuit delays, the value should be kept at 100nF to
achieve the datasheet operation.
ISS
Set Oscillator
CSD
Figure 4, Cold Lamp Inrush Current with Soft Start.
Range
5V
Run Mode (Voltage Compensation)
Figure 2, Halogen Convertor.
When soft start is completed the system switches over to
compensation mode. This function provides some regula-
tion of the output voltage of the convertor from minimum to
maximum load. In this type of system it is desirable that the
voltage supplied to the lamp does not exceed a particular
limit. If the lamp voltage becomes too high the temperature
of the filament runs too high and the life of the lamp is
significantly reduced. The problem is that the output trans-
former is never perfectly coupled so there will always be a
degree of load regulation.
It can be seen from Figure 2, that at switch on, the CSD
capacitor is internally switched to the soft start circuit input.
A current source charges CSD linearly to 5V over a period
of 0.5s at which time the comparator output goes high. The
PMOS switch opens and the ISS current source is
disconnected from CSD. The comparator latches high at this
point and this causes the oscillator range to change and the
CSD capacitor to be disconnected from the soft start circuit
and connected to the voltage compensation circuit. The
latching comparator has a built in delay of at least 20uS in
order to prevent false triggering caused by transients.
The transformer has to be designed such that the lamp
voltage at maximum load is sufficiently high to ensure
adequate light output.
At minimum load the voltage will consequently be higher
and is likely to exceed the maximum desired lamp voltage.
In the widely used self-oscillating system based around
bipolar power transistors, there is some frequency change
(increasing the frequency reduces the output voltage)
depending on the load that helps to compensate for this,
although this is non-linear and depends on many parameters
in the circuit and so is not easy to predict.
The IR2161 based system includes a function that monitors
the load current through the current sense resistor (RCS).
The peak current is detected and amplified within the IC
then appears at the CSD pin during run mode. The voltage
Figure 3, Typical Cold Lamp Inrush Current.
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IR2161( )&(PbF)
across the CSD capacitor will vary from 0V if there is no
load to approximately 5V at maximum load.
This is provided that the correct value of current sense
resistor has been selected for the maximum rated load and
line voltage supply of the convertor. This should be 0.33
Ohm (0.5W) for a 100W system running from a 220-240V
AC line. (It should be noted that the RCS resistor value is
also critical for setting the limits for the shut down circuit)
In RUN mode the oscillator frequency will vary from
approximately 34kHz when VCSD is 5V (maximum load) to
70kHz when VCSD is 0V (no load). The result of this is that
if a lighter load, such as a single 35W lamp, is connected to
a 100W convertor, the frequency will shift upwards so that
the output voltage falls below the maximum that is desirable
for the lamp. This provides sufficient compensation for the
load to ensure that the lamp voltage will always be within
acceptable limits but does not require a complicated regulation
scheme involving feedback from the output.
Figure 6, VS voltage and CSD voltage.
In the above trace it can be seen that a leading edge phase
cut (triac) dimmer is connected at close to maximum
brightness. There is a short delay at the beginning of each
half cycle before the AC line voltage is switched to the
convertor. Dimming increases the ripple in the CSD voltage
and gives more modulation. This is an inherent effect that
causes no system problems.
An additional internal current source has been included to
discharge the external capacitor. This will provide
approximately 10% ripple at twice the line frequency if CSD
is 100nF.
The advantage of this is that during the line voltage half
cycle the oscillator frequency will vary by several kHz thus
spreading the EMI conducted and radiated emissions over
a range of frequencies and avoiding high amplitude peaks
at particular frequencies. In this way the filter components
used may be similar to those used in a common bipolar self-
The startup sequence of the CSD pin can be seen from the
point where VCC increases above the UVLO+ threshold.
AV > 13
CS
CSD
150K
12K
Figure 7, Startup sequence of CSD.
This trace shows that after the CSD voltage has ramped up
through soft start, the system switches over to voltage com-
pensation mode and a ripple exists which allows the fre-
quency modulation (or dither) to occur. In this case the
oscillating system.
Figure 5, Voltage Compensation Circuit
10
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IR2161(S)&(PbF)
convertor is close to maximum load. If the load is reduced,
the average level at which the ripple occurs (i.e. the DC
component) will be at a lower level.
S
R
Q
Q
I_SC
I_OL
12V
CS
Enable Outputs
Switch
1.2V
2.5V
Shutdown Function
Shut Down Circuit
CSD
0.54V
The IR2161 contains a dual mode auto-resetting shutdown
circuit that detects both a short circuit or overload condition
in the convertor. The load current detected at the CS pin is
used to sense these conditions. If the output of the convertor
is short-circuited, a very high current will flow in the half
bridge and the system must shut down within a few mains
half cycles, otherwise the MOSFETs will rapidly be destroyed
due to excessive junction temperature. The internal CS pin
Overload Function
I_RESET
4V
Figure 8, Shut Down Circuit.
The oscillator operates at minimum frequency when the
CSD capacitor is required for shutdown circuit timing.
has an internal threshold (V
threshold so that if the voltage exceeds this level for more
than 50mS, the system will shut down.
). There also exists a lower
CSSC
During soft start or run mode, if the 0.5V threshold (V
)
CSOL
is exceeded the IR2161 charges CSD rapidly to approxi-
mately 5V (V ).
CSDOL
A delay is included to prevent false tripping either due to
lamp inrush current at switch on (this current is still higher
than normal with the soft start operation) or transient
currents that may occur if an external triac based phase
cut dimmer is being used.
When the voltage at the CS input is greater than 0.5V, the
CSD capacitor is charged by current source I and when
OL
the short circuit threshold of 1.2V is exceeded it is charged
by I as well. If 1.2V is exceeded CSD will charge from 5V
SC
(V
) to 12V (V
CSDOL
), in approximately 50ms. When
CSDSD
0.5V is exceeded but 1.2V is not, CSD charges from 5V
(V ) to 12V (V ) in approximately 0.5s. It should
be remembered that, the timing accounts for the fact that
high frequency pulses with approximately 50% duty cycle
and a sinusoidal envelope appear at the CS pin.
There also exists a lower threshold (V
), which has a
CSOL
CSDOL
CSDSD
much longer delay before it shuts down the system. This
provides the overload protection if an excessive number of
lamps is connected to the output or the output is short-
circuited at the end of a length of cable that has sufficient
resistance to prevent the current from being large enough
to trip the short circuit protection. Also under this condition
there is an excessive current in the half bridge that is
sufficient to cause heating and eventual failure but over a
longer period of time. The threshold for overload shutdown
is approximately 50% above maximum load with a delay of
approximately 0.5s. These timings are based on a current
waveform that has a sinusoidal envelope and a high
frequency square wave component with 50% duty cycle.
The values of I
and I take into account that only at the
OL
SC
peak of the mains will the comparator outputs go high and
effectively the capacitor will be charged in steps each line
half cycle. Once VCSD reaches 12V (V
), VCSD
CSDSD
discharges down to 2.4V (V
) and the system starts
CSDRS
up again. If the fault mode is still present, CSD starts
charging again.
If a fault is detected but goes away before CSD reaches
12V (V
), then CSD will discharge to 2.4V (V
)
CSDSD
CSDRS
Both shutdown modes are auto resetting, which allows the
oscillator to start again approximately 1.5s after shutting
down. This is so that if the fault condition is removed the
system can start operating normally again without the line
voltage having to be switched off and back on again. It also
provides a good indication of overload to the end user as all
the lamps connected to the system will flash on and off
continuously if too many are connected.
and then the system will revert to compensation mode
without interruption of the output.
Following a shutdown, when the system starts up again
after the delay, the CSD capacitor will be internally switched
back to the voltage compensation circuit. However, if the
fault is still present the system will switch CSD back to the
shutdown circuit again.
The shut down circuit also uses the external CSD capacitor for
its timing functions. When the 0.5V threshold (V ) is ex-
CSOL
ceeded at CS the CSD is internally disconnected from the voltage
compensation circuit and connected to the shutdown circuit.
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11
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IR2161( )&(PbF)
In addition, any time Vcs exceeds VCSLATCH
(approximately half Vcc), this latching shutdown function
will be triggered and the system will remain in FAULT mode
until VCC is re-cycled.
The IR2161 also includes over temperature shutdown, which
latches the convertor off when the die temperature of the
IC exceeds 130-135°C. Experimental measurements reveal
that the die temperature will be no more than 20°C above
the ambient temperature at all operating frequencies inside
the convertor.
Calculating Rcs
The value of the current sense resistor Rcs is critical to
achieve correct operation in the IR2161 based Halogen
convertor.
Figure 9, Short Circuit Output Current.
DC Bus
Voltage
VS
VCSpk
VCS
1/2 DC Bus
Voltage
LOAD
RCS
Figure 10, Overload Output Current.
In figures 9 and 10, trace (1) shows the half bridge
oscillations during both types of fault mode and trace (2)
shows the charging and discharging of the CSD capacitor.
Figure 11, Calculating RCS
Ignoring the output transformer we can assume for this
calculation that the load is connected from the half bridge to
the mid point of the two output capacitors and that the
voltage at this point will be half the DC bus voltage. The
RMS voltage of the DC bus is the same as that of the AC line
so we can see that the RMS voltage across the load shown
in Figure 8, will be half the RMS voltage of the line. The load
is the maximum rated load of the convertor. The current in
Rcs will be half the load current given by :
The IR2161 can also be externally shut off by applying a
voltage above 9V (VCSLATCH) to the CS pin. This will
cause the system to go directly to a latched fault mode,
after a delay of approximately 1uS to avoid the possibility of
false tripping caused by transients. To restart the system, it
is necessary to cycle Vcc off and on.
12
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IR2161(S)&(PbF)
In this case :
P
LOAD
2
ICS (RMS)
=
100
230
⎛
⎜
⎞
VAC
×0.33 = 0.062W
⎟
⎠
⎝
Since the load is resistive the current waveform will have a
sinusoidal envelope and so the peak can be easily deter-
mined taking into account that the current has a high fre-
quency component with an approximate 50% duty cycle:
It is important to bear in mind that the resistor must be rated
to handle this current in a high ambient temperature.
IMPORTANT NOTE
The filter resistor RL should be 1K, which is needed to
protect the CS input from negative going transients. CCS
should be 1nF and is also necessary to filter out switching
transients that can impair the operation of the shutdown
circuit.
ICS (PK) = 2 2 × ICS(RMS )
Therefore:
VCS (PK ) = ICS (PK ) × RCS
Adaptive Dead Time
For correct operation at maximum load the peak voltage
should be 0.4V.
Because of the fact that the DC bus voltage varies during
the mains half cycle, the dead time may need to vary in
order to achieve soft switching. The IR2161 has an adap-
tive dead time circuit (ADT) that detects the point at which
the voltage at the half bridge slews to 0V (COM) and sets
the LO output high at this point. There is an internal sample
and hold system that allows approximately the same delay
to be used to set HO high after LO has gone low. This
reacts on a cycle-by-cycle basis of the oscillator and there-
fore will adjust the dead time as necessary regardless of
external conditions.
The calculation can be simplified by combining the formulae,
0.4⋅VCS
RCS =
2⋅ 2 ⋅P
LOAD
Which can be simplified to:
VAC
RCS = 0.141⋅
P
LOAD
Example
For a 100W convertor working from a 230VAC supply the
current sense resistor would need to be :
0.141×230
= 0.324Ω
100
The nearest preferred value to this would be 0.33 Ohms.
The power dissipation in Rcs should also be considered
and is given by :
2
⎛
⎜
⎞
⎟
P
LOAD
Figure 12, ADT when VS slews from VBUS to COM
P =
× RCS
CS
⎜
⎝
⎟
⎠
VAC
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13
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IR2161( )&(PbF)
of the power MOSFETs in the half-bridge will be at a
maximum. At lighter loads there may be hard switching if
the VS voltage is unable to slew all the way or it slews so
rapidly that the voltage begins to turn around again before
the IR2161 is able to switch on the relevant MOSFET in the
half bridge.
Such a situation is not desirable but may be acceptable at
lighter loads where the conduction losses are small.
With correct optimization of the output transformer and
surrounding circuit it is possible to achieve a design that
will not hard switch from 20% to 100% of the maximum
rated load of the system.
This system avoids the need for an external resistor to
program the dead time and contributes to the multi func-
tional nature of the CSD pin to the IR2161 being realized
with only 8 external pins
Figure 12, ADT when VS slews from COM to VBUS
In any design when there is no load at the output, the VS
voltage will not slew and obviously the ADT circuit is not
able to function in this condition. In this case the dead time
will default to approximately 1μS, the maximum allowed by
the IC and there will be hard switching.
The above waveforms are typical, showing the operation
of the ADT circuit in either direction. In this case the design
could be optimized further by increasing the snubber ca-
pacitor to slightly increase the slew time, in order to ac-
count for the propagation delays in the system. Alterna-
tively an output transformer with a greater leakage induc-
tance can extend the period before the VS voltage turns
around and starts to go back the other way again.
Although this will inevitably lead to some switching losses,
there are no conduction losses so the temperature rise of
the half bridge MOSFETs should not create a problem in this
case.
The designer does not need to take into account parasitic
capacitances in the MOSFETs or leakage inductance in the Dimming
output transformer and fix the dead time accordingly.
Almost any Halogen convertor available can be dimmed by
The system can operate reliably down to dead times in the
order of 300nS, which should be low enough to
accommodate the output transformer leakage inductance
and parasitic MOSFET capacitances of a practical Halogen
convertor.
an external phase cut dimmer that operates in trailing edge
mode. This means that at the beginning of the line voltage
half cycle, the switch inside the dimmer is closed and mains
voltage is supplied to the convertor allowing the convertor
to operate normally. At some point during the half cycle, the
switch inside the dimmer is opened and voltage is no longer
applied. The DC bus inside the convertor almost immediately
drops to 0V and the output is no longer present. In this way
bursts of high frequency output voltage are applied to the
lamp. The RMS voltage across the lamp will naturally vary
depending on the phase angle at which the dimmer switch
switches off. In this way the lamp brightness may easily
be varied from zero to maximum output.
The slew rate can easily be increased, if necessary, by
adding a small snubber capacitor across the primary of the
transformer if necessary. However, should the snubber
capacitor be too large, it will prevent the VS voltage from
slewing all the way to the opposite rail. Consequently the
ADT function will be unable to operate, causing the IR2161
to revert to the default dead time of 1μS. Snubber capacitors
would normally be in the order of hundreds of pF.
When designing a halogen convertor it is desirable to optimize
the system at maximum load, where the conduction losses
14
www.irf.com
IR2161(S)&(PbF)
DC BUS VOLTAGE
LAMP VOLTAGE
DC BUS VOLTAGE
LAMP VOLTAGE
Figure 13, Trailing Edge Dimming
Figure 14, Leading Edge Dimming
Trailing edge dimmers are less common however than leading
edge dimmers. This is because they are more expensive to
make and need to incorporate a pair of MOSFETs or IGBTs
whereas a leading edge dimmer is based around a single
triac.
Conversely many Halogen convertors are not able to oper-
ate with leading edge dimmers because of the fact that
they are based around a triac. It is possible, however, to
design a Halogen convertor that will work effectively with
a triac based dimmer by designing the input filter compo-
nents correctly ensuring that at the firing point of the triac
the oscillator can start up rapidly. In the IR2161 based sys-
tem this is easy to achieve through the addition of RD and
CD, which conduct a large current to VCC due to the high
dv/dt that occurs when the triac fires. At the same time, the
bus voltage rises rapidly from zero to the AC line voltage. If
holding current. If the load is purely resistive (as in a fila-
ment lamp directly connected to the dimmer) this will natu-
rally happen at the end of the line voltage half cycle as the
current has to fall to zero. In a Halogen convertor it is nec-
essary to place a capacitor and inductor at the AC input to
comply with regulations regarding EMI conducted emis-
sions. This means that when the line voltage falls to zero
there could still be some current flowing that is enough to
keep the triac switched on and so the next cycle will follow
through and not be phase cut as required. This can happen
intermittently resulting in flickering of the lamps. The way to
avoid the problem is to ensure that the product has the
smallest possible filter capacitor CCS and to state a mini-
mum load for the convertor. This would be typically one
third of the maximum load to avoid problems of this kind.
the VCC voltage falls below V
during the time when
CCUV-
the triac in the dimmer is off, the soft start will not be initi-
ated because the soft start circuit is not reset until VCC
drops approxmately 2V below V
. This takes some
CCUV-
time as the VCC capacitor discharges very slowly during
UVLO micro-power operation. The intermediate period is
referred to as Standby mode.
During dimming the voltage compensation circuit will cause
a frequency shift upward at angles above 90° because the
peak voltage at CS will be reduced (see figure 14). This will
result in a reduction of voltage at CSD and thus an increase
in frequency. However this will not have a noticeable effect
on the light output.
The problem associated with operation of Halogen conver-
tors with triac dimmers is due to the fact that after a triac
has been fired it will conduct until the current falls below its
Figure 15, Half Bridge voltage and current during dimming
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15
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IR2161( )&(PbF)
15
5
4
3
2
1
0
VCCUV+
12
ICCHF
VCCUV-
9
6
3
0
ICCLF
IQCCFLT
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Graph : VCCUV+/- vs TEMP (IR2161)
Graph : IQCC vs TEMP (IR2161)
20
6
5
4
3
2
1
0
VCCLAMP_25ma
VCCLAMP_5ma
VCSDMAX
15
10
5
VCSDMIN
0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Graph : VCCLAMP_5_25ma vs TEMP (IR2161)
16
VCSDMIN,MAX vs TEMP (IR2161)
www.irf.com
IR2161(S)&(PbF)
2
1.5
1
20
15
10
5
VCS_SC
VCS_OL
I_OL
0.5
0
I_RESET
0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
I_RESET, I_OL vs TEMP (IR2161)
VCS_OL, VCS_SC vs TEMP (IR2161)
100
90
12
9
VCSD_SD
I_SC
6
80
VCSD_OL
VCSD_RS
3
70
0
60
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Graph : VCSDSD,OL,RS vs TEMP (IR2161)
I_SC vs TEMP (IR2161)
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17
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IR2161( )&(PbF)
175
150
1
0.8
0.6
0.4
0.2
0
FSS
125
100
75
FRUN
50
25
FMIN
0
-25
0
25
50
75
100
125
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Frequency vs TEMP (IR2161)
Graph : Iss (uA) vs TEMP (IR2161)
18
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IR2161(S)&(PbF)
Case outlines
01-6014
01-3003 01 (MS-001AB)
IR2161 8-Lead PDIP
01-6027
01-0021 11 (MS-012AA)
IR2161S 8-Lead SOIC
www.irf.com
19
S
IR2161( )&(PbF)
LEADFREE PART MARKING INFORMATION
Part number
Date code
IRxxxxxx
YWW?
IR logo
?XXXX
Pin 1
Identifier
Lot Code
(Prod mode - 4 digit SPN code)
?
MARKING CODE
P
Lead Free Released
Non-Lead Free
Released
Assembly site code
Per SCOP 200-002
ORDER INFORMATION
Leadfree Part
Basic Part (Non-Lead Free)
8-Lead PDIP IR2161 order IR2161PbF
8-Lead PDIP IR2161 order IR2161
8-Lead SOIC IR2161S order IR2161SPbF
8-Lead SOIC IR2161S order IR2161S
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
This product has been qualified per industrial level MSL-2, Lead-free available
Data and specifications subject to change without notice. 9/19/2005
20
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