IR2181PBF [INFINEON]
HIGH AND LOW SIDE DRIVER; 高端和低端驱动器
| 型号： | IR2181PBF |
| 厂家： | 
Infineon |
| 描述： | HIGH AND LOW SIDE DRIVER |
| 文件： | 总14页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Data Sheet No. PD60030 rev.O
IR2213(S)&(PbF)
HIGH AND LOW SIDE DRIVER
Features
Product Summary
Floating channel designed for bootstrap operation
•
V
1200V max.
1.7A / 2A
12 - 20V
OFFSET
Fully operational to +1200V
Tolerant to negative transient voltage
dV/dt immune
I +/-
O
Gate drive supply range from 12 to 20V
•
V
OUT
Undervoltage lockout for both channels
•
3.3V logic compatible
•
t
(typ.)
280 & 225 ns
30 ns
Separate logic supply range from 3.3V to 20V
Logic and power ground ±±V offset
on/off
Delay Matching
Packages
CMOS Schmitt-triggered inputs with pull-down
•
Cycle by cycle edge-triggered shutdown logic
•
Matched propagation delay for both channels
•
•
Outputs in phase with inputs
• Also available LEAD-FREE (PbF)
Description
The IR2213(S) is a high voltage, high speed power
MOSFET and IGBT driver with independent high and
low side referenced output channels. Proprietary
HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. Logic inputs are
compatible with standard CMOS or LSTTL outputs,
down to 3.3V logic. The output drivers feature a high
16-Lead SOIC
(wide body)
14-Lead PDIP
pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched
to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power
MOSFET or IGBT in the high side configuration which operates up to 1200 volts.
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Typical Connection
ꢀꢍ
ꢋ
ꢋ
ꢋ
ꢋ
ꢐꢐ
ꢐꢐ
ꢑ
ꢒ
ꢀꢁꢂ
ꢒꢐ
ꢎꢁꢂ
ꢀꢁꢂ
ꢒꢐ
ꢎꢁꢂ
ꢌꢍ
ꢎꢍꢏꢐ
ꢋ
ꢓꢓ
ꢋ
ꢓꢍꢔ
ꢎꢍ
ꢋ
ꢒꢒ
ꢒꢒ
ꢋ
ꢓꢓ
(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical
connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
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1
IR2213(S)&(PbF)
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions.
Symbol
Definition
High Side Floating Supply Voltage
High Side Floating Supply Offset Voltage
High Side Floating Output Voltage
Low Side Fixed Supply Voltage
Low Side Output Voltage
Min.
Max.
Units
V
B
-0.3
122±
V
S
V
- 2±
V
+ 0.3
+ 0.3
2±
B
B
V
HO
V
S
- 0.3
V
B
V
CC
-0.3
-0.3
-0.3
V
LO
V
+ 0.3
CC
V
V
DD
Logic Supply Voltage
V
+ 2±
+ 0.3
+ 0.3
SS
CC
DD
V
Logic Supply Offset Voltage
V
- 2±
V
V
SS
CC
V
Logic Input Voltage (HIN, LIN & SD)
Allowable Offset Supply Voltage Transient (Figure 2)
V
- 0.3
IN
SS
dV /dt
s
—
±0
V/ns
W
P
D
Package Power Dissipation @ T ≤ +2±°C (14 Lead PDIP)
A
—
—
—
—
—
-±±
—
1.6
1.2±
7±
(16 Lead SOIC)
R
THJA
Thermal Resistance, Junction to Ambient
(14 Lead PDIP)
(16 Lead SOIC)
°C/W
100
12±
1±0
300
T
J
Junction Temperature
°C
T
S
Storage Temperature
T
L
Lead Temperature (Soldering, 10 seconds)
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. The V and V offset ratings are tested with all supplies biased at 1±V differential.
S SS
Symbol
Definition
High Side Floating Supply Absolute Voltage
High Side Floating Supply Offset Voltage
High Side Floating Output Voltage
Low Side Fixed Supply Voltage
Low Side Output Voltage
Min.
Max.
Units
V
B
V
+ 12
V + 20
S
S
V
S
Note 1
1200
V
HO
V
S
V
B
V
CC
12
0
20
V
V
LO
VCC
V
DD
Logic Supply Voltage
V
SS
+ 3
V
SS
+ 20
V
Logic Supply Offset Voltage
-± (Note 2)
±
SS
V
Logic Input Voltage (HIN, LIN & SD)
V
V
DD
IN
SS
Note 1: Logic operational for V of -± to +1200V. Logic state held for V of -±V to -V . (Please refer to the Design Tip
S S BS
DT97-3 for more details).
Note 2: When VDD<±V, the minimum VSS offset is limited to -VDD
2
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IR2213(S)&(PbF)
Dynamic Electrical Characteristics
V
(V , V , V ) = 1±V, C = 1000 pF, T = 2±°C and V
= COM unless otherwise specified. The dynamic
SS
BIAS
CC BS DD
L
A
electrical characteristics are measured using the test circuit shown in Figure 3.
Symbol
Definition
Turn-On Propagation Delay
Turn-Off Propagation Delay
Shutdown Propagation Delay
Turn-On Rise Time
Min. Typ. Max. Units Test Conditions
t
—
—
—
—
—
—
280
22±
230
2±
—
—
—
—
—
30
V = 0V
S
on
t
V
= 1200V
= 1200V
S
off
S
t
sd
V
ns
t
r
t
f
Turn-Off Fall Time
17
MT
Delay Matching, HS & LS Turn-On/Off
—
Static Electrical Characteristics
V
(V , V , V ) = 1±V, T = 2±°C and V = COM unless otherwise specified. The V , V and I parameters
BIAS CC BS DD
A
SS
IN TH
IN
are referenced to V and are applicable to all three logic input leads: HIN, LIN and SD. The V and I parameters are
SS
O
O
referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
Definition
Min. Typ. Max. Units Test Conditions
V
Logic “1” Input Voltage
9.±
—
—
—
—
—
—
—
—
—
—
—
6.0
1.2
0.1
±0
IH
V
IL
Logic “0” Input Voltage
V
V
OH
High Level Output Voltage, V
Low Level Output Voltage, V
- V
—
I
I
= 0A
= 0A
BIAS
O
O
V
OL
—
O
O
I
Offset Supply Leakage Current
—
V
= V = 1200V
B S
LK
I
Quiescent V Supply Current
BS
12±
180
1±
20
—
230
340
30
V
= 0V or V
QBS
IN
DD
DD
DD
I
Quiescent V
Quiescent V
Supply Current
Supply Current
V
V
= 0V or V
= 0V or V
QCC
CC
DD
IN
IN
µA
I
QDD
I
Logic “1” Input Bias Current
Logic “0” Input Bias Current
40
V
= V
IN DD
IN+
I
—
1.0
V
IN
= 0V
IN-
V
V
Supply Undervoltage Positive Going
BS
8.7
10.2 11.7
BSUV+
Threshold
Supply Undervoltage Negative Going
BS
V
V
7.9
8.7
7.9
1.7
2.0
9.3
10.7
BSUV-
Threshold
V
V
V
Supply Undervoltage Positive Going
10.2 11.7
CCUV+
CC
Threshold
V
V
Supply Undervoltage Negative Going
9.3
2.0`
2.±
10.7
—
CCUV-
CC
Threshold
I
Output High Short Circuit Pulsed Current
V
O
= 0V, V = V
IN DD
O+
PW ≤ 10 µs
= 1±V, V = 0V
O IN
A
I
O-
Output Low Short Circuit Pulsed Current
—
V
PW ≤ 10 µs
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3
IR2213(S)&(PbF)
Functional Block Diagram
ꢋ
ꢑ
ꢖꢋ
ꢋ
ꢐꢐ
ꢐꢗꢌꢗꢓꢌ
ꢙ
ꢙ
ꢒ
ꢚ
ꢀꢋ
ꢎꢗꢋꢗꢎ
ꢒꢀꢁꢜꢌ
ꢕꢖꢎꢒꢗ
ꢜꢁꢎꢌꢗꢙ
ꢀꢍ
ꢙ
ꢚ
ꢒ
ꢋ ꢝꢋ
ꢐꢐ ꢓꢓ
ꢀꢁꢂ
ꢎꢗꢋꢗꢎ
ꢒꢀꢁꢜꢌ
ꢕꢖꢎꢒꢗ
ꢘꢗꢂ
ꢋ
ꢒ
ꢒꢐ
ꢋ
ꢓꢓ
ꢖꢋ
ꢐꢗꢌꢗꢓꢌ
ꢋ ꢝꢋ
ꢐꢐ ꢓꢓ
ꢎꢁꢂ
ꢎꢗꢋꢗꢎ
ꢎꢍ
ꢒꢀꢁꢜꢌ
ꢒ
ꢙ
ꢚ
ꢐꢗꢎꢏꢛ
ꢓꢍꢔ
ꢋ
ꢒꢒ
Lead Definitions
Symbol Description
V
DD
Logic supply
HIN
SD
Logic input for high side gate driver output (HO), in phase
Logic input for shutdown
LIN
Logic input for low side gate driver output (LO), in phase
Logic ground
V
SS
V
B
High side floating supply
HO
High side gate drive output
High side floating supply return
Low side supply
V
S
V
CC
LO
Low side gate drive output
COM
Low side return
Lead Assignments
14 Lead PDIP
16 Lead SOIC (Wide Body)
IR2213
IR2213S
Part Number
4
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IR2213(S)&(PbF)
HV =10 to 1200V
<±0 V/ns
Figure 1. Input/Output Timing Diagram
Figure 2. Floating Supply Voltage Transient Test Circuit
#ꢊ$
#ꢊ$
ꢀꢁꢂ
ꢎꢁꢂ
(0 to 1200V)
ꢆ
ꢆ
ꢆ
ꢠ
ꢆ
ꢇꢟ
ꢇꢠꢠ
ꢞ
%ꢊ$
%ꢊ$
ꢀꢍ
ꢎꢍ
ꢈꢊ$
ꢈꢊ$
Figure 3. Switching Time Test Circuit
Figure 4. Switching Time Waveform Definition
#ꢊ$
#ꢊ$
ꢀꢁꢂ
ꢎꢁꢂ
50%
SD
ꢎꢍ
ꢀꢍ
t
sd
90%
ꢈꢊ$
HO
LO
ꢔꢌ
ꢔꢌ
%ꢊ$
ꢎꢍ
ꢀꢍ
Figure 5. Shutdown Waveform Definitions
Figure 6. Delay Matching Waveform Definitions
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±
IR2213(S)&(PbF)
100
80
100
80
60
40
20
0
60
Max.
Typ.
40
M ax.
Typ.
20
0
-50
-25
0
25
50
75
100
125
10
12
14
16
18
20
Temperature (°C)
VBIAS Supply Voltage (V)
Figure 10A. Turn-On Rise Time vs. Temperature
Figure 10B. Turn-On Rise Time vs. Voltage
50
50
40
30
20
10
0
40
30
20
10
0
Max.
Typ.
Max.
Typ.
-50
-25
0
25
50
75
100
125
10
12
14
16
18
20
Temperature (°C)
V
BIAS Supply Voltage (V)
Figure 11A. Turn-Off Fall Time vs. Temperature
Figure 11B. Turn-Off Fall Time vs. Voltage
15.0
12.0
15
12
9
Max.
Min.
9.0
6
6.0
3.0
0.0
3
0
0
2
4
6
VDD Logic Supply Voltage (V)
8
10 12 14 16 18 20
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 12A. Logic “1” Input Threshold vs. Temperature
Figure 12B. Logic “1” Input Threshold vs. Voltage
6
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IR2213(S)&(PbF)
15.0
12.0
9.0
15
12
9
Min
.
Max.
6
6.0
3
3.0
0
0.0
0
2
4
6
VDD Logic Supply Voltage (V)
8
10 12 14 16 18 20
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 13A. Logic “0” Input Threshold vs. Temperature
Figure 13B. Logic “0” Input Threshold vs. Voltage
5.00
4.00
3.00
2.00
5.00
4.00
3.00
2.00
Max.
M ax.
1.00
1.00
0.00
0.00
-50
-25
0
25
50
75
100
125
10
12
14
16
18
20
Temperature (°C)
V
BIAS Supply Voltage (V)
Figure 14A. High Level Output vs. Temperature
Figure 14B. High Level Output vs. Voltage
1.00
1.00
0.80
0.60
0.40
0.20
0.00
0.80
0.60
0.40
0.20
M ax.
Max.
0.00
-50
-25
0
25
50
75
100
125
10
12
14
16
18
20
Temperature (°C)
V
BIAS Supply Voltage (V)
Figure 15A. Low Level Output vs. Temperature
Figure 15B. Low Level Output vs. Voltage
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7
IR2213(S)&(PbF)
500
400
300
200
100
500
400
300
200
100
0
Max.
Max.
0
-50
-25
0
25
50
75
100
125
0
200
400
600
800
1000
1200
VB Boost Voltage (V)
Temperature (°C)
Figure 16A. Offset Supply Current vs. Temperature
Figure 16B. Offset Supply Current vs. Voltage
500
400
300
500
400
300
200
100
0
Max.
200
Max.
Typ.
Typ.
100
0
-50
-25
0
25
50
75
100
125
10
12
14
16
18
20
Temperature (°C)
VBS Floating Supply Voltage (V)
Figure 17A. VBS Supply Current vs. Temperature
Figure 17B. VBS Supply Current vs. Voltage
625
625
500
375
500
375
250
125
0
Max.
250
Max.
Typ.
Typ.
125
0
-50
-25
0
25
50
75
100
125
10
12
14
16
18
20
Temperature (°C)
VCC Fixed Supply Voltage (V)
Figure 18A. VCC Supply Current vs. Temperature
Figure 18B. VCC Supply Current vs. Voltage
8
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IR2213(S)&(PbF)
100
80
60
40
20
0
60
50
40
30
20
10
0
max
Max.
Typ.
typ.
0
2
4
6
VDD Logic Supply Voltage (V)
8
10 12 14 16 18 20
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 19B. VDD Supply Current vs. VDD Voltage
Figure 19A. VDD Supply Current vs. Temperature
100
80
60
50
40
30
20
60
40
Max.
max
10
20
Typ.
typ.
0
0
0
2
4
6
VDD Logic Supply Voltage (V)
8
10 12 14 16 18 20
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 20A. Logic “1” Input Current vs. Temperature
Figure 20B. Logic “1” Input Current vs. VDD Voltage
5
4
3
2
5.00
4.00
3.00
2.00
max
1
Max.
1.00
0
0.00
0
2
4
6
VDD Logic Supply Voltage (V)
8
10 12 14 16 18 20
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 21A. Logic “0” Input Current vs. Temperature
Figure 21B. Logic “0” Input Current vs. VDD Voltage
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9
IR2213(S)&(PbF)
0.0
20.0
16.0
12.0
8.0
-3.0
Typ.
-6.0
-9.0
Typ.
-12.0
-15.0
4.0
0.0
10
12
14
16
18
20
10
12
14
16
18
20
VBS Floating Supply Voltage (V)
VCC Fixed Supply Voltage (V)
Figure 22. Maximum VS Negative Offset vs.
VBS Supply Voltage
Figure 23. Maximum VSS Positive Offset vs.
VCC Supply Voltage
65
55
45
35
25
15
65
55
45
35
25
15
300v
200v
300v
200v
100v
0v
100v
0v
0.1
1
10
100
0.1
1
10
100
Frequency (KHZ)
Frequency (KHZ)
Figure 24. IR2213s vs. Frequency (IRFBC20)
Figure 25. IR2213s vs. Frequency (IRFBC30)
Rgate=33 , VCC=15V
Rgate=22 , VCC=15V
Ω
Ω
10
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IR2213(S)&(PbF)
75
65
55
45
35
25
15
75
65
55
45
35
25
15
300v
200v
100v
0v
300v
200v
100v
0v
0.1
1
10
100
0.1
1
10
100
Frequency (KHZ)
Frequency (KHZ)
Figure 26. IR2213s vs. Frequency (IRFBC40)
Figure 27. IR2213s vs. Frequency (IRFBC50)
Rgate=15 , VCC=15V
Rgate=10 , VCC=15V
Ω
Ω
65
55
45
35
25
15
65
55
45
35
25
15
300v
200v
300v
200v
100v
100v
0v
0v
0.1
1
10
100
0.1
1
10
100
Frequency (KHZ)
Frequency (KHZ)
Figure 28. IR2213 vs. Frequency (IRFBC20)
Figure 29. IR2213 vs. Frequency (IRFBC30)
Rgate=33 , VCC=15V
Rgate=22 , VCC=15V
Ω
Ω
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11
IR2213(S)&(PbF)
75
65
55
45
35
25
15
75
65
55
45
35
25
15
300v
200v
100v
300v
200v
100v
0v
0v
0.1
1
10
100
0.1
1
10
100
Frequency (KHZ)
Frequency (KHZ)
Figure 30. IR2213 vs. Frequency (IRFBC40)
Rgate=15 , VCC=15V
Figure 31. IR213 vs. Frequency (IRFBC50)
Rgate=10 VCC=15V
Ω
Ω,
12
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IR2213(S)&(PbF)
Case outlines
01-6010
01-3002 03 (MS-001AC)
14-Lead PDIP
01 601±
16-Lead SOIC (wide body)
01-3014 03 (MS-013AA)
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13
IR2213(S)&(PbF)
LEADFREE PART MARKING INFORMATION
Part number
Date code
IRxxxxxx
YWW?
IR logo
?XXXX
Pin 1
Identifier
Lot Code
(Prod mode - 4 digit SPN code)
?
MARKING CODE
P
Lead Free Released
Non-Lead Free
Released
Assembly site code
Per SCOP 200-002
ORDER INFORMATION
Basic Part (Non-Lead Free)
Leadfree Part
8-Lead PDIP IR2181 order IR2181
8-Lead SOIC IR2181S order IR2181S
14-Lead PDIP IR21814 order IR21814
14-Lead SOIC IR21814 order IR21814S
8-Lead PDIP IR2181 order IR2181PbF
8-Lead SOIC IR2181S order IR2181SPbF
14-Lead PDIP IR21814 order IR21814PbF
14-Lead SOIC IR21814 order IR21814SPbF
Thisproduct has been designed and qualified for the industrial market.
Qualification Standards can be found on IR’s Web Site http://www.irf.com
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
9/21/2004
14
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