IR22141PBF [INFINEON]
Half Bridge Based Peripheral Driver, 3A, PDSO24, MO-150AH, SSOP-24;
| 型号： | IR22141PBF |
| 厂家： | 
Infineon |
| 描述： | Half Bridge Based Peripheral Driver, 3A, PDSO24, MO-150AH, SSOP-24 驱动 光电二极管 接口集成电路 |
| 文件： | 总28页 (文件大小：836K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet No.PD60213
ADVANCE DATA
IR2214/IR22141
HALF-BRIDGE GATE DRIVER IC
Features
Product Summary
Floating channel up to +1200V
Soft overcurrent shutdown
Synchronization signal to synchronize shut down
with the other phases
Integrated desaturation detection circuit
Two stage turn on output for di/dt control
Separate pull-up/pull-down output drive pins
Matched delay outputs
•
V
1200V max.
2.0 A / 3.0A
10.4V - 20V
OFFSET
I +/- (typ.)
•
O
•
V
OUT
•
Deadtime matching (max) 75nsec
•
•
•
•
Deadtime (typ)
330nsec
Desat blanking time (typ)
DSH,DSL input voltage
threshold (typ)
3µsec
Under voltage lockout with hysteresis band
8.0V
9.6µsec
Description
The IR2214/IR22141 is a gate driver suited to drive a
single half bridge in power switching applications.
The high gate driving capability (2A source, 3A sink)
Soft shutdown time (typ)
and the low quiescent current enable bootstrap supply techniques in medium
power systems. The IR2214/IR22141 driver features full short circuit protection
by means of the power transistor desaturation detection. The IR2214/IR22141
manages all the half-bridge faults by turning off smoothly the desaturated tran-
sistor through the dedicated soft shut down pin, therefore preventing over-volt-
ages and reducing EM emissions. In multi-phase system IR2214/IR22141 driv-
ers communicate using a dedicated local network (SY_FLT and FAULT/SD sig-
nals) to properly manage phase-to-phase short circuits. The system controller
may force shutdown or read device fault state through the 3.3 V compatible CMOS
I/O pin (FAULT/SD). To improve the signal immunity from DC-bus noise, the con-
trol and power ground use
Package
24-Lead SSOP
DC+
dedicated pins enabling
low-side emitter current
sensing as well. Under volt-
age conditions in floating
and low voltage circuits are
managed independently.
VCC
VB
15 V
HOP
HON
LIN
SSDH
HIN
DSH
VS
uP,
Control
Motor
DC BUS
(1200V)
FAULT/SD
FLT_CLR
SY_FLT
Typical Connection
LOP
LON
(Refer to Lead Assignments for
correct pin configuration). This/
These diagram(s) show
SSDL
DSL
COM
VSS
electrical connections only.
Please refer to our Application
Notes and DesignTips for
proper circuit board layout.
DC-
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1
ADVANCE DATA
IR2214/IR22141
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur.All voltage parameters
are absolute voltages referenced to V
all currents are defined positive into any lead The thermal resistance and power
SS,
dissipation ratings are measured under board mounted and still air conditions.
Symbol
Definition
Min.
Max.
Units
V
V
High side offset voltage
V
- 25
V + 0.3
B
S
B
B
High side floating supply voltage
-0.3
- 0.3
1225
V
V
High side floating output voltage (HOP, HON and SSDH)
Low side and logic fixed supply voltage
Power ground
V
S
V
B
+ 0.3
25
HO
CC
-0.3
- 25
COM
V
CC
V
V
+ 0.3
+ 0.3
+ 0.3
+ 0.3
CC
CC
V
Low side output voltage (LOP, LON and SSDL)
Logic input voltage (HIN, LIN and FLT_CLR)
FAULT input/output voltage (FAULT/SD and SY_FLT)
High side DS input voltage
V
-0.3
COM
V
LO
V
IN
-0.3
-0.3
V
V
CC
CC
V
FLT
V
DSH
V
-25
V
+ 0.3
B
B
V
DSL
Low side DS input voltage
V
CC
- 25
V
+ 0.3
CC
dV /dt
Allowable offset voltage slew rate
—
50
V/ns
W
s
P
D
Package power dissipation @ T ≤ +25°C
—
—
1.5
65
A
Rth
Thermal resistance, junction to ambient
Junction temperature
°C/W
JA
T
T
T
—
150
150
300
J
°C
Storage temperature
-55
—
S
L
Lead temperature (soldering, 10 seconds)
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. All voltage parameters are absoute
voltages referenced to V
The V offset rating is tested with all supplies biased at 15V differential.
SS.
S
Symbol
Definition
Min.
Max.
Units
V
High side floating supply voltage (Note 1)
High side floating supply offset voltage
High side output voltage (HOP, HON and SSDH)
Low side output voltage (LOP, LON and SSDL)
Low side and logic fixed supply voltage (Note 1)
Power ground
V
+ 11.5
V + 20
S
B
S
V
S
Note 2
1200
V + 20
S
V
HO
V
S
V
LO
V
COM
V
CC
V
CC
11.5
20
5
COM
- 5
0
V
V
IN
Logic input voltage (HIN, LIN and FLT_CLR)
Fault input/output voltage (FAULT/SD and SY_FLT)
High side DS pin input voltage
V
CC
V
FLT
0
V
CC
V
DSH
V
- 20
V
B
B
V
DSL
Low side DS pin input voltage
V
- 20
V
CC
CC
T
A
Ambient temperature
-40
125
°C
Note 1: While internal circuitry is operational below the indicated supply voltages, the UV lockout disables the output
drivers if the UV thresholds are not reached.
Note 2: Logic operational for VS from VSS-5 to VSS+1200V. Logic state held for VS from VSS-5V to VSS-VBS. (Please
refer to the Design Tip DT97-3 for more details).
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2
ADVANCE DATA
IR2214/IR22141
Static Electrical Characteristics
V
CC
= 15 V, V = COM = 0 V, V = 0 ÷ 1200 V and T = 25oC unless otherwise specified.
SS
S
A
Pin: VCC, VSS, VB, VS
Symbol
Definition
Min Typ Max Units Test Conditions
VCCUV+
VCCUV-
VCCUVH
VBSUV+
VBSUV-
VBSUVH
ILK
Vcc supply undervoltage positive going threshold
Vcc supply undervoltage negative going threshold
Vcc supply undervoltage lockout hysteresis
(VB-VS) supply undervoltage positive going threshold 9.3 10.2 11.4
(VB-VS) supply undervoltage negative going threshold 8.7 9.3 10.3
(VB-VS) supply undervoltage lockout hysteresis
Offset supply leakage current
Quiescent VBS supply current
9.3 10.2 11.4
8.7 9.3 10.3
-
0.9
-
V
VS=0V, VS=1200V
VS=0V, VS=1200V
-
-
-
-
0.9
-
-
50
VB = VS = 1200V
VIN = 0V or 3.3V
(No load)
ìA
IQBS
400 800
0.7 2.5 mA
IQCC
Quiescent Vcc supply current
comparator
VCC/VB
internal
signal
UV
VCCUV/VBSUV
VSS/VS
Figure 1: Undervoltage diagram
Pin: HIN, LIN, FLTCLR, FAULT/SD, SY_FLT
Symbol
Definition
Min Typ
Max Units Test Conditions
VIH
VIL
Logic "1" input voltage
Logic "0" input voltage
2.0
-
-
-
VCC = VCCUV- to
V
-
0.2
-
0.8
20V
VIHSS
Logic input hysteresis
0.4
370
-
60
60
-
-
ìA
IN+
I
IN
V = 3.3V
Logic "1" input bias current
Logic "0" input bias current
FAULT/SD open drain resistance
SY_FLT open drain resistance
IIN-
ON,FLT
-1
-
0
-
VIN = 0V
µA
R
Ù
ON,SY
R
-
-
P ≤7 ìs
schmitt
trigger
internal
signal
HIN/LIN/
FLTCLR
10k
VSS
Figure 2: HIN, LIN and FLTCLR diagram
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3
ADVANCE DATA
IR2214/IR22141
fault/hold
internal signal
FAULT/SD
SY_FLT
schmitt
trigger
RON
hard/soft shutdown
internal signal
VSS
Figure 3: FAULT/SD and SY_FLT diagram
Pin: DSL, DSH
The active bias is present only in IR22141. VDESAT, IDS and IDSB parameters are referenced to COM and VS
respectively for DSL and DSH.
Symbol
Definition
Min Typ Max Units
Test Conditions
VDESAT+
High desat input threshold voltage
Low desat input threshold voltage
Desat input voltage hysteresis
High DSH or DSL input bias current
Low DSH or DSL input bias current
DSH or DSL input bias current (IR22141 only)
7.2 8.0 8.8
6.3 7.0 7.7
V
See Fig. 16, 4
DESAT-
V
VDSTH
DS+
-
-
-
-
1.0
21
-160
-20
-
-
-
-
DESAT
V
CC
BS
I
= V or V
ìA
DS-
I
DESAT
V = 0V
DSB
DESAT
V =
I
mA
CC
BS
(V or V ) - 2V
VCC/VBS
active
bias
100k
700k
comparator
DSL/DSH
internal
signal
SSD
VDESAT
COM/VS
Figure 4: DSH and DSL diagram
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4
ADVANCE DATA
IR2214/IR22141
Pin: HOP, LOP
Symbol
Definition
Min Typ Max Units Test Conditions
mV
IO = 1mA
VOH
IO1+
High level output voltage, VB – VHOP or Vcc –VLOP
Output high first stage short circuit pulsed current
-
-
20 100
2
-
VHOP/LOP=0V,
HIN or LIN= 1,
PW≤200ns,
resistive load,
see Fig. 8
A
IO2+
Output high second stage short circuit pulsed current
-
1
-
VHOP/LOP=0V,
H
IN or LIN = 1,
400ns≤PW≤10ìs,
resistive load,
see Fig. 8
200ns
oneshot
VCC/VB
VOH
on/off
internal signal
LOP/HOP
Figure 5: HOP and LOP diagram
Pin: HON, LON, SSDH, SSDL
mV
Ù
IO = 1mA
VOL
Low level output voltage, VHON or VLON
Soft Shutdown on resistance (Note 1)
Output low short circuit pulsed current
-
2.3
15
RON,SSD
IO-
-
-
90
3
-
-
PW ≤ 7 ìs
A
VHOP/LOP=15V,
H
IN or LIN = 0,
PW≤10ìs
LON/HON
SSDL/SSDH
on/off
internal signal
VOL
RON,SSD
desat
internal signal
COM/VS
Figure 6: HON, LON, SSDH and SSDL diagram
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5
ADVANCE DATA
IR2214/IR22141
AC Electrical Characteristics
VCC = VBS = 15V, VS = VSS and TA = 25°C unless otherwise specified.
Symbol
Definition
Min. Typ. Max. Units
Test Conditions
ton
toff
Turn on propagation delay
220 440 660
220 440 660
VIN = 0 & 1
Turn off propagation delay
VS = 0 to 1200V
HOP shorted to HON,
LOP shorted to LON,
tr
tf
Turn on rise time (CLOAD=1nF)
Turn off fall time (CLOAD=1nF)
Turn on first stage duration time
—
—
24
7
—
—
Figure 7, 10
Figure 8
ton1
tDESAT1
120 200 280
DSH to HO soft shutdown propagation delay at HO 2000 3300 4600
turn on
VHIN= 1
tDESAT2
tDESAT3
tDESAT4
DSH to HO soft shutdown propagation delay after
Blanking
1050
—
—
VDESAT = 15V,Fig.10
DSL to LO soft shutdown propagation delay at LO
turn on
2000 3300 4600
VLIN = 1
DSL to LO soft shutdown propagation delay after
Blanking
1050
1000
—
—
—
—
VDESAT = 15V,Fig.10
tDS
tSS
Soft shutdown minimum pulse width of desat
Soft shutdown duration period
Figure 9
5700 9600 13500
CL=TBD ìꢀ,
VDS=15V,Fig. 9
ns
tSY_FLT,
DESAT1
tSY_FLT,
DESAT2
tSY_FLT,
DESAT3
tSY_FLT,
DESAT4
tBL
DSH to SY_FLT propagation delay at HO turn on
DSH to SY_FLT propagation delay after blanking
DSL to SY_FLT propagation delay at LO turn on
DSL to SY_FLT propagation delay after blanking
DS blanking time at turn on
—
1300
—
3600
—
—
—
—
—
—
VHIN = 1
VDS = 15V, Fig. 10
3050
—
VLIN = 1
1050
—
VDESAT=15V,Fig.10
3000
VHIN = VLIN = 1
VDESAT=15V,Fig.10
Dead-time/Delay Matching Characteristics
DT
MDT
Dead-time
Dead-time matching, MDT=DTH-DTL
—
—
330
—
—
75
Figure 11
External DT=0nsec
Figure 11
PDM
Propagation delay matching,
Max(ton, toff) - Min(ton, toff)
—
—
75
External DT>
500nsec, Fig.7
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6
ADVANCE DATA
IR2214/IR22141
3.3V
HIN
LIN
50%
50%
PWin
ton
tr
toff
tf
PWout
HO (HOP=HON)
LO (LOP=LON)
90%
90%
10%
10%
Figure 7: Switching Time Waveforms
Ton1
Io1+
Io2+
Figure 8: Output Source Current
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7
ADVANCE DATA
IR2214/IR22141
3.3V
HIN/LIN
tDS
VDESAT+
DSH/DSL
VDESAT-
SSD Driver Enable
tSS
tDESAT
HO/LO
Figure 9: Soft Shutdown Timing Waveform
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8
ADVANCE DATA
IR2214/IR22141
50%
50%
HIN
LIN
50%
8V
8V
DSH
8V
8V
DSL
50%
50%
50%
50%
SY_FLT
tSY_FLT,DESAT1
tSY_FLT,DESAT2
tSY_FLT,DESAT3
tSY_FLT,DESAT4
FAULT/SD
FLTCLR
HON
90%
90%
90%
SoftShutdown
SoftShutdown
50%
10%
50%
tBL
tDESAT1
tBL
tDESAT2
toff
90%
90%
SoftShutdown
50%
10%
50%
SoftShutdown
ton
LON
tBL
tDESAT3
tBL
tDESAT4
ton
Figure 10: Desat Timing
LIN
HIN
50%
50%
50%
50%
DTL
HO (HOP=HON)
DTH
50%
LO (LOP=LON) 50%
MDT=DTH-DTL
Figure 11: Internal Dead-Time Timing
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9
ADVANCE DATA
IR2214/IR22141
Lead Assignments
1
HIN
LIN
24
DSH
VB
FLT_CLR
SY_FLT
FAULT/SD
VSS
N.C.
HOP
HON
VS
24-Lead SSOP – IR2214SS
SSOP24
SSDL
COM
SSDH
N.C.
N.C.
N.C.
N.C.
N.C.
LON
LOP
VCC
12
DSL
13
Lead Definitions
Symbol
Description
VCC
VSS
HIN
LIN
Low side gate driver supply
Logic Ground
Logic input for high side gate driver outputs (HOP/HON)
Logic input for low side gate driver outputs (LOP/LON)
Dual function (in/out) active low pin. Refer to figures 17, 18 and 15. As an output, indicates fault
FAULT/SD condition. As an input, shuts down the outputs of the gate driver regardless HIN/LIN status.
Dual function (in/out) active low pin. Refer to figures 17, 18 and 15. As an output, indicates SSD
SY_FLT
sequence is occurring. As an input, an active low signal freezes both output status.
FLT_CLR Fault clear active high input. Clears latched fault condition (See figure 17)
LOP
LON
DSL
SSDL
COM
VB
HOP
HON
DSH
SSDH
VS
Low side driver sourcing output
Low side driver sinking output
Low side IGBT desaturation protection input
Low side soft shutdown
Low side driver return
High side gate driver floating supply
High side driver sourcing output
High side driver sinking output
High side IGBT desaturation protection input
High side soft shutdown
High side floating supply return
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ADVANCE DATA
IR2214/IR22141
Functional Block Diagram
VCC
VB
on/off
SCHMITT
TRIGGER
INPUT
LATCH
HOP
on/off (HS)
on/off (LS)
di/dt control
on/off
desat
HIN
LIN
Driver
LOCAL DESAT
PROTECTION
INPUT
HOLD
LOGIC
OUTPUT
SHUTDOWN
LOGIC
soft
HON
LEVEL
SHIFTERS
SHOOT
THROUGH
PREVENTION
shutdown
SOFT SHUTDOWN
UV_VBS DETECT
SSDH
DSH
(DT) Deadtime
VS
UV_VCC
DETECT
UV_VCC
on/off
LOP
LON
di/dt control
Driver
DesatHS
soft
SSD
HOLD
SD
LOCAL DESAT
PROTECTION
FAULT LOGIC
managemend
(See figure 14)
SY_FLT
FAULT/SD
FLT_CLR
shutdown
FAULT
SSDL
DSL
SOFTSHUTDOWN
DesatLS
COM
VSS
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11
ADVANCE DATA
IR2214/IR22141
State Diagram
Start-Up
Sequence
ShutDown
HO=LO=0
UnderVoltage
VCC
UnderVoltage
VBS
FAULT
HO=LO=0
HO=0, LO=LIN
UV_VCC
DESAT
EVENT
HO/LO=1
UV_VBS
Soft
ShutDown
Freeze
Stable State
Temporary State
System Variable
−
−
FAULT
−
−
SOFT SHUTDOWN
START UP SEQUENCE
−
−
−
−
−
−
−
FLT_CLR
HIN/LIN
UV_VCC
UV_VBS
DSH/L
HO=LO=0 (Normal
operation)
−
HO/LO=1 (Normal
operation)
−
−
−
−
UNDERVOLTAGE VCC
SHUTDOWN (SD)
UNDERVOLTAGE VBS
FREEZE
SY_FLT
FAULT/SD
NOTE1: a change of logic value of the signal labeled on lines (system variable) generates a state
transition.
NOTE2: Exiting from UNDERVOLTAGE VBS state, the HO goes high only if a rising edge event
happens in HIN.
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ADVANCE DATA
IR2214/IR22141
IR2214 Logic Table
Output drivers status description
HO/LO
HOP/LOP HON/LON
SSDH/SSDL
status
0
1
SSD
HiZ
1
HiZ
0
HiZ
HiZ
HiZ
HiZ
0
Output follows inputs (in=1->out=1, in=0->out=0)
LO/HO
LOn-1/HOn-1
Output keeps previous status
Under Voltage
Yes: V< UV threshold
No : V> UV threshold
INPUTS
INPUT/OUTPUT
OUTPUTS
X
: don’t care
SY_FLT
SSD: desat (out)
FAULT/SD
SD: shutdown (in)
VCC
VBS
HO
LO
Hin
Lin
FLT_CLR
Operation
HOLD: freezing (in) FAULT: diagnostic (out)
Shut Down
Fault Clear
X
X
X
X
0 (SD)
(FAULT)
X
X
0
HO
1
0
LO
0
NOTE1
HIN LIN
No
No
No
No
No
No
No
No
1
0
0
0
1
0
0
0
0
1
1
1
1
1
1
Normal
Operation
0
1
0
0
Anti Shoot
Through
1
1
1
0
0
0
0
0
0
X
X
X
1
1
1
No
No
No
No
No
No
No
Yes
No
No
No
No
No
No
Yes
X
0
SSD
0
0
0
(SSD)
Soft Shut Down (entering)
(SSD)
(SSD)
(SSD)
0
1
1
SSD
0
(FAULT)
X
X
X
X
X
X
0
Soft Shut Down (finishing)
Freeze
(FAULT)
X
0
0
X
0 (HOLD)
1
1
HOn-1 LOn-1
LIN
X
1
1
0
0
LO
0
Under Voltage
0 (FAULT)
NOTE1: SY_FLT automatically resets after SSD event is over and FLT_CLR is not required.
In order to avoid FLT_CLR to conflict with the SSD procedure, FLT_CLR should not be
operated while SY_FLT is active.
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ADVANCE DATA
IR2214/IR22141
2. Normal operation mode
FEATURES DESCRIPTION
1. Start-up sequence
After start-up sequence has been terminated, the
device becomes fully operative (see grey blocks
in the State Diagram).
HIN and LIN produce driver outputs to switch
accordingly, while the input logic checks the input
signals preventing shoot-through events and
including DeadTime (DT).
At power supply start-up it is recommended to
keep FLT_CLR pin active until supply voltages
are properly established. This prevents spurious
diagnostic signals being generated. All protection
functions are operating independently from
FLT_CLR status and output driver status reflects
the input commands.
3. Shut down
When bootstrap supply topology is used for
supplying the floating high side stage, the
following start-up sequence is recommended
(see also figure 12):
The system controller can asynchronously
command the Hard ShutDown (HSD) through the
3.3 V compatible CMOS I/O FAULT/SD pin. This
event is not latched.
In a multi-phase system, FAULT/SD signals are
or-wired so the controller or one of the gate drivers
can force simultaneous shutdown to the other
gate drivers through the same pin.
1. Set Vcc
2. Set FLT_CLR pin to HIGH level
3. Set LIN pin to HIGH level and let the
bootstrap capacitor be charged
4. Release LIN pin to LOW level
5. Release FLT_CLR pin to LOW level
4. Fault management
IR2214 is able to manage both the supply failure
(undervoltage lock out on both low and high side
circuits) and the desaturation of both power
transistors.
VCC
FLT_CLR
LIN
4.1 Undervoltage (UV)
The Undervoltage protection function disables the
driver’s output stage preventing the power device
being driven with too low voltages.
Both the low side (VCC supplied) and the floating
side (VBS supplied) are controlled by a dedicate
undervoltage function.
LO
Undervoltage event on the VCC (when
VCC < UVVCC-) generates a diagnostic signal by
forcing FAULT/SD pin low (see FAULT/SD section
and figure 14). This event disables both low side
and floating drivers and the diagnostic signal holds
until the under voltage condition is over. Fault
condition is not latched and the FAULT/SD pin is
Figure 12 Start-up sequence
A minimum 15µs LIN and FLT-CLR pulse is
required.
released once VCC becomes higher than UVVCC+
.
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14
ADVANCE DATA
IR2214/IR22141
The undervoltage on the VBS works disabling only
the floating driver. Undervoltage on VBS does not
prevent the low side driver to activate its output
nor generate diagnostic signals. VBS undervoltage
condition (VBS < UVVBS-) latches the high side
output stage in the low state. VBS must be
reestablished higher than UVVBS+ to return in
normal operating mode. To turn on the floating
driver HIN must be re-asserted high (rising edge
event on HIN is required).
of an external high voltage diode. High current in
the IGBT may cause the transistor to desaturate,
i.e. VCE to increase.
Once in desaturation, the current in power
transistor can be as high as 10 times the nominal
current. Whenever the transistor is switched off,
this high current generates relevant voltage
transients in the power stage that need to be
smoothed out in order to avoid destruction (by
over-voltages). The IR2214 gate driver accomplish
the transients control by smoothly turning off the
desaturated transistor by means of the SSD pin
activating a so called Soft ShutDown sequence
(SSD).
4.2 Power devices desaturation
Different causes can generate a power inverter
failure: phase and/or rail supply short-circuit,
overload conditions induced by the load, etc…
In all these fault conditions a large current
increase is produced in the IGBT.
4.2.1 Desaturation detection: DSH/L function
Figure 13 shows the structure of the desaturation
sensing and soft shutdown block. This configu-
ration is the same for both high and low side
output stages.
The IR2214 fault detection circuit monitors the
IGBT emitter to collector voltage (VCE) by means
sensing
diode
VB/Vcc
HOP/LOP
HON/LON
SSDH/L
PreDriver
ONE
SHOT
(ton1)
on/off
tBL
Blanking
tss
One Shot
DesatHS/LS
tDS
filter
DSH/L
desat
comparator
VDESAT
VS/COM
Figure 13: high and low side output stage
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15
ADVANCE DATA
IR2214/IR22141
internal
HOLD
internal FAULT
(hard shutdown)
SY_FLT
(external
hold)
FAULT/SD
(external hard
shutdown)
SET
CLR
Q
Q
S
R
DesatHS
DesatLS
UVCC
FLTCLR
Figure 14: fault management diagram
not completely saturated after TBL, desaturation
is detected and the driver will turn off.
The external sensing diode should have
BV>1200V and low stray capacitance (in order
to minimize noise coupling and switching de-
lays). The diode is biased by an internal pull-up
resistor RDSH/L (equal to VCC/IDS- or VBS/IDS- for
IR2214) or by a dedicated circuit (see the active-
bias section for the IR22141). When VCE in-
creases, the voltage at DSH/L pin increases too.
Being internally biased to the local supply,
DSH/L voltage is automatically clamped. When
DSH/L exceeds the VDESAT+ threshold the com-
parator triggers (see figure 13). Comparator
output is filtered in order to avoid false
desaturation detection by externally induced
noise; pulses shorter than tDS are filtered out. To
avoid detecting a false desaturation during IGBT
turn on, the desaturation circuit is disabled by a
Blanking signal (TBL, see Blanking block in fig-
ure 13). This time is the estimated maximum
IGBT turn on time and must be not exceeded by
proper gate resistance sizing. When the IGBT is
Eligible desaturation signals initiate the Soft
Shutdown sequence (SSD). While in SSD, the
output driver goes in high impedance and the
SSD pull-down is activated to turn off the IGBT
through SSDH/L pin. The SY_FLT output pin
(active low, see figure 14) reports the IR2214
status all the way long SSD sequence lasts (tSS).
Once finished SSD, SYS_FLT releases, and
IR2214 generates a FAULT signal (see the
FAULT/SD section) by activating FAULT/SD pin.
This generates a hard shut down for both high
and low output stages (HO=LO=low). Each driver
is latched low until the fault is cleared (see
FLT_CLR).
Figure 14 shows the fault management circuit.
In this diagram DesatHS and DesatLS are two
internal signals that come from the output stages
(see figure 13).
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16
ADVANCE DATA
IR2214/IR22141
FAULT
VCC
VB
VCC
VB
VCC
VB
LIN
HOP
HON
SSH
LIN
HOP
HON
SSH
LIN
HOP
HON
SSH
HIN
HIN
HIN
FLT_CLR
FLT_CLR
FLT_CLR
DSH
VS
DSH
VS
DSH
VS
SY_FLT
SY_FLT
SY_FLT
LOP
LON
SSL
LOP
LON
SSL
LOP
LON
SSL
FAULT/SD
FAULT/SD
FAULT/SD
DSL
DSL
DSL
VSS
COM
VSS
COM
VSS
COM
phase U
phase V
phase W
Figure 15: IR2214 application in 3ph system.
It must be noted that while in Soft Shut Down,
both Under Voltage fault and external Shut Down
(SD) are masked until the end of SSD.
Desaturation protection is working independently
by the other entire control pin and it is disabled
only when the output status is off.
to-phase short circuit where two IGBTs are
involved; in fact, while one is softly shutting-down,
the other must be prevented from hard shutdown
to avoid vanishing SSD.
In the Freeze state the frozen drivers are not
completely inactive because desaturation
detection still takes the highest priority.
SY_FLT communication has been designed for
creating a local network between the drivers.
There is no need to wire SY_FLT to the controller.
4.2.2 Fault management in multi-phase
systems
In a system with two or more gate drivers the
IR2214 devices must be connected as in figure 15.
FAULT/SD
SY_FLT.
The bi-directional FAULT/SD pins communicates
each other and with the system controller. The
logic signal is active low.
When low, the FAULT/SD signal commands the
outputs to go off by hard shutdown. There are
three events that can force FAULT/SD low:
The bi-directional SY_FLT pins communicate
each other in the local network. The logic signal
is active low.
The device that detects the IGBT desaturation
activates the SY_FLT, which is then read by the
other gate drivers. When SYS_FLT is active all
the drivers hold their output state regardless the
input signals (HIN, LIN) they receive from the
controller (freeze state).
1. Desaturation detection event: the
FAULT\SD pin is latched low when SSD
is over, and only a FLT_CLR signal can
reset it.
This feature is particularly important in phase-
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17
ADVANCE DATA
IR2214/IR22141
2. Undervoltage on VCC: the FAULT\SD pin
is forced low and held until the
undervoltage is active (not latched).
3. FAULT/SD is externally driven low either
from the controller or from another
IR2214 device. This event is not latched;
therefore the FLT_CLR cannot disable
it. Only when FAULT/SD becomes high
the device returns in normal operating
mode.
An Active Bias structure is available only for
IR22141 version for DSH/L pin. The DSH/L pins
present an active pull-up respectively to VB/VCC,
and a pull-down respectively to VS/COM.
The dedicated biasing circuit reduces the
impedance on the DSH/L pin when the voltage
exceeds the VDESAT threshold (see figure 16). This
low impedance helps in rejecting the noise
providing the current inject by the parasitic
capacitance. When the power transistor is fully
on, the sensing diode gets forward biased and
the voltage at the DSH/L pin decreases. At this
point the biasing circuit deactivates, in order to
reduce the bias current of the diode as shown in
figure 16.
5. Active bias
For the purpose of sensing the power transistor
desaturation the collector voltage is read by an
external HV diode. The diode is normally biased
by an internal pull up resistor connected to the
local supply line (VB or VCC). When the transistor
is “on” the diode is conducting and the amount
of current flowing in the circuit is determined by
the internal pull up resistor value.
RDSH/L
100K ohm
In the high side circuit, the desaturation biasing
current may become relevant for dimensioning
the bootstrap capacitor (see figure 19). In fact,
too low pull up resistor value may result in high
current discharging significantly the bootstrap
capacitor. For that reason typical pull up resistor
are in the range of 100 kΩ. This is the value of
the internal pull up.
100 ohm
VDSH/L
Figure 16: RDSH/L Active Biasing
While the impedance of DSH/DSL pins is very
low when the transistor is on (low impedance
path through the external diode down to the power
transistor), the impedance is only controlled by
the pull up resistor when the transistor is off. In
that case relevant dV/dt applied by the power
transistor during the commutation at the output
results in a considerable current injected through
the stray capacitance of the diode into the
desaturation detection pin (DSH/L). This coupled
noise may be easily reduced using an active bias
for the sensing diode.
6. Output stage
The structure is shown in figure 13 and consists
of two turns on stages and one turn off stage.
When the driver turns on the IGBT (see figure 8),
a first stage is constantly activated while an
additional stage is maintained active only for a
limited time (ton1). This feature boost the total
driving capability in order to accommodate both
fast gate charge to the plateau voltage and dV/dt
control in switching.
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18
ADVANCE DATA
IR2214/IR22141
At turn off, a single n-channel sinks up to 3A (IO-)
and offers a low impedance path to prevent the
self-turn on due to the parasitic Miller capacitance
in the power switch.
7. Timing and logic state diagrams
description
The following figures show the input/output logic
diagram.
Figure 17 shows the SY_FLT and FAULT/SD
signals as output, whereas figure 18 shows them
as input.
A
B
C
D
E
F
G
HIN
LIN
DSH
DSL
SY_FLT
FAULT/SD
FLT_CLR
HO(HOP/HON)
LO(LOP/LON)
Figure 17: I/O timing diagram with SY_FLT and FAULT/SD as output
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19
ADVANCE DATA
IR2214/IR22141
A
B
C
D
E
F
HIN
LIN
SY_FLT
FAULT/SD
FLT_CLR
HO (HOP/HON)
LO (LOP/LON)
Figure 18: I/O logic diagram with SY_FLT and FAULT/SD as input
Referred to timing diagram of figure 17:
Referred to logic diagram figure 18:
A. When the input signals are on together the
outputs go off (anti-shoot through).
A. The device is in hold state, regardless of input
variations. Hold state is forced by SY_FLT
forced low externally
B. The device outputs goes off by hard
shutdown, externally commanded. A through
B is the same sequence adopted by another
IR2214 device in SSD procedure.
C. Externally driven low FAULT/SD (shutdown
state) cannot be disabled by forcing FLT_CLR
(see FAULT/SD section).
D. The FAULT/SD is released and the outputs
go back to follow the inputs.
B. The HO signal is on and the high side IGBT
desaturates, the HO turn off softly while the
SY_FLT stays low. When SY_FLT goes high
the FAULT/SD goes low. While in SSD, if
LIN goes up, LO does not change (freeze).
C. When FAULT/SD is latched low (see FAULT/
SD section) FLT_CLR can disable it and the
outputs go back to follow the inputs.
D. The DSH goes high but this is not read
because HO is off.
E. The LO signal is on and the low side IGBT
desaturates, the low side behaviour is the
same as described in point B.
E. Externally driven low FAULT/SD: outputs go
off by hard shutdown (like point B).
F. As point A and B but for the low side output.
F. The DSL goes high but this is not read
because LO is off.
G. As point A (anti-shoot through).
www.irf.com
20
ADVANCE DATA
IR2214/IR22141
If VGEmin is the minimum gate emitter voltage we
want to maintain, the voltage drop must be:
Sizing tips
Bootstrap supply
∆VBS ≤ VCC −VF −VGE min −VCEon
The VBS voltage provides the supply to the high
side driver circuitry of the IR2214. This supply
sits on top of the VS voltage and so it must be
floating.
under the condition:
VGE min > VBSUV −
The bootstrap method to generate VBS supply
can be used with IR2214. The bootstrap supply
is formed by a diode and a capacitor connected
as in figure 19.
where VCC is the IC voltage supply, VF is boot-
strap diode forward voltage, VCEon is emitter-col-
lector voltage of low side IGBT and VBSUV- is the
high-side supply undervoltage negative going
threshold.
bootstrap
resistor
bootstrap
diode
DC+
Rboot
VF
Now we must consider the influencing factors
contributing VBS to decrease:
VCC
VB
VCC
HOP
HON
VS
bootstrap
capacitor
VBS
- IGBT turn on required Gate charge (QG);
- IGBT gate-source leakage current (ILK_GE);
- Floating section quiescent current (IQBS);
- Floating section leakage current (ILK)
- Bootstrap diode leakage current (ILK_DIODE);
VGE
ILOAD
motor
SSDH
VCEon
VFP
- Desat diode bias when on (IDS-
)
COM
- Charge required by the internal level shifters
(QLS); typical 20nC
- Bootstrap capacitor leakage current (ILK_CAP);
- High side on time (THON).
Figure 19: bootstrap supply schematic
This method has the advantage of being simple
and low cost but may force some limitations on
duty-cycle and on-time since they are limited by
the requirement to refresh the charge in the boot-
strap capacitor.
ILK_CAP is only relevant when using an electrolytic
capacitor and can be ignored if other types of
capacitors are used. It is strongly recommend
using at least one low ESR ceramic capacitor
(paralleling electrolytic and low ESR ceramic
may result in an efficient solution).
Proper capacitor choice can reduce drastically
these limitations.
Bootstrap capacitor sizing
Then we have:
To size the bootstrap capacitor, the first step is
to establish the minimum voltage drop (∆VBS)
that we have to guarantee when the high side
IGBT is on.
=
+
+
+
+
QTOT QG QLS (ILK _ GE IQBS
+
+
+
+
ILK ILK _ DIODE ILK _ CAP IDS − ) THON
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21
ADVANCE DATA
IR2214/IR22141
NOTICE: Here above VCC has been cho-
The minimum size of bootstrap capacitor is:
sen to be 15V. Some IGBTs may require
higher supply to work correctly with the boot-
strap technique. Also Vcc variations must be
accounted in the above formulas.
QTOT
CBOOT min
=
∆VBS
An example follows:
a) using a 25A @ 125C IGBT (IRGP30B120KD):
Some important considerations
a. Voltage ripple
IQBS = 800 µA (See Static Electrical Charact.);
ILK = 50 µA (See Static Electrical Charact.);
QLS = 20 nC;
•
•
•
•
•
•
There are three different cases making the boot-
strap circuit gets conductive (see figure 19):
ILOAD < 0; the load current flows in the low
•
QG = 160 nC (Datasheet IRGP30B120KD);
ILK_GE = 100 nA (Datasheet IRGP30B120KD);
ILK_DIODE = 100 µA (with reverse recovery
time <100 ns);
side IGBT displaying relevant VCEon
VBS = VCC −VF −VCEon
In this case we have the lowest value for VBS.
This represents the worst case for the bootstrap
capacitor sizing. When the IGBT is turned off
the Vs node is pushed up by the load current
until the high side freewheeling diode get for-
warded biased
ILK_CAP = 0 (neglected for ceramic capacitor);
IDS- = 150 µA (see Static Electrical Charact.);
THON = 100 µs.
•
•
•
And:
ILOAD = 0; the IGBT is not loaded while be-
ing on and VCE can be neglected
•
VCC = 15 V
•
•
•
•
VF = 1 V
=
−
VBS VCC VF
VCEonmax = 3.1 V
VGEmin = 10.5 V
ILOAD > 0; the load current flows through the
•
freewheeling diode
the maximum voltage drop ∆VBS becomes
VBS = VCC −VF +VFP
∆VBS ≤VCC −VF −VGEmin −VCEon
=
In this case we have the highest value for VBS.
Turning on the high side IGBT, ILOAD flows into
it and VS is pulled up.
15V 1V 10.5V 3.1V 0.4V
=
−
−
−
=
and the boodstrap capacitor is:
290 nC
To minimize the risk of undervoltage, bootstrap
capacitor should be sized according to the
ILOAD<0 case.
CBOOT
≥
= 725 nF
0.4V
www.irf.com
22
ADVANCE DATA
IR2214/IR22141
b. Bootstrap Resistor
Gate resistances
A resistor (Rboot) is placed in series with boot-
strap diode (see figure 19) so to limit the current
when the bootstrap capacitor is initially charged.
We suggest not exceeding some Ohms (typi-
cally 5, maximum 10 Ohm) to avoid increasing
the VBS time-constant. The minimum on time for
charging the bootstrap capacitor or for refresh-
ing its charge must be verified against this time-
constant.
The switching speed of the output transistor can
be controlled by properly size the resistors con-
trolling the turn-on and turn-off gate current. The
following section provides some basic rules for
sizing the resistors to obtain the desired switch-
ing time and speed by introducing the equivalent
output resistance of the gate driver (RDRp and
RDRn).
The examples always use IGBT power transis-
tor. Figure 20 shows the nomenclature used in
the following paragraphs. In addition, Vge* indi-
cates the plateau voltage, Qgc and Qge indicate
the gate to collector and gate to emitter charge
respectively.
c. Bootstrap Capacitor
For high THON designs where is used an electro-
lytic tank capacitor, its ESR must be consid-
ered. This parasitic resistance forms a voltage
divider with Rboot generating a voltage step on VBS
at the first charge of bootstrap capacitor. The
voltage step and the related speed (dVBS/dt)
should be limited. As a general rule, ESR should
meet the following constraint:
IC
CRES
VGE
ESR
VCC ≤ 3V
ESR + RBOOT
t1,QGE
VCE
t2,QGC
Parallel combination of small ceramic and large
electrolytic capacitors is normally the best com-
promise, the first acting as fast charge thank for
the gate charge only and limiting the dVBS/dt by
reducing the equivalent resistance while the sec-
ond keeps the VBS voltage drop inside the de-
sired ∆VBS.
dV/dt
IC
90%
CRESon
CRES
VGE
Vge
*
CRESoff
10%
10%
t,Q
d. Bootstrap Diode
The diode must have a BV> 1200V and a fast
recovery time (trr < 100 ns) to minimize the
amount of charge fed back from the bootstrap
capacitor to VCC supply
tSW
tDon
tR
Figure 20: Nomenclature
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23
ADVANCE DATA
IR2214/IR22141
When RGon > 7 Ohm, RDRp is defined by
Sizing the turn-on gate resistor
•
Switching-time
ton1 Vcc Vcc t
+
SW −1 when tSW >ton1
For the matters of the calculation included here-
after, the switching time tsw is defined as the time
spent to reach the end of the plateau voltage (a
total Qgc+Qge has been provided to the IGBT gate).
To obtain the desired switching time the gate
resistance can be sized starting from Qge and
tSW Io1+ Io2+ ton1
RDRp=
Vcc
Io1+
when tSW ≤ton1
(IO1+ ,IO2+ and ton1 from the IR2214 datasheet).
*
Qgc, Vcc, Vge (see figure 21):
Table 1 reports the gate resistance size for two
commonly used IGBTs (calculation made using
typical datasheet values and assuming
Vcc=15V).
Qgc + Qge
Iavg
=
tsw
and
•
Output voltage slope
Vcc −Vg*e
Turn-on gate resistor RGon can be sized to con-
RTOT
=
trol output slope (dVOUT/dt).
Iavg
While the output voltage has a non-linear
behaviour, the maximum output slope can be ap-
proximated by:
Iavg
Vcc/Vb
Iavg
dVout
dt
CRES
=
CRESoff
RDRp
inserting the expression yielding Iavg and
rearranging:
RGon
*
Vcc −Vge
COM/Vs
RTOT
=
dVout
dt
CRESoff
Figure 21: RGon sizing
As an example, table 2 shows the sizing of gate
resistance to get dVout/dt=5V/ns when using two
popular IGBTs, typical datasheet values and
assuming Vcc=15V.
where RTOT = RDRp + RGon
RGon = gate on-resistor
RDRp = driver equivalent on-resistance
NOTICE: Turn on time must be lower than TBL to
avoid improper desaturation detection and SSD
triggering.
www.irf.com
24
ADVANCE DATA
IR2214/IR22141
Translated into equations::
Sizing the turn-off gate resistor
The worst case in sizing the turn-off resistor RGoff
is when the collector of the IGBT in off state is
forced to commutate by external events (i.e. the
turn-on of the companion IGBT).
Vth
≥
(
RGoff
+
R
)
I
=
(
RGoff R
+
)
DRn
DRn
dVout
dt
CRESoff
In this case the dV/dt of the output node induces
a parasitic current through CRESoff flowing in RGoff
and RDRn (see figure 22).
If the voltage drop at the gate exceeds the thresh-
old voltage of the IGBT, the device may self turn
on causing large oscillation and relevant cross
conduction.
Rearranging the equation yields:
Vth
RGoff
≤
− RDRn
dV
dt
CRESoff
When RGoff > 4 Ohm, RDRn is well defined by
Vcc/IO- (IO- from IR2214 datasheet).
As an example, table 3 reports RGoff for two popu-
lar IGBT to withstand dVout/dt = 5V/ns.
dV/dt
HS Turning ON
CRESoff
NOTICE: the above-described equations are in-
tended being an approximated way for the gate
resistances sizing. More accurate sizing may
account more precise device modelling and para-
sitic component dependent on the PCB and
power section layout and related connections.
RGoff
OFF
ON
RDRn
Figure 22: RGoff sizing: current path when Low
Side is off and High Side turns on
Table 1: tsw driven RGon sizing
IGBT
Qge
Qgc
Vge* tsw
Iavg
Rtot
→
Tsw
RGon
std commercial value
IRGP30B120K(D)
IRG4PH30K(D)
19nC
10nC
82nC
20nC
9V
9V
400ns
200ns
0.25A
0.15A
Ω
Ω
→
→
→
→
24
40
RTOT - RDRp = 12.7 Ù
RTOT - RDRp = 32.5 Ù
10 Ù
33 Ù
420ns
202ns
Table 2: dVOUT/dt driven RGon sizing
IGBT
Qge
19nC 82nC 9V
10nc 20nC 9V
Qgc
Vge* CRESoff Rtot
dVout/dt
RGon → std commercial value
IRGP30B120K(D)
IRG4PH30K(D)
85pF
14pF
14Ω
85Ω
RTOT - RDRp = 6.5 Ù → 8.2 Ù
RTOT - RDRp = 78 Ù → 82 Ù
→4.5V/ns
→5V/ns
Table 3: RGoff sizing
IGBT
Vth(min)
CRESoff RGoff
IRGP30B120K(D)
IRG4PH30K(D)
4
3
85pF
14pF
RGoff ≤ 4 Ù
RGoff ≤ 35 Ù
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25
ADVANCE DATA
IR2214/IR22141
Supply capacitors:
PCB LAYOUT TIPS
IR2214 output stages are able to quickly turn on
IGBT with up to 2 A of output current. The sup-
ply capacitors must be placed as close as pos-
sible to the device pins (VCC and VSS for the
ground tied supply, VB and VS for the floating
supply) in order to minimize parasitic inductance/
resistance.
Distance from H to L voltage:
The IR2214 pin out maximizes the distance be-
tween floating (from DC- to DC+) and low voltage
pins. It’s strongly recommended to place com-
ponents tied to floating voltage in the high volt-
age side of device (VB, VS side) while the other
components in the opposite side.
Routing and placement example:
Figure 24 shows one of the possible layout solu-
tions using a 3 layer PCB. This example takes
into account all the previous considerations.
Placement and routing for supply capacitors and
gate resistances in the high and low voltage side
minimize respectively supply path and gate drive
loop. The bootstrap diode is placed under the
device to have the cathode as close as possible
to bootstrap capacitor and the anode far from
high voltage and close to VCC.
Ground plane:
Ground plane must not be placed under or
nearby the high voltage floating side to minimize
noise coupling.
Gate drive loops:
Current loops behave like an antenna able to re-
ceive and transmit EM noise. In order to reduce
EM coupling and improve the power switch turn
on/off performances, gate drive loops must be
reduced as much as possible. Figure 23 shows
the high and low side gate loops.
Moreover, current can be injected inside the gate
drive loop via the IGBT collector-to-gate parasitic
capacitance. The parasitic auto-inductance of the
gate loop contributes to develop a voltage across
the gate-emitter increasing the possibility of self
turn-on effect. For this reason is strongly recom-
mended to place the three gate resistances close
together and to minimize the loop
area (see figure 23).
IGC
VB/ VCC
gate
resistance
CGC
H/LOP
H/LON
SSDH/L
Gate Drive
VGE
Loop
VS/COM
Figure 23: gate drive loop
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26
ADVANCE DATA
IR2214/IR22141
R2
R3
R4
D2
DC+
VGH
C1
VEH
IR2214
D3
Phase
VCC
R1
R5
R6
R7
VGL
C2
VEL
a)
b)
c)
Figure 24: layout example: top (a), bottom (b)
and ground plane (c) layer
Referred to figure 24:
Bootstrap section: R1, C1, D1
High side gate: R2, R3, R4
High side Desat: D2
Low side supply: C2
Low side gate: R5, R6, R7
Low side Desat: D3
www.irf.com
27
ADVANCE DATA
IR2214/IR22141
Case outline
01 6076 01
01 5537 01 MO-150AH
24-Lead SSOP
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 8/6/2003
www.irf.com
28
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