IR2520DPBF [INFINEON]

ADAPTIVE BALLAST CONTROL IC; 自适应镇流器控制IC


型号：	IR2520DPBF
厂家：	Infineon
描述：	ADAPTIVE BALLAST CONTROL IC 自适应镇流器控制IC
文件：	总17页 (文件大小：334K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Data Sheet No. PD60212 revC

IR2520D(S) & (PbF)

ADAPTIVE BALLAST CONTROL IC

Packages

Features

• 600V Half Bridge Driver

• Integrated Bootstrap FET

• Adaptive zero-voltage switching (ZVS)

• Internal Crest Factor Over-Current Protection

• 0 to 6VDC Voltage Controlled Oscillator

• Programmable minimum frequency

• Micropower Startup Current (80uA)

• Internal 15.6V zener clamp on Vcc

• Small DIP8/SO8 Package

8 Lead SOIC

IR2520DS

8-Lead PDIP

IR2520D

• Also available LEAD-FREE (PbF)

Description

The IR2520D(S) is a complete adaptive ballast controller and 600V half-bridge driver integrated into a single

IC for fluorescent lighting applications. The IC includes adaptive zero-voltage switching (ZVS), internal crest

factor over-current protection, as well as an integrated bootstrap FET. The heart of this IC is a voltage con-

trolled oscillator with externally programmable minimum frequency. All of the necessary ballast features are

integrated in a small 8-pin DIP or SOIC package.

Typical Application Diagram

RSUPPLY

DCP2

SPIRAL

CFL

BR1

MHS

VCC

LRES

CVCC

COM

CBUS

CDC

CSNUB

CBS

MLS

FMIN

RFMIN

CRES

VCO

CVCO

DCP1

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IR2520D(S)&(PbF)

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-

eters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance

and power dissipation ratings are measured under board mounted and still air conditions.

Symbol

Definition

Min.

Max.

Units

High side floating supply voltage

-0.3

625

High side floating supply offset voltage

High side floating output voltage

Low side output voltage

- 25

+ 0.3

- 0.3

-0.3

-5

Voltage controlled oscillator input current (Note 1)

Supply current (Note 2)

+ 5

VCO

-25

-50

—

dV /dt

Allowable offset voltage slew rate

V/ns

Package power dissipation @ T ≤ +25°C

8-Lead PDIP

PD=(T

-T )Rth

A JA

8-Lead SOIC

8-Lead PDIP

8-Lead SOIC

—

0.625

125

200

150

300

JMAX

Rth

Thermal resistance, junction to ambient

—

°C/W

—

Junction temperature

-55

—

°C

Storage temperature

Lead temperature (soldering, 10 seconds)

Note 1: This IC contains a zener clamp structure between the chip VCO and COM, which has a nominal breakdown voltage

of 6V. Please note that this pin should not be driven by a DC, low impedance power source greater than 6V.

Note 2: This IC contains a zener clamp structure between the chip VCC and COM, which has a nominal breakdown voltage

of 15.6V. Please note that this supply pin should not be driven by a DC, low impedance power source greater than the

VCLAMP specified in the Electrical Characteristics section.

Recommended Operating Conditions

For proper operation the device should be used within the recommended conditions.

Symbol

Definition

Min.

Max.

Units

High side floating supply voltage

- 0.7

CLAMP

600

Steady state high side floating supply offset voltage

Supply voltage

-1

CCUV+

CLAMP

Supply current

Note 3

kΩ

Minimum frequency setting resistance

VCO pin voltage

140

FMIN

VCO

Junction temperature

-25

125

°C

Note 3: Enough current should be supplied into the VCC pin to keep the internal 15.6V zener clamp diode on this pin

regulating its voltage,

VCLAMP.

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IR2520D(S) &(PbF)

Electrical Characteristics

V V V

CC = BS = BIAS

= 14V +/- 0.25V, C =C =1000pF, R

LO HO

= 82kΩ and T = 25°C unless otherwise specified.

FMIN

Symbol

Definition

Min. Typ. Max. Units Test Conditions

Supply Characteristics

and V supply undervoltage positive going

11.4

9.0

12.6

10.0

13.8

11.0

rising from OV

CCUV+

threshold

V and V supply undervoltage negative going

CCUV-

threshold

supply undervoltage lockout hysteresis

—

2.7

—

UVHYS

UVLO quiescent current

Fault mode quiescent current

= 10V

=0V

QCCUV

µA

—

100

4.5

2.0

15.4

QCCFLT

supply current f=85KHz

supply current f=35KHz

Zener clamp voltage

—

CCHF

VCO

—

=6V

CCLF

VCO

14.4

= 10mA

CLAMP

Floating Supply Characteristics

Quiescent V supply current

—

150

=10V, V =14V

CC BS

QBS0

µA

Quiescent V supply current

=10V, V =7V

CC BS

QBSUV

BSUV+

BSUV-

VBS supply undervoltage positive going threshold

VBS supply undervoltage negative going threshold

Offset supply leakage current

7.7

6.8

—

9.0

8.0

—

10.3

9.2

µA

V = V = 600V

B S

Oscillator I/O Characteristics

29.6

—

2.0

1.3

1.1

38.2

—

=6V

=0V

Minimum oscillator frequency (Note 4)

Maximum oscillator frequency (Note 4)

Oscillator duty cycle

VCO

(min)

kHz

f₍

VCO

max)

LO output deadtime

—

µS

HO output deadtime

—

quick start

—

=0V

=2V

VCOQS

VCO

frequency sweep

when VCO is at 5V

0.8

—

1.7

—

µA

VCOFS

VCO

VCO_

Maximum VCO voltage

—

VCO_max

Gate Driver Output Characteristics

—

COM

VCC

150

—

LO output voltage when LO is low

HO output voltage when HO is low

LO output voltage when LO is high

HO output voltage when HO is high

Turn on rise time

LO=LOW

HO=LOW

—

LO=HIGH

—

HO=HIGH

RISE

230

120

—

FALL

Turn off fall time

IO+

IO-

Output source short circuit pulsed current

Output sink short circuit pulse current

140

230

—

Note 4: Frequency shown is nominal for R

=82kΩ. Frequency can be programmed higher or lower with the value of R

FMIN

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IR2520D(S)&(PbF)

Electrical Characteristics

V V

CC = BS = BIAS

= 14V +/- 0.25V, C =C =1000pF, R

LO HO

= 82kΩ and T = 25°C unless otherwise specified.

FMIN

Symbol

Definition

Min. Typ. Max. Units Test Conditions

Protection Characteristics

VCO voltage when entering run mode

—

4.8

—

VCO_RUN

CSCF

Crest factor peak-to-average fault factor

Maximum crest factor VS offset voltage

5.0

3.0

N/A

V offset = 0.5V

VS_

OFFSET_MAX

VCO

shutdown voltage

0.74

0.82

0.91

VCOSD

Minimum Frequency Setting Characteristics

FMIN lead voltage during normal operation

FMIN lead voltage during fault mode

4.8

—

5.1

5.4

—

FMIN

FMINFLT

Bootstrap FET

0.1uF,

IBS1

VB current

—

CBS=

VS=0V

IBS2

VB current

VBS = 10V

Lead Definitions

Symbol Description

VCC

COM

FMIN

VCO

Supply voltage

VCC

COM

FMIN

VCO

IC power and signal ground

Minimum frequency setting

Voltage controlled oscillator input

Low-side gate driver output

High-side floating return

7 HO

High-side gate driver output

High-side gate driver floating supply

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IR2520D(S) &(PbF)

Block Diagram

Bootstrap

FET

VCC

Bootstrap

FET

15.6V

Control

COM

I_FMAX

I_FMIN

I_VCO

I_QS

UVLO

High-Voltage Well

VCO

VS-Sensing

FET

SET

RST

Level

Shift

5.1V

Level-Shift

FETs

VCC

Driver

Logic

HIN

LIN

PGEN

I_DT

300ns

PGEN

Fault

Logic

0.8V

1us

blank

VCC

Averaging

Circuit

x 5

UVLO

4.8V

120uA

I_FMIN=

R_RFMIN

FMIN

All values are typical

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IR2520D(S)&(PbF)

State Diagram

Power Turned

VCCUV Mode

¹/₂-Bridge Off

I_{QCC ≅}

µA

V_VCO= 0V

VCC < 10V

V_FMIN= 0V

(VCCUV-)

FAULT

VCC > 12.6V

Mode

(VCCUV+)

-Bridge Off

V_VCO= 0V

≅

I_QCCFLT

µA

100

V_FMIN= 0V

VCC < 10V

Frequency Sweep Mode

(VCCUV-)

Crest Factor > 5.0

V_FMIN= 5.1V

(CSCF)

VCO ramps up, frequency ramps down

V_VCO< 0.82V

Crest Factor Disabled

ZVS Disabled

(V_VCOSD

)

V_VCO>4.8V

(V_VCO_RUN)

RUN Mode

Crest Factor Enabled

ZVS Enabled

_VCO= 6.0V, Frequency = fmin

If non-ZVS detected then V_VCOdecreases

and frequency increases to maintain ZVS

All values are typical

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IR2520D(S) &(PbF)

Functional Description

high-side driver is enabled. During UVLO mode, the high- and

low-side gate driver outputs, HO and LO, are both low and

pin VCO is pulled down to COM for resetting the starting

frequency to the maximum.

Under-voltage Lock-Out Mode

The under-voltage lock-out mode (UVLO) is defined as the

state the IR2520D is in when VCC is below the turn-on

threshold of the IC. The IR2520D UVLO is designed to main-

Frequency Sweep Mode

tain an ultra-low supply current (I

<80uA), and to

QCCUV

When VCC exceeds V

threshold, the IR2520D enters

CCUV+

guarantee that the IR2520D is fully functional before the

high- and low-side output gate drivers are activated. The

VCC capacitor, CVCC, is charged by current through sup-

ply resistor, RSUPPLY, minus the start-up current drawn by

the IR2520D (Figure 1). This resistor is chosen to provide

sufficient current to supply the IR2520D from the DC bus.

Once the capacitor voltage on VCC reaches the start-up

frequency sweep mode. An internal current source (Figure

2) charges the external capacitor on pin VCO, CVCO, and

the voltage on pin VCO starts ramping up linearly. An addi-

tional quick-start current (I

) is also connected to the

VCOQS

VCO pin and charges the VCO pin initially to 0.85V. When the

VCO voltage exceeds 0.85V, the quick-start current is then

disconnected internally and the VCO voltage continues to

charge up with the normal frequency sweep current source

threshold, V

, the IR2520D turns on and HO and LO

start oscillating. Capacitor CVCCshould be large enough to

CCUV+

(I ) (Figure 3). This quick-start brings the VCO voltage

VCOFS

hold the voltage at VCC above the V

threshold for

CCUV+

quickly to the internal range of the VCO. The frequency ramps

down towards the resonance frequency of the high-Q bal-

last output stage causing the lamp voltage and load current to

increase. The voltage on pin VCO continues to increase and

the frequency keeps decreasing until the lamp ignites. If the

lamp ignites successfully, the voltage on pin VCO continues

one half-cycle of the line voltage or until the external auxil-

iary supply can maintain the required supply voltage and

current to the IC.

DCBUS(+)

to increase until it internally limits at 6V (V

). The

VCO_MAX

RSUPPLY

frequency stops decreasing and stays at the minimum fre-

quency as programmed by an external resistor, RFMIN, on

pin FMIN. The minimum frequency should be set below the

high-Q resonance frequency of the ballast output stage to

ensure that the frequency ramps through resonance for lamp

ignition (Figure 4). The desired preheat time can be set by

adjusting the slope of the VCO ramp with the external capaci-

tor CVCO.

DCP2

MHS

VCC

COM

FMIN

VCO

Bootstrap

FET

CVCC

Driver

TO LOAD

High-

and

15.6V

CLAMP

Low-

side

CBS

CSNUB

VCC

UVLO

Driver

RFMIN

CVCO

MLS

DCBUS(+)

DCP1

RSUPPLY

DCP2

DCBUS(-)

LOAD RETURN

MHS

VCC

COM

FMIN

VCO

Bootstrap

FET

Fig. 1 Start-up circuitry

CVCC

Driver

TO LOAD

High-

and

An internal bootstrap MOSFET between VCC and VB and

external supply capacitor, CBS, determine the supply volt-

age for the high-side driver circuitry. An external charge

pump circuit consisting of capacitor CSNUBand diodes DCP1

and DCP2, comprises the auxiliary supply voltage for the

low-side driver circuitry. To guarantee that the high-side

supply is charged up before the first pulse on pin HO, the

first pulse from the output drivers comes from the LO pin.

LO may oscillate several times until VB-VS exceeds the

15.6V

CLAMP

Low-

side

CBS

CSNUB

Driver

VCO

RFMIN

CVCO

MLS

DCP1

LOAD RETURN

DCBUS(-)

high-side UVLO rising threshold, V

(9 Volts), and the

BSUV+

Fig. 2 Frequency sweep circuitry mode circuitry

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IR2520D(S)&(PbF)

VCO

Run Mode

The IR2520D enters RUN mode when the voltage on pin

4.8V

VCO exceeds 4.8V (V

). The lamp has ignited and

VCO_RUN

the ballast output stage becomes a low-Q, series-L, paral-

lel-RC circuit. Also, the VS sensing and fault logic blocks

(Figure 5) both become enabled for protection against non-

ZVS and over-current fault conditions. The voltage on the

VCO pin continues to increase and the frequency deceases

0.85V

further until the VCO pin voltage limits at 6V (V

)

VCO_MAX

and the minimum frequency is reached. The resonant in-

ductor, resonant capacitor, DC bus voltage and minimum

frequency determine the running lamp power. The IC stays

at this minimum frequency unless non-ZVS occurs at the

VS pin, a crest factor over-current condition is detected at

the VS pin, or VCC decreases below the UVLO- threshold

(see State Diagram).

Frequency Sweep Mode

Run Mode

Freq

fmax

fmin

DCBUS(+)

RSUPPLY

Fig. 3 IR2520D Frequency sweep mode timing

diagram.

DCP2

MHS

VCC

COM

FMIN

VCO

Bootstrap

FET

CVCC

Driver

TO LOAD

High-

and

15.6V

CLAMP

Low-

side

CBS

CSNUB

Driver

VCO

RFMIN

Fault

Logic

CVCO

MLS

Sense

High -Q

Vout

Vin

Ignition

DCP1

LOAD RETURN

DCBUS(-)

Fig. 5 IR2520D Run mode circuitry.

Run

Non Zero-Voltage Switching (ZVS) Protection

Start

Low -Q

During run mode, if the voltage at the VS pin has not slewed

entirely to COM during the dead-time such that there is

voltage between the drain and source of the external low-

side half-bridge MOSFET when LO turns-on, then the system

is operating too close to, or, on the capacitive side of,

resonance. The result is non-ZVS capacitive-mode

switching that causes high peak currents to flow in the

half-bridge MOSFETs that can damage or destroy them

(Figure 6). This can occur due to a lamp filament failure(s),

fmin

fmax

Frequency

Fig. 4 Resonant tank Bode plot with lamp operating

points.

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IR2520D(S) &(PbF)

lamp removal (open circuit), a dropping DC bus during a

mains brown-out or mains interrupt, lamp variations over

time, or component variations. To protect against this, an

internal high-voltage MOSFET is turned on at the turn-off of

HO and the VS-sensing circuit measures VS at each rising

edge of LO. If the VS voltage is non-zero, a pulse of current

is sinked from the VCO pin (Figures 5 and 6) to slightly

discharge the external capacitor, CVCO, causing the

frequency to increase slightly. The VCO capacitor then

charges up during the rest of the cycle slowly due to the

internal current source.

open circuit (Figure 7). This will cause capacitive switching

(hard-switching) resulting in high peak MOSFET currents

that can damage them. The IR2520D will increase the fre-

quency in attempt to satisfy ZVS until the VCO pin de-

creases below 0.82V (V

). The IC will enter Fault

VCOSD

Mode and latch the LO and HO gate driver outputs ‘low’ for

turning the half-bridge off safely before any damage can

occur to the MOSFETs.

RUN MODE

FAULT MODE

V^LO

V^HO

V^LO

V^HO

V^VS

MLS

MHS

MLS

VCO

MHS

0.85V

Frequency shifted higher

until VCO < 0.82V. LO and

HO are latched low before

damage occurs to MOSFETs.

Capacitive switching. Hard-switching

and high peak MOSFET currents!

VCO

Too close to resonance.

Hard-switching and high

peak MOSFET currents!

Frequency shifted higher

to maintain ZVS.

Fig. 7 Lamp removal or open filament fault

condition timing diagram

Fig. 6 IR2520D non-ZVS protection timing diagram.

Crest Factor Over-current Protection

The frequency is trying to decrease towards resonance

by charging the VCO capacitor and the adaptive ZVS cir-

cuit “nudges” the frequency back up slightly above reso-

nance each time non-ZVS is detected at the turn-on of LO.

The internal high-voltage MOSFET is then turned off at the

turn-off of LO and it withstands the high-voltage when VS

slews up to the DC bus potential. The circuit then remains in

this closed-loop adaptive ZVS mode during running and

maintains ZVS operation with changing line conditions, com-

ponent tolerance variations and lamp/load variations. Dur-

ing a lamp removal or filament failure, the lamp resonant

tank will be interrupted causing the half-bridge output to go

During normal lamp ignition, the frequency sweeps through

resonance and the output voltage increases across the

resonant capacitor and lamp until the lamp ignites. If the

lamp fails to ignite, the resonant capacitor voltage, the inductor

voltage and inductor current will continue to increase until

the inductor saturates or the output voltage exceeds the

maximum voltage rating of the resonant capacitor or inductor.

The ballast must shutdown before damage occurs. To

protect against a lamp non-strike fault condition, the IR2520D

uses the VS-sensing circuitry (Figure 5) to also measure

the low-side half-bridge MOSFET current for detecting an

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IR2520D(S)&(PbF)

faults. This can occur when a half-bridge MOSFET is

selected that has an RDSon that is too large for the application

causing the internal average to exceed the maximum limit.

over-current fault. By using the RDSon of the external low-

side MOSFET for current sensing and the VS-sensing

circuitry, the IR2520D eliminates the need for an additional

current sensing resistor, filter and current-sensing pin. To

cancel changes in the RDSon value due to temperature and

MOSFET variations, the IR2520D performs a crest factor

measurement that detects when the peak current exceeds

the average current by a factor of 5 (CSCF). Measuring the

crest factor is ideal for detecting when the inductor saturates

due to excessive current that occurs in the resonant tank

when the frequency sweeps through resonance and the

lamp does not ignite. When the VCO voltage ramps up for

the first time from zero, the resonant tank current and

voltages increase as the frequency decreases towards

resonance (Figure 8). If the lamp does not ignite, the inductor

current will eventually saturate but the crest factor fault

protection is not active until the VCO voltage exceeds 4.8V

FAULT MODE

During Run Mode, should the VCO voltage decrease below

0.82V (V

) or a crest factor fault occur, the IR2520D

VCOSD

will enter Fault Mode (see State Diagram). The LO and HO

gate driver outputs are both latched ‘low’ so that the half-

bridge is disabled. The VCO pin is pulled low to COM and

the FMIN pin decreases from 5V to COM. VCC draws

micro-power current (I

) so that VCC stays at the

CCFLT

clamp voltage and the IC remains in Fault Mode without the

need for the charge-pump auxiliary supply. To exit Fault

Mode and return to Frequency Sweep Mode, VCC must be

cycled below the UVLO- threshold and back above the

UVLO+ threshold.

) for the first time. The frequency will continue

VCO_RUN

decreasing to the capacitive side of resonance towards

the minimum frequency setting and the resonant tank current

and voltages will decrease again. When the VCO voltage

exceeds 4.8V (V

), the IC enters Run Mode and

VCO_RUN

the non-ZVS protection and crest factor protection are both

enabled. The non-ZVS protection will increase the

frequency again cycle-by-cycle towards resonance from

the capacitive side. The resonant tank current will increase

again as the frequency nears resonance until the inductor

saturates again.

AVG*5

Inductor

saturation

MLS

INDUCTIVE SIDE

OF RESONANCE

CAPACITIVE SIDE

OF RESONANCE

The crest factor protection is now enabled and measures

the instantaneous voltage at the VS pin only during the time

when LO is ‘high’ and after an initial 1us blank time from the

rising edge of LO. The blank time is necessary to prevent

the crest factor protection circuit from reacting to a non-

ZVS condition. An internal averaging circuit averages the

instantaneous voltage at the VS pin over 10 to 20 switching

cycles of LO. During Run Mode, the first time the inductor

saturates when LO is ‘high’ (after the 1us blank time) and

the peak current exceeds the average by 5 (CSCF), the

IR2520D will enter Fault Mode and both LO and HO outputs

will be latched ‘low’. The half-bridge will be safely disabled

before any damage can occur to the ballast components.

4.6V

VCO

FREQUENCY SWEEP MODE

RUN MODE FAULT MODE

The crest factor peak-to-average fault factor varies as a

function of the internal average (Figure 20). The maximum

internal average should be below 3.0 volts. Should the

average exceed this amount, the multiplied average voltage

can exceed the maximum limit of the VS sensing circuit and

the VS sensing circuit will no longer detect crest factor

Fig. 8 Crest factor protection timing diagram

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IR2520D(S) &(PbF)

VCCUV+

VCCUV-

-25

75 100 125

-25

100

125

Temperature(C)

Temperature(°C)

Fig. 10 IQCCUV vs TEMP

VCC=10V, VCO=0V

Fig. 9 VCCUV+/- vs TEMP

100

VBSUV+

VBSUV-

-25

100

125

-25

100

125

Temperature(°C)

Fig. 12 IQBSUV vs TEMP

Fig. 11 VBSUV+/- vs TEMP

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IR2520D(S)&(PbF)

100

VVCO=0V

100

120

140

VVCO=5V

-25

25 50 75 100 125

-25

100

125

Temperature(C)

Fig. 13 Frequency vs TEMP

REMIN=82K

Fig. 14 Frequency vs RFMIN vs TEMP

VVCO=6V

100

-25

125

Temperature(C)

VCO(V)

Fig. 16 FREQ VS VCC vs TEMP

VVCO=0V

Fig. 15 FREQ VS VVCO vs TEMP

VCC=14V

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IR2520D(S) &(PbF)

2.5

1.8

1.6

1.4

1.2

TDHO

TDLO

1.5

0.8

0.6

0.4

0.2

0.5

-25

100

125

-25

100

125

Temperature(°C)

Fig. 17 DTHO, DTLO vs TEMP

VCO=0V

Fig. 18 IVCO_FS vs TEMP

6.5

5.5

0.2

0.4

0.6

0.8

-25

100

125

VS OFFSET(V)

Temperature(C)

Fig. 20 CSCF vs OFFSET

Fig. 19 VVCOMAX vs TEMP

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IR2520D(S)&(PbF)

1.5

1.25

0.75

0.5

0.25

-25

100

125

-25

100

125

Temperature (°C)

Temperature(°C)

Fig. 22 VVCO_SD vs TEMP

Fig. 21 CSCF vs TEMP

VS_OFFSET=0.5V

100

-25

100

125

-25

100

125

Temperature(C)

(

Temperature(°C)

)

Fig. 24 IBS1 vs TEMP

Fig. 23 VFMIN vs TEMP

VCO=0V, RFMIN=82K

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IR2520D(S) &(PbF)

-25

100

125

Temperature(°C)

Fig. 26 IBS2 vs TEMP

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IR2520D(S)&(PbF)

Case outlines

01-6014

01-3003 01 (MS-001AB)

IR2520D 8-Lead PDIP

INC HES

MILLIMETERS

DIM

MIN

.0532

A1 .0040

MAX

.0688

.0098

.020

MIN

1.35

0.10

0.33

0.19

4.80

3.80

MAX

1.75

0.25

0.51

0.25

5.00

4.00

FOOTPRINT

8X 0.72 [.028]

.013

.0075

.189

.1497

.0098

.1968

.1574

0.25 [.010]

.050 BASIC

1.27 BASIC

0.635 BASIC

6.46 [.255]

e 1 .025 BASIC

.2284

.0099

.016

0°

.2440

.0196

.050

8°

5.80

0.25

0.40

0°

6.20

0.50

1.27

8°

3X 1.27 [.050]

8X 1.78 [.070]

K x 45°

0.10 [.004]

8X c

8X L

8X b

0.25 [.010]

NOTES:

DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.

MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].

DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.

MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].

DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO

A SUBSTRATE.

1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.

2. CONTROLLING DIMENSION: MILLIMETER

3. DIMENSIONS ARE SHOWN IN MILLIMETERS [INCHES].

4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA.

01-6027

IR2520DS

8-Lead SOIC

01-0021 11 (MS-012AA)

www.irf.com

IR2520D(S) &(PbF)

LEADFREE PART MARKING INFORMATION

Part number

Date code

IRxxxxxx

YWW?

IR logo

?XXXX

Pin 1

Identifier

Lot Code

(Prod mode - 4 digit SPN code)

MARKING CODE

Lead Free Released

Non-Lead Free

Released

Assembly site code

Per SCOP 200-002

ORDER INFORMATION

Basic Part (Non-Lead Free)

Leadfree Part

8-Lead PDIP IR2520D order IR2520D

8-Lead SOIC IR2520DS order IR2520DS

8-Lead PDIP IR2520D order IR2520DPbF

8-Lead SOIC IR2520DS order IR2520DSPbF

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105

This product has been qualified per industrial level MSL-3

Data and specifications subject to change without notice. 3/1/2005

www.irf.com

IR2520DPBF [INFINEON]

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