IR3081AM_技术文档

IR3081A

DATA SHEET

XPHASE^TMVR 10 CONTROL IC

DESCRIPTION

The IR3081A Control IC combined with an IR XPhase^TMPhase IC provides a full featured and flexible way

to implement a complete VR 10 power solution. The “Control” IC provides overall system control and

interfaces with any number of “Phase ICs” which each drive and monitor a single phase of a multiphase

converter. The XPhase^TMarchitecture results in a power supply that is smaller, less expensive, and easier

to design while providing higher efficiency than conventional approaches. The IR3081A is intended for

VRD 10 or VRM/EVRD 10 applications that use external VCCVID/VTT circuits.

The IR3081A is functionally equivalent to the IR3081, but incorporates the following modifications:

•

Under Voltage Lockout start threshold increased from 9.1V to 9.7V (typical) and hysteresis increased

from 200mV to 800mV (typical).

•

Hysteresis (52mV typical) added to the SS/DEL comparator to prevent Power Good output chatter.

Over current discharge current increased from 6uA to 40uA (typical) to reduce the over current delay

time.

•

IIN pin precondition circuit added to disable current sharing in the phase ICs during soft start.

FEATURES

•

6 bit VR 10 compatible VID with 0.5% overall system accuracy

1 to X phases operation with matching phase ICs

Programmable Dynamic VID Slew Rate

No Discharge of output capacitors during Dynamic VID step-down (can be disabled)

+/-300mV Differential Remote Sense

Programmable 150kHz to 1MHz oscillator

Programmable VID Offset and Load Line output impedance

Programmable Softstart

Programmable Hiccup Over-Current Protection with Delay to prevent false triggering

Simplified Powergood provides indication of proper operation and avoids false triggering

Operates from 12V input with 9.1V Under-Voltage Lockout

6.8V/5mA Bias Regulator provides System Reference Voltage

Enable Input

Small thermally enhanced 28L MLPQ package

Page 1 of 39

1/31/05

IR3081A

APPLICATION CIRCUIT

RVCC

10 ohm

12V

CVCC

0.1uF

POWERGOOD

ENABLE

RMPOUT

VBIAS

1

21

20

19

18

17

16

15

0.1uF

OSCDS

VBIAS

BBFB

EAOUT

FB

2

VID5

VID0

VID5

3

IR3081A

CONTROL

IC

EA

VID0

CCP

RCP

4

VID1

VID2

VID3

VID1

5 Wire Analog Bus

to Phase ICs

5

VID2

VDRP

IIN

CDRP

RDRP1

RDRP

6

CCP1

VID3

7

VID4

OCSET

ISHARE

VDAC

ROCSET

CFB

ROSC

RVDAC

CVDAC

RFB1

RFB

VOSENSE+

VOSENSE-

Remote Sense

ORDERING INFORMATION

Device

Order Quantity

3000 per reel

IR3081AMTR

IR3081AM

100 piece strips

Page 2 of 39

1/31/05

IR3081A

ABSOLUTE MAXIMUM RATINGS

Operating Junction Temperature……………..150^oC

Storage Temperature Range………………….-65^oC to 150^oC

ESD Rating………………………………………HBM Class 1C JEDEC standard

PIN #

1

2-7

PIN NAME

OSCDS

VID0-5

V_MAX

20V

V_MIN

-0.3V

I_SOURCE

1mA

10mA

I_SINK

1mA

10mA

8, 9,

TRM1-4

Do Not Connect

11,12

10

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

VOSNS-

ROSC

VDAC

OCSET

IIN

VDRP

FB

EAOUT

BBFB

VBIAS

VCC

LGND

RMPOUT

SS/DEL

PWRGD

N/C

0.5V

20V

10V

20V

n/a

-0.5V

-0.3V

n/a

10mA

1mA

5mA

1mA

10mA

1mA

50mA

1mA

n/a

10mA

1mA

5mA

1mA

20mA

1mA

50mA

1mA

20mA

n/a

20V

n/a

-0.3V

n/a

ENABLE

20V

-0.3V

1mA

Page 3 of 39

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IR3081A

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, these specifications apply over: 9.5V ≤ V_CC≤ 14V, 0 ^oC ≤ T_J≤ 100 ^oC

PARAMETER

TEST CONDITION

MIN

TYP

MAX

UNIT

VDAC Reference

System Set-Point Accuracy

-0.3V ≤ VOSNS- ≤ 0.3V, Connect FB to

EAOUT, Measure V(EAOUT) –

V(VOSNS-) deviation from Table 1.

Applies to all VID codes.

R_ROSC= 41.9kΩ

0.5

%

Source Current

Sink Current

VID Input Threshold

VID Input Bias Current

68

47

500

-5

80

55

600

0

92

63

700

5

µA

mV

µA

mV

0V ≤ VID0-5 ≤ VCC

Regulation Detect Comparator

Input Offset

-5

0

5

Regulation Detect to EAOUT

130

200

ns

Delay

BBFB to FB Bias Current

Ratio

0.95

1.00

1.05

µA/µA

VID 11111x Blanking Delay

Measure Time till PWRGD drives low

Measure from VID inputs to EAOUT

800

1.7

ns

µs

VID Step Down Detect

Blanking Time

VID Down BB Clamp Voltage

VID Down BB Clamp Current

Error Amplifier

Percent of VDAC voltage

70

3.5

75

6.2

80

12

%

mA

Input Offset Voltage

Connect FB to EAOUT, and measure

V(EAOUT) – V(DAC). Applies to all VID

codes from table 1 and -0.3V ≤ VOSNS-

≤ 0.3V. Note 2

R_ROSC= 41.9kΩ

Note 1

-3

4

8

mV

FB Bias Current

DC Gain

Gain-Bandwidth Product

Source Current

Sink Current

Max Voltage

Min Voltage

-31

90

4

0.4

0.7

125

30

-29.5

100

7

0.6

1.2

250

100

600

-28

105

µA

dB

Note 1

MHz

mA

mV

0.8

1.7

375

150

750

VBIAS–VEAOUT (referenced to VBIAS)

Normal operation or Fault mode

IIN Precondition Reset

450

Comparator Threshold

VDRP Buffer Amplifier

Input Offset Voltage

Bandwidth (-3dB)

Slew Rate

V(VDRP) – V(IIN), 0.8V ≤ V(IIN) ≤ 5.5V

Note 1

-13

1

-2

6

10

-0.75

600

6

mV

MHz

V/µs

µA

IIN Bias Current

-2.0

350

0

850

IIN Precondition Set

Difference of preconditioning active

voltage and SS/DEL-FB offset voltage

SS/DEL=0V.

mV

Comparator Threshold Offset

IIN Precondition Pull Down

7.5

15

22.5

KΩ

Resistance

Page 4 of 39

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IR3081A

PARAMETER

TEST CONDITION

R_ROSC= 41.9kΩ

MIN

TYP

MAX

UNIT

Oscillator

Switching Frequency

255

70

300

71

345

74

kHz

%

Peak Voltage (5V typical,

R_ROSC= 41.9kΩ

measured as % of VBIAS)

Valley Voltage (1V typical,

measured as % of VBIAS)

R_ROSC= 41.9kΩ

11

14

16

%

VBIAS Regulator

Output Voltage

Current Limit

-5mA ≤ I(VBIAS) ≤ 0

6.5

-30

6.8

-15

7.1

-6

V

mA

Soft Start and Delay

SS/DEL to FB Input Offset

With FB = 0V, adjust V(SS/DEL) until

EAOUT drives high

0.85

1.3

1.5

V

Voltage

Charge Current

Discharge Current

40

4

10

70

6

11.5

100

9

13

µA

µA/µA

Charge/Discharge Current

Ratio

Charge Voltage

3.5

3.8

40

4.0

V

uA

Over Current Discharge

Current

Over Current Delay Time

CSS/DEL=0.1uF. Note 1

150

35

250

65

350

95

us

mV

Delay Comparator Threshold

Relative to Charge Voltage, SS/DEL

rising

Delay Comparator Threshold

Relative to Charge Voltage, SS/DEL

falling

85

32

115

52

145

72

mV

Delay Comparator Hysteresis

Over-Current Comparator

Input Offset Voltage

OCSET Bias Current

PWRGD Output

Output Voltage

Leakage Current

Enable Input

Threshold voltage

Bias Current

1V ≤ V(OCSET) ≤ 5V

R_ROSC= 41.9kΩ

-10

-31

0

10

-28

mV

µA

-29.5

I(PWRGD) = 4mA

V(PWRGD) = 5.5V

150

0

400

10

mV

µA

500

-5

600

0

700

5

mV

µA

0V ≤ V(ENABLE) ≤ VCC

VCC Under-Voltage Lockout

Start Threshold

Stop Threshold

Hysteresis

9.2

8.4

600

9.7

8.9

800

10.2

9.4

1200

V

mV

Start – Stop

General

VCC Supply Current

VOSNS- Current

8

-5.5

11

-4.5

14

-3.5

mA

-0.3V ≤ VOSNS- ≤ 0.3V, All VID Codes

Note 1: Guaranteed by design, but not tested in production

Note 2: VDAC Output is trimmed to compensate for Error Amplifier input offset errors

Page 5 of 39

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IR3081A

PIN DESCRIPTION

PIN# PIN SYMBOL PIN DESCRIPTION

1

OSCDS

Apply a voltage greater than VBIAS to disable the oscillator. Used during factory

testing & trimming. Ground or leave open for normal operation.

Inputs to VID D to A Converter

2-7

VID0-5

8, 9,

TRM1-4

Used for precision post-package trimming of the VDAC voltage. Do not make any

11,12

connection to these pins.

10

13

VOSNS-

ROSC

Remote Sense Input. Connect to ground at the Load.

Connect a resistor to VOSNS- to program oscillator frequency and FB, OCSET,

BBFB, and VDAC bias currents

14

VDAC

Regulated voltage programmed by the VID inputs. Current Sensing and PWM

operation are referenced to this pin. Connect an external RC network to VOSNS- to

program Dynamic VID slew rate.

15

OCSET

Programs the hiccup over-current threshold through an external resistor tied to

VDAC and an internal current source. Over-current protection can be disabled by

connecting this pin to a DC voltage no greater than 6.5V (do not float this pin as

improper operation will occur).

16

IIN

Current Sense input from the Phase IC(s). To ensure proper operation bias to at

least 250mV (don’t float this pin). The pin is clamped to ground during the early

stage of soft start to disable current sharing function in the phase ICs.

17

18

VDRP

FB

Buffered IIN signal. Connect an external RC network to FB to program converter

output impedance

Inverting input to the Error Amplifier. Converter output voltage is offset from the

VDAC voltage through an external resistor connected to the converter output voltage

at the load and an internal current source.

19

20

EAOUT

BBFB

Output of the Error Amplifier

Input to the Regulation Detect Comparator. Connect to converter output voltage and

VDRP pin through resistor network to program recovery from VID step-down.

Connect to ground to disable Body Braking^TMduring transition to a lower VID code.

21

VBIAS

6.8V/5mA Regulated output used as a system reference voltage for internal circuitry

and the Phase ICs.

22

23

24

25

VCC

LGND

RMPOUT

SS/DEL

Power for internal circuitry

Local Ground and IC substrate connection

Oscillator Output voltage. Used by Phase ICs to program Phase Delay

Controls Converter Softstart, Power Good, and Over-Current Delay Timing. Connect

an external capacitor to LGND to program the timing. An optional resistor can be

added in series with the capacitor to reduce the over-current delay time.

26

PWRGD

Open Collector output that drives low during Softstart and any external fault

condition. Connect external pull-up.

27

28

N/C

ENABLE

No internal connection

Enable Input. A logic low applied to this pin puts the IC into Fault mode.

Page 6 of 39

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IR3081A

SYSTEM THEORY OF OPERATION

XPhase^TMArchitecture

The XPhase^TMarchitecture is designed for multiphase interleaved buck converters which are used in applications

requiring small size, design flexibility, low voltage, high current and fast transient response. The architecture can

control converters of any phase number where flexibility facilitates the design trade-off of multiphase converters.

The scalable architecture can be applied to other applications which require high current or multiple output voltages.

As shown in Figure 1, the XPhase^TMarchitecture consists of a Control IC and a scalable array of phase converters

each using a single Phase IC. The Control IC communicates with the Phase ICs through a 5-wire analog bus, i.e.

bias voltage, phase timing, average current, error amplifier output, and VID voltage. The Control IC incorporates all

the system functions, i.e. VID, PWM ramp oscillator, error amplifier, bias voltage, and fault protections etc. The

Phase IC implements the functions required by the converter of each phase, i.e. the gate drivers, PWM comparator

and latch, over-voltage protection, and current sensing and sharing.

There is no unused or redundant silicon with the XPhase^TMarchitecture compared to others such as a 4 phase

controller that can be configured for 2, 3, or 4 phase operation. PCB Layout is easier since the 5 wire bus

eliminates the need for point-to-point wiring between the Control IC and each Phase. The critical gate drive and

current sense connections are short and local to the Phase ICs. This improves the PCB layout by lowering the

parasitic inductance of the gate drive circuits and reducing the noise of the current sense signal.

POWER GOOD

PHASE FAULT

VR HOT

GATE VOLTAGE

12V

REGULATOR

ENABLE

PHASE FAULT

VID5

IR3081A

CONTROL

IC

>> BIAS VOLTAGE

>> PHASE TIMING

<< CURRENT SENSE

>> PWM CONTROL

>> VID VOLTAGE

BIAS VOLTAGE

PHASE TIMING

CURRENT SHARE

PWM CONTROL

VID VOLTAGE

PHASE HOT

VID0

VID1

VID2

VID3

VID4

CIN

VOUT SENSE+

VOUT+

IR3086A

PHASE IC

0.1uF

COUT

VOUT-

CCS RCS

VOUT SENSE-

PHASE FAULT

BIAS VOLTAGE

PHASE TIMING

CURRENT SHARE

PWM CONTROL

VID VOLTAGE

PHASE HOT

IR3086A

PHASE IC

0.1uF

CCS RCS

ADDITIONAL PHASES

OCOCOCOC

OCOC

OCOCOC

INPUT/OUTPUT

OC

CONTROL BUS

Figure 1. System Block Diagram

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IR3081A

PWM Control Method

The PWM block diagram of the XPhase^TMarchitecture is shown in Figure 2. Feed-forward voltage mode control with

trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used

for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to program the

slope of the PWM ramp and to provide the feed-forward control at each phase. The PWM ramp slope will change

with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change

due to variations in the silver box output voltage or due to the wire and PCB-trace voltage drop related to changes

in load current.

VIN

CONTROL IC

PHASE IC

SYSTEM

REFERENCE

VOLTAGE

BIASIN

PWM

LATCH

50%

DUTY

CYCLE

RAMP GENERATOR

RAMPIN+

GATEH

GATEL

+

VPEAK

CLOCK

PULSE

GENERATOR

RMPOUT

VOSNS+

VOUT

S

-

PWM

COMPARATOR

RESET

DOMINANT

RPHS1

RAMPIN-

EAIN

VVALLEY

-

COUT

R

+

VBIAS

VDAC

GND

RPHS2

ENABLE

+

-

PWMRMP

SCOMP

+

RPWMRMP

VBIAS

REGULATOR

BODY

-

BRAKING

COMPARATOR

RAMP

DISCHARGE

CLAMP

VOSNS-

EAOUT

VOSNS-

CPWMRMP

VDAC

+

-

SHARE

ADJUST

ERROR

CSCOMP

X

0.91

AMPLIFIER

ERROR

AMP

RVFB

RDRP

CURRENT

SENSE

AMPLIFIER

+

ISHARE

DACIN

FB

CSIN+

CSIN-

10K

20mV

+

-

CCS RCS

-

IFB

IROSC

X34

VDRP

AMP

+

VDRP

-

IIN

PHASE IC

SYSTEM

REFERENCE

VOLTAGE

BIASIN

PWM

LATCH

RAMPIN+

GATEH

GATEL

+

-

CLOCK

PULSE

GENERATOR

S

RPHS1

RPHS2

PWM

RESET

RAMPIN-

EAIN

COMPARATOR ^DOMINANT

-

R

+

ENABLE

PWMRMP

SCOMP

+

RPWMRMP

BODY

BRAKING

COMPARATOR

-

RAMP

DISCHARGE

CLAMP

CPWMRMP

SHARE

ADJUST

CSCOMP

ERROR

X

AMPLIFIER

0.91

CURRENT

SENSE

AMPLIFIER

+

ISHARE

DACIN

CSIN+

CSIN-

10K

20mV

+

-

CCS RCS

-

X34

Figure 2. PWM Block Diagram

Frequency and Phase Timing Control

The oscillator is located in the Control IC and its frequency is programmable from 150kHz to 1MHZ by an external

resistor. The output of the oscillator is a 50% duty cycle triangle waveform with peak and valley voltages of

approximately 5V and 1V respectively. This signal is used to program both the switching frequency and phase

timing of the Phase ICs. The Phase IC is programmed by resistor divider RPHS1 and RPHS2 connected between the

VBIAS reference voltage and the Phase IC LGND pin. A comparator in the Phase ICs detects the crossing of the

oscillator waveform over the voltage generated by the resistor divider and triggers a clock pulse that starts the PWM

cycle. The peak and valley voltages track the VBIAS voltage reducing potential Phase IC timing errors. Figure 3

shows the Phase timing for an 8 phase converter. Note that both slopes of the triangle waveform can be used for

phase timing by swapping the RMPIN+ and RMPIN– pins, as shown in figure 2.

Page 8 of 39

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IR3081A

50% RAMP

DUTY CYCLE

SLOPE

=

80mV

/

%

DC

ns

VPEAK (5.0V)

1.6mV

8.0mV

/

@

200kHz

1MHz

VPHASE4&5 (4.5V)

VPHASE3&6 (3.5V)

VPHASE2&7 (2.5V)

VPHASE1&8 (1.5V)

VVALLEY (1.00V)

CLK1

CLK2

CLK3

CLK4

CLK5

CLK6

CLK7

CLK8

Figure 3. 8 Phase Oscillator Waveforms

PWM Operation

The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is set; the PWMRMP

voltage begins to increase; the low side driver is turned off, and the high side driver is then turned on after the non-

overlap time. When the PWMRMP voltage exceeds the Error Amplifier’s output voltage, the PWM latch is reset.

This turns off the high side driver and then turns on the low side driver after the non-overlap time; it activates the

Ramp Discharge Clamp, which quickly discharges the PWMRMP capacitor to the VDAC voltage of the Control IC

until the next clock pulse.

The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in

response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step

increase with turn-on gated by the clock pulses. An Error Amplifier output voltage greater than the common mode

input range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This

arrangement guarantees the Error Amplifier is always in control and can demand 0 to 100% duty cycle as required.

It also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of

most systems. The inductor current will increase much more rapidly than decrease in response to load transients.

This control method is designed to provide “single cycle transient response” where the inductor current changes in

response to load transients within a single switching cycle maximizing the effectiveness of the power train and

minimizing the output capacitor requirements. An additional advantage of the architecture is that differences in

ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC.

Figure 4 depicts PWM operating waveforms under various conditions.

Page 9 of 39

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IR3081A

PHASE IC

CLOCK

PULSE

EAIN

PWMRMP

GATEH

GATEL

VDAC

91% VDAC

STEADY-STATE

OPERATION

DUTY CYCLE INCREASE

DUE TO LOAD

INCREASE

DUTY CYCLE DECREASE

DUE TO VIN INCREASE

(FEED-FORWARD)

DUTY CYCLE DECREASE DUE TO LOAD

DECREASE (BODY BRAKING) OR FAULT

(VCC UV, OCP, VID=11111X)

STEADY-STATE

OPERATION

Figure 4. PWM Operating Waveforms

Body Braking^TM

In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in

response to a load step decrease is;

L*(I_MAX− I_MIN

)

T_SLEW

=

V_O

The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in

response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the

synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout +

V_BODYDIODE

.

The minimum time required to reduce the current in the inductor in response to a load transient

decrease is now;

L*(I_MAX− I_MIN

=

)

T_SLEW

V_O+V_BODYDIODE

Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be

increased by 2X or more. This patent pending technique is referred to as “body braking” and is accomplished

through the “0% Duty Cycle Comparator” located in the Phase IC. If the Error Amplifier’s output voltage drops below

91% of the VDAC voltage this comparator turns off the low side gate driver.

Lossless Average Inductor Current Sensing

Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor

and measuring the voltage across the capacitor, as shown in Figure 5. The equation of the sensing network is,

1

R_L+ sL

1+ sR_CSC_CS

v_C(s) = v_L(s)

= i_L(s)

1+ sR_CSC_CS

Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time

constant of the inductor which is the inductance L over the inductor DCR. If the two time constants match, the

voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense

resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of

inductor DC current, but affects the AC component of the inductor current.

Page 10 of 39

1/31/05

IR3081A

L

v

L

R

L

i

O

V

CS

C

O

C

Current

Sense Amp

c

vCS

CSOUT

Figure 5. Inductor Current Sensing and Current Sense Amplifier

The advantage of sensing the inductor current versus high side or low side sensing is that actual output current

being delivered to the load is obtained rather than peak or sampled information about the switch currents. The

output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in

series with the inductor, this is the only sense method that can support a single cycle transient response. Other

methods provide no information during either load increase (low side sensing) or load decrease (high side sensing).

An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer

from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency

variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and

the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier

bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional

sources of peak-to-average errors.

Current Sense Amplifier

A high speed differential current sense amplifier is located in the Phase IC, as shown in Figure 5. Its gain decreases

with increasing temperature and is nominally 34 at 25ºC and 29 at 125ºC (-1470 ppm/ºC). This reduction of gain

tends to compensate the 3850 ppm/ºC increase in inductor DCR. Since in most designs the Phase IC junction is

hotter than the inductor these two effects tend to cancel such that no additional temperature compensation of the

load line is required.

The current sense amplifier can accept positive differential input up to 100mV and negative up to -20mV before

clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the Control IC and

other Phases through an on-chip 10KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the phases

are tied together and the voltage on the share bus represents the average current through all the inductors and is

used by the Control IC for voltage positioning and current limit protection.

Average Current Share Loop

Current sharing between phases of the converter is achieved by the average current share loop in each Phase IC.

The output of the current sense amplifier is compared with the share bus less a 20mV offset. If current in a phase is

smaller than the average current, the share adjust amplifier of the phase will activate a current source that reduces

the slope of its PWM ramp thereby increasing its duty cycle and output current. The crossover frequency of the

current share loop can be programmed with a capacitor at the SCOMP pin so that the share loop does not interact

with the output voltage loop.

Page 11 of 39

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IR3081A

IR3081A THEORY OF OPERATION

Block Diagram

The Block diagram of the IR3081A is shown in Fig. 6, and specific features are discussed in the following sections.

VCC UVLO

COMPARATOR

FAULT

LATCH

VCC

-

START

PWRGD

STOP

+

S

Q

+

-

9.7V

8.9V

DISCHARGE

COMPARATOR

+

0.2V

OVER

CURRENT

SET

DOMINANT

ENABLE

COMPARATOR

R

-

ENABLE

-

+

65mV

DELAY

IROSC

+

-

COMPARATOR

115mV

OVER CURRENT

COMPARATOR

IOCSET

0.6V

-

OCSET

IIN

+

-

+

-

VCHG

3.8V

+

SET THRESHOLD

0.7V (1.3-0.6V) PRECONDITION

IDISCHG

40uA

VDRP

PRECONDITION

LATCH

SET COMPARATOR

AMPLIFIER

+

S

Q

VDRP

OCICHG

-

10k

RESET

DOMINANT

ON

PRECONDITION

IDISCHGIDISCHG

6uA

RESET COMPARATOR

SS/DEL

DISCHARGE

R

+

OFF

ICHG

70uA

ICHG

-

+

SOFT START CLAMP

1.3V

ERROR

AMPLIFIER

0.6V

SS/DEL

-

+

-

VID5

VID0

VID1

VID2

VID3

VID4

BBFB

EAOUT

IROSC

+

-

VID

=

11111X

IROSC

DISABLE

IROSC

VID

VID STEP-DOWN

VID DAC OUTPUT

IROSC

CONTROL

IROSC

VDAC

FB

IROSC

1.2V

IROSC

IFB

VOSNS-

VBIAS

LGND

VBIAS

REGULATOR

+

-

+

VBIAS

IROSC

6.8V

-

50%

DUTY

CYCLE

RAMP GENERATOR

5.0V

ROSC

BUFFER

CURRENT

SOURCE

GENERATOR

RMPOUT

ROSC

+

-

AMPLIFIER

1.0V

Figure 6. IR3081A Block Diagram

VID Control

A 6-bit VID voltage compatible with VR 10, as shown in Table 1, is available at the VDAC pin. A detailed block

diagram of the VID control circuitry can be found in Figure 7. The VID pins require an external bias voltage and

should not be floated. The VID input comparators, with 0.6V reference, monitor the VID pins and control the 6 bit

Digital-to-Analog Converter (DAC) whose output is sent to the VDAC buffer amplifier. The output of the buffer

amplifier is the VDAC pin. The VDAC voltage is post-package trimmed to compensate for the input offsets of the

Error Amplifier to provide a 0.5% system set-point accuracy. The actual VDAC voltage does not determine the

system accuracy and has a wider tolerance.

Page 12 of 39

1/31/05

IR3081A

The IR3081A can accept changes in the VID code while operating and vary the DAC voltage accordingly. The

sink/source capability of the VDAC buffer amplifier is programmed by the same external resistor that sets the

oscillator frequency. The slew rate of the voltage at the VDAC pin can be adjusted by an external capacitor between

VDAC pin and the VOSNS- pin. A resistor connected in series with this capacitor is required to compensate the

VDAC buffer amplifier. Digital VID transitions result in a smooth analog transition of the VDAC voltage and

converter output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output

voltage.

It is desirable to prevent negative inductor currents in response to a request for a lower VID code. Negative current

transforms the buck converter into a boost converter and transfers energy from the output capacitors back into the

input voltage. This energy can cause voltage spikes and damage the silver box or other components unless they

are specifically designed to handle it. Furthermore, power is wasted during the transfer of energy from the output

back to the input.

The IR3081A includes circuitry that turns off both control and synchronous MOSFETs in response to a lower VID

code so that the load current instead of the inductor discharges the output capacitors. A lower VID code is detected

by the VID step-down detect comparator which monitors the “fast” output of the DAC (plus 7mV for noise immunity)

compared to the “slow” output of the VDAC pin. If a dynamic VID step down is detected, the body brake latch is set

and the output of the error amplifier is pulled down to 75% of the DAC voltage by the VID body brake clamp. This

triggers the Body Braking^TMfunction, which turns off both high side and low side drivers in the phase ICs.

The converter’s output voltage needs to be monitored and compared to the VDAC voltage to determine when to

resume normal operation. Unfortunately, the voltage on the FB pin can be pulled down by its compensation network

during the sudden decrease in the Error Amplifier’s output voltage so an additional pin BBFB is provided. The BBFB

pin is connected to the converter output voltage and VDRP pin with resistors of the same value as on the FB pin

and therefore provides an un-corrupted representation of converter output voltage. The regulation detect

comparator compares the BBFB to the VDAC voltage and resets the body brake latch releasing the error amplifier’s

output and allowing normal operation to resume. Body Braking^TMduring a transition to a lower VID code can be

disabled by connecting the BBFB pin to ground.

800ns

BLANKING

VID

=

11111X DETECT

VDAC BUFFER

AMP

VID5

VID0

VID1

VID2

VID3

VID4

DIGITAL TO

ANALOG

CONVERTER

VID INPUT

COMPARATORS

"FAST" VDAC

(1 OF

6

+

-

+

-

SHOWN)

ISOURCE

ISINK

"SLOW" VDAC

+

-

VDAC

+

0.6V

-

VOSNS-

EAOUT

-

VID DOWN

BB CLAMP

7mV

+

-

TO ERROR AMP

75%

VID STEP-DOWN

DETECT

ENABLE

COMPARATOR

1.7us

BLANKING

-

+

S

R

BODY

BRAKE

LATCH

IBBFB

+

-

BBFB

REGULATION

DETECT

COMPARATOR

IROSC (From Current Source Generator)

Figure 7. VID Control Block Diagram

Page 13 of 39

1/31/05

IR3081A

Processor Pins (0 = low, 1 = high)

Vout

(V)

Vout

(V)

VID4 VID3 VID2 VID1 VID0 VID5

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0.8375

0.8500

0.8625

0.8750

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

1.0500

1.0625

1.0750

1.0875

OFF⁴

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

1.4750

1.4875

1.5000

1.5125

1.5250

1.5375

1.5500

1.5625

1.5750

1.5875

1.6000

OFF⁴

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

Note: 3. Output disabled (Fault mode)

Table 1. Voltage Identification (VID)

Adaptive Voltage Positioning

Adaptive voltage positioning is needed to reduce the output voltage deviations during load transients and the power

dissipation of the load when it is drawing maximum current. The circuitry related to voltage positioning is shown in

Figure 8. Resistor RFB is connected between the Error Amplifier’s inverting input pin FB and the converter’s output

voltage. An internal current source whose value is programmed by the same external resistor that programs the

oscillator frequency pumps current into the FB pin. The error amplifier forces the converter’s output voltage lower to

maintain a balance at its inputs. RFB is selected to program the desired amount of fixed offset voltage below the

DAC voltage.

The voltage at the VDRP pin is a buffered version of the share bus and represents the sum of the DAC voltage and

the average inductor current of all the phases. The VDRP pin is connected to the FB pin through the resistor RDRP.

Since the Error Amplifier will force the loop to maintain FB to be equal to the VDAC reference voltage, an additional

current will flow into the FB pin equal to (VDRP-VDAC) / RDRP. When the load current increases, the adaptive

positioning voltage increases accordingly. More current flows through the feedback resistor RFB, and makes the

output voltage lower proportional to the load current. The positioning voltage can be programmed by the resistor

RDRP so that the droop impedance produces the desired converter output impedance. The offset and slope of the

converter output impedance are referenced to and therefore independent of the VDAC voltage.

Page 14 of 39

1/31/05

IR3081A

Control IC

Phase IC

Error

Current Sense

Amplifier

CSIN+

CSIN-

+

VDAC

ISHARE

VDAC

+

EA OUT

FB

-

10k

Vo

IFB

RFB

RDRP

VDRP

Amplifier

Phase IC

VDRP

IIN

Current Sense

-

+

Amplifier

CSIN+

CSIN-

+

ISHARE

VDAC

-

10k

Figure 8. Adaptive voltage positioning

Inductor DCR Temperature Correction

If the thermal compensation of the inductor DCR provided by the temperature dependent gain of the current sense

amplifier is not adequate, a negative temperature coefficient (NTC) thermistor can be used for additional correction.

The thermistor should be placed close to the inductor and connected in parallel with the feedback resistor, as

shown in Figure 9. The resistor in series with the thermistor is used to reduce the nonlinearity of the thermistor. A

similar network must be placed on the BBFB to ensure proper operation during a transition to a lower VID code with

Body Braking^TM.

Control IC

Error

Amplifier

+

VDAC

EA OUT

-

Vo

RFB

RFB2

FB

IFB

Rt

RDRP

AVP

Amplifier

VDRP

IIN

-

+

Figure 9. Temperature compensation of inductor DCR

Remote Voltage Sensing

To reduce the effect of impedance in the ground plane, the VOSNS- pin is used for remote sensing and connected

directly to the load. The VDAC voltage is referenced to VOSNS- to avoid additional error terms or delay related to a

separate differential amplifier. The capacitor connecting the VDAC and VOSNS- pins ensure that high speed

transients are fed directly into the error amplifier without delay.

Page 15 of 39

1/31/05

IR3081A

Soft Start, Over-Current Fault Delay, and Hiccup Mode

The IR3081A has a programmable soft-start function to limit the surge current during the converter start-up. A

capacitor connected between the SS/DEL and LGND pins controls soft start as well as over-current protection delay

and hiccup mode timing. A charge current of 70uA and discharge current of 6uA control the up slope and down

slope of the voltage at the SS/DEL pin respectively

Figure 10 depicts the various operating modes as controlled by the SS/DEL function. If there is no fault, the SS/DEL

pin will begin to be charged. The error amplifier output is clamped low until SS/DEL reaches 1.3V. The error

amplifier will then regulate the converter’s output voltage to match the SS/DEL voltage less the 1.3V offset until it

reaches the level determined by the VID inputs. The SS/DEL voltage continues to increase until it rises above 3.71V

and allows the PWRGD signal to be asserted. SS/DEL finally settles at 3.8V, indicating the end of the soft start.

Under Voltage Lock Out and VID=11111x faults as well as a low signal on the ENABLE input immediately sets the

fault latch causing SS/DEL to begin to discharge. The SS/DEL capacitor will continue to discharge down to 0.2V. If

the fault has cleared the fault latch will be reset by the discharge comparator allowing a normal soft start to occur.

A delay is included if an over-current condition occurs after a successful soft start sequence. This is required since

over-current conditions can occur as part of normal operation due to load transients or VID transitions. If an over-

current fault occurs during normal operation it will initiate the discharge of the capacitor at SS/DEL but will not set

the fault latch immediately. If the over-current condition persists long enough for the SS/DEL capacitor to discharge

below the 90mV offset of the delay comparator, the Fault latch will be set pulling the error amplifier’s output low

inhibiting switching in the phase ICs and de-asserting the PWRGD signal. The SS/DEL capacitor will continue to

discharge until it reaches 0.2V and the fault latch is reset allowing a normal soft start to occur. If an over-current

condition is again encountered during the soft start cycle the fault latch will be set without any delay and hiccup

mode will begin. During hiccup mode the charge to discharge current ratio results in a fixed 7.9% hiccup mode duty

cycle regardless of at what point the over-current condition occurs. However, the hiccup frequency is determined by

the load current and over-current set value.

The over-current delay can be reduced by adding a resistor in series with the SS/DEL capacitor. The delay

comparator’s offset voltage is reduced by the drop in the resistor caused by the discharge current. The value of the

series resistor should be 10KΩ or less to avoid interference with the soft start function.

If SS/DEL pin is pulled below 0.9V, the converter can be disabled.

Under Voltage Lockout (UVLO)

The UVLO function monitors the IR3081A’s VCC supply pin and ensures that IR3081A has a high enough voltage

to power the internal circuit. The IR3081A’s UVLO is set higher than the minimum operating voltage of compatible

Phase ICs thus providing UVLO protection for them as well. During power-up the fault latch is reset when VCC

exceeds 9.7V and there is no other fault. If the VCC voltage drops below 8.9V the fault latch will be set. For

converters using a separate 5V supply for gate driver bias an external UVLO circuit can be added to prevent any

operation until adequate voltage is present. A diode connected between the 5V supply and the SS/DEL pin provides

a simple 5V UVLO function.

Over Current Protection (OCP)

The current limit threshold is set by a resistor connected between the OCSET and VDAC pins. If the IIN pin voltage,

which is proportional to the average current plus DAC voltage, exceeds the OCSET voltage, the over-current

protection is triggered.

VID = 11111X Fault

VID codes of 111111 and 111110 will set the fault latch and disable the error amplifier. An 800ns delay is provided

to prevent a fault condition from occurring during Dynamic VID changes.

Enable Input

Pulling the ENABLE pin below 0.6V sets the Fault Latch.

Page 16 of 39

1/31/05

IR3081A

8.9V

UVLO

VCC

(12V)

ENABLE

3.735V

3.685V

SS/DEL

VOUT

1.3V

PWRGD

IOUT

OCP THRESHOLD

START-UP

NORMAL OPERATION

HICCUP OVER-CURRENT

PROTECTION

RE-START

AFTER

OCP

POWER-DOWN

(ENABLE GATES

FAULT MODE)

(VOUT CHANGES DUE TO LOAD

AND VID CHANGES)

(VCC GATES

FAULT MODE)

OCP

DELAY

Figure 10. Operating Waveforms

Power Good Output

The PWRGD pin is an open-collector output and should be pulled up to a voltage source through a resistor. During

soft start, the PWRGD remains low until the output voltage is in regulation and SS/DEL is above 3.71V. The

PWRGD pin becomes low if the fault latch is set. A high level at the PWRGD pin indicates that the converter is in

operation and has no fault, but does not ensure the output voltage is within the specification. Output voltage

regulation within the design limits can logically be assured however, assuming no component failure in the system.

Load Current Indicator Output

The VDRP pin voltage represents the average current of the converter plus the DAC voltage. The load current can

be retrieved by a differential amplifier which subtracts the VDAC voltage from the VDRP voltage.

System Reference Voltage (VBIAS)

The IR3081 supplies a 6.8V/5mA precision reference voltage from the VBIAS pin. The oscillator ramp amplitude

tracks the VBIAS voltage, which should be used to program the Phase IC trip points to minimize phase delay errors.

Precondition of IIN during Soft Start

IIN pin is clamped during the early stage of soft start, which disables current sharing function in the phase ICs to

prevent PWM ramp from pulling too low. When V(SS/DEL)<0.7V, the precondition latch is set, and IIN is clamped

to ground through a 10kꢀ resistor. After V(SS/DEL) is 1.3V above V(FB), error amplifier output is released. When

V(EAOUT) jumps above 0.6V, the precondition latch is reset and the IIN clamp is removed. Normal current

sharing in the phase ICs then resumes.

Page 17 of 39

1/31/05

IR3081A

APPLICATION INFORMATION

POWERGOOD

VRHOT

PHASE FAULT

12V

RCS-

CCS-

QGATE

VGATE

RVCC

CCS+

RCS+

10 ohm

RBIASIN 20k

DBST

DGATE

RGATE

CVCC

0.1uF

CBST

CIN

VOUT SENSE+

1

15

14

13

12

11

RMPIN+

VCCH

GATEH

PGND

GATEL

VCCL

2

3

4

5

IR3086A

PHASE

IC

RMPIN-

HOTSET

VRHOT

ISHARE

L

VOUT+

DISTRIBUTION

IMPEDANCE

COUT

0.1uF

CFB

ENABLE

VOUT-

CVCCL

RBBFB

RFB1

RFB

RVCC

VOUT SENSE-

RPWMRMP

1

2

3

4

5

6

7

21

20

19

18

17

16

15

OSCDS

VID5

VID0

VID1

VID2

VID3

VID4

VBIAS

BBFB

EAOUT

FB

CSCOMP

RBBDRP

CVCC

VID5

VID0

VID1

VID2

VID3

VID4

IR3081A

CONTROL

IC

CCP

RCP

RCS-

VDRP

IIN

RDRP1 CDRP

RDRP

CCS+

RCS+

CCP1

CCS-

RBIASIN 20k

OCSET

DBST

CBST

ROCSET

1

15

RMPIN+

VCCH

GATEH

PGND

GATEL

VCCL

2

3

4

5

14

13

12

11

IR3086A

PHASE

IC

RMPIN-

HOTSET

VRHOT

ISHARE

L

ROSC

RVDAC

CVDAC

RSHARE

CVCCL

RVCC

RPWMRMP

CSCOMP

CVCC

RCS-

CCS+

RCS+

CCS-

RBIASIN 20k

DBST

CBST

1

15

RMPIN+

VCCH

2

3

4

5

14

IR3086A

PHASE

IC

RMPIN-

HOTSET

VRHOT

ISHARE

GATEH

L

13

PGND

12

GATEL

11

VCCL

CVCCL

RVCC

RPWMRMP

CSCOMP

CVCC

RCS-

CCS+

RCS+

CCS-

RBIASIN 20k

DBST

CBST

1

15

RMPIN+

VCCH

2

3

4

5

14

IR3086A

PHASE

IC

RMPIN-

HOTSET

VRHOT

ISHARE

GATEH

L

13

PGND

12

GATEL

11

VCCL

CVCCL

RVCC

RPWMRMP

CSCOMP

CVCC

RCS-

CCS+

RCS+

CCS-

RBIASIN 20k

DBST

RCS+

CBST

1

15

RMPIN+

VCCH

2

3

4

5

14

IR3086A

PHASE

IC

RMPIN-

HOTSET

VRHOT

ISHARE

GATEH

L

13

PGND

12

GATEL

11

VCCL

CVCCL

RVCC

RPWMRMP

CSCOMP

CVCC

RCS-

CCS+

RCS+

CCS-

RBIASIN 20k

DBST

RCS+

CBST

1

15

RMPIN+

VCCH

2

3

4

5

14

IR3086A

PHASE

IC

RMPIN-

HOTSET

VRHOT

ISHARE

GATEH

L

13

PGND

12

GATEL

11

VCCL

CVCCL

RVCC

RPWMRMP

CSCOMP

CVCC

Figure 11. IR3081A/IR3086A Six-Phase VRM/EVRD 10 Converter

Page 18 of 39

1/31/05

IR3081A

DESIGN PROCEDURES - IR3081A AND IR3086A CHIPSET

IR3081A EXTERNAL COMPONENTS

Oscillator Resistor Rosc

The oscillator of IR3081A generates a triangle waveform to synchronize the phase ICs, and the switching frequency

of the each phase converter equals the oscillator frequency, which is set by the external resistor ROSC according to

the curve in Figure 13.

Soft Start Capacitor CSS/DEL

Because the capacitor CSS/DEL programs four different time parameters, i.e. soft start delay time, soft start time,

over-current latch delay time, and power good delay time, they should be considered together while choosing

CSS/DEL.

The SS/DEL pin voltage controls the slew rate of the converter output voltage, as shown in Figure 10. After the

ENABLE pin voltage rises above 0.6V, there is a soft-start delay time tSSDEL, after which the error amplifier output is

released to allow the soft start. The soft start time tSS represents the time during which converter voltage rises from

zero to VO. tSS can be programmed by an external capacitor, which is determined by Equation (1).

I_CHG*t_SS70 *10⁻⁶*t_SS

(1)

C_{SS / DEL}

=

V_O

Once CSS/DEL is chosen, the soft start delay time tSSDEL, the over-current fault latch delay time tOCDEL, and the

delay time tVccPG from output voltage (VO) in regulation to Power Good are fixed and shown in Equations (2), (3)

and (4) respectively.

C

_{SS / DEL}*1.3 C

I_CHG

_{SS / DEL}*1.3

70*10⁻⁶

(2)

(3)

(4)

t_SSDEL

t_OCDEL

t_VccPG

=

C

_{SS / DEL}*0.115

I_OCDISCHG

C

=

_{SS / DEL}*0.115

40*10⁻⁶

=

C

_{SS / DEL}*(3.8 − 0.065 −V_O−1.3)

C

=

_{SS / DEL}*(3.735 −V_O−1.3)

=

70*10⁻⁶

I_CHG

VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC

The slew rate of VDAC down-slope SRDOWN can be programmed by the external capacitor CVDAC as defined in

Equation (5), where ISINK is the sink current of VDAC pin as shown in Figure 15. The resistor RVDAC is used to

compensate VDAC circuit and is determined by Equation (6). The slew rate of VDAC up-slope SRUP is proportional

to that of VDAC down-slope and is given by Equation (7), where ISOURCE is the source current of VDAC pin as

shown in Figure15.

I_SINK

SR_DOWN

(5)

(6)

(7)

C_VDAC

=

3.2 ∗10⁻¹⁵

R_VDAC= 0.5 +

2

C_VDAC

I_SOURCE

=

SR_UP

C_VDAC

Page 19 of 39

1/31/05

IR3081A

Over Current Setting Resistor ROCSET

The inductor DC resistance is utilized to sense the inductor current. The copper wire of inductor has a constant

temperature coefficient of 3850 ppm/°C, and therefore the maximum inductor DCR can be calculated from Equation

(8), where RL_MAX and RL_ROOM are the inductor DCR at maximum temperature TL_MAX and room temperature

T_ROOM respectively.

R_{L _ MAX}= R_{L _ ROOM}∗[1+ 3850 *10⁻⁶∗ (T_{L _ MAX}− T_ROOM)]

(8)

The current sense amplifier gain of IR3086A decreases with temperature at the rate of 1470 ppm/°C, which

compensates part of the inductor DCR increase. The phase IC die temperature is only a couple of degrees Celsius

higher than the PCB temperature due to the low thermal impedance of MLPQ package. The minimum current sense

amplifier gain at the maximum phase IC temperature TIC_MAX is calculated from Equation (9).

G_{CS _ MIN}= G_{CS _ ROOM}∗[1−1470 *10⁻⁶∗ (T_{IC _ MAX}− T_ROOM)]

(9)

The total input offset voltage (VCS_TOFST) of current sense amplifier in phase ICs is the sum of input offset

(VCS_OFST) of the amplifier itself and that created by the amplifier input bias currents flowing through the current

sense resistors RCS+ and RCS-.

V_{CS _ TOFST}= V_{CS _ OFST}+ I_{CSIN +}∗ R_{CS +}− I_{CSIN −}∗ R_{CS −}

(10)

The over current limit is set by the external resistor ROCSET as defined in Equation (11), where ILIMIT is the required

over current limit. IOCSET, the bias current of OCSET pin, changes with switching frequency setting resistor ROSC

and is determined by the curve in Figure 14. KP is the ratio of inductor peak current over average current in each

phase and is calculated from Equation (12).

I_LIMIT

n

R_OCSET= [

∗ R_{L _ MAX}∗(1+ K_P) +V_{CS _ TOFST}]∗G_{CS _ MIN}/ I_OCSET

(11)

(12)

(V_I−V_O)∗V_O/(L∗V_I∗ f_SW∗2)

I_O/ n

K_P=

No Load Output Voltage Setting Resistor RFB and Adaptive Voltage Positioning Resistor RDRP

A resistor between FB pin and the converter output is used to create output voltage offset VO_NLOFST, which is the

difference between VDAC voltage and output voltage at no load condition. Adaptive voltage positioning further

lowers the converter voltage by RO*IO, where RO is the required output impedance of the converter.

RFB is not only determined by IFB, the current flowing out of FB pin as shown in Figure 14, but also affected by the

adaptive voltage positioning resistor RDRP and total input offset voltage of current sense amplifiers. RFB and RDRP

are determined by (13) and (14) respectively.

R_{L _ MAX}∗V_{O _ NLOFST}−V_{CS _TOFST}∗ n ∗ R_O

R_FB

=

(13)

I_FB∗ R_{L _ MAX}

R_FB∗ R_{L _ MAX}∗G_{CS _ MIN}

(14)

R_DRP

=

n ∗ R_O

Body Braking^TMRelated Resistors RBBFB and RBBDRP

The body braking^TMduring Dynamic VID can be disabled by connecting BBFB pin to ground. If the feature is

enabled, Resistors RBBFB and RBBDRP are needed to restore the feedback voltage of the error amplifier after

Dynamic VID step down. Usually RBBFB and RBBDRP are chosen to match RFB and RDRP respectively.

Page 20 of 39

1/31/05

IR3081A

IR3086A EXTERNAL COMPONENTS

PWM Ramp Resistor RPWMRMP and Capacitor CPWMRMP

PWM ramp is generated by connecting the resistor RPWMRMP between a voltage source and PWMRMP pin as well

as the capacitor CPWMRMP between PWMRMP and LGND. Choose the desired PWM ramp magnitude VRAMP and

the capacitor CPWMRMP in the range of 100pF and 470pF, and then calculate the resistor RPWMRMP from Equation

(15). To achieve feed-forward voltage mode control, the resistor RRAMP should be connected to the input of the

converter.

V_O

(15)

R_PWMRMP

=

V

_IN* f_SW*C_PWMRMP*[ln(V_IN−V_DAC) − ln(V_IN−V_DAC−V_PWMRMP)]

Inductor Current Sensing Capacitor CCS+ and Resistors RCS+ and RCS-

The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS+ and capacitor

CCS+ in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage

across the capacitor CCS+ represents the inductor current. If the two time constants are not the same, the AC

component of the capacitor voltage is different from that of the real inductor current. The time constant mismatch

does not affect the average current sharing among the multiple phases, but affect the current signal ISHARE as well

as the output voltage during the load current transient if adaptive voltage positioning is adopted.

Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS+ and calculate RCS+ as

follows.

L R_L

=

(16)

R_CS+

C_{CS +}

The bias current flowing out of the non-inverting input of the current sense amplifier creates a voltage drop across

RCS+, which is equivalent to an input offset voltage of the current sense amplifier. The offset affects the accuracy of

converter current signal ISHARE as well as the accuracy of the converter output voltage if adaptive voltage

positioning is adopted. To reduce the offset voltage, a resistor RCS- should be added between the amplifier inverting

input and the converter output. The resistor RCS- is determined by the ratio of the bias current from the non-inverting

input and the bias current from the inverting input.

I_{CSIN +}

I_{CSIN −}

(17)

R_{CS −}

=

∗ R_{CS +}

If RCS- is not used, RCS+ should be chosen so that the offset voltage is small enough. Usually RCS+ should be less

than 2 kꢀ and therefore a larger CCS+ value is needed.

Over Temperature Setting Resistors RHOTSET1 and RHOTSET2

The threshold voltage of VRHOT comparator is proportional to the die temperature TJ (ºC) of phase IC. Determine

the relationship between the die temperature of phase IC and the temperature of the power converter according to

the power loss, PCB layout and airflow etc, and then calculate HOTSET threshold voltage corresponding to the

allowed maximum temperature from Equation (18).

V_HOTSET= 4.73*10⁻³*T_J+1.241

(18)

There are two ways to set the over temperature threshold, central setting and local setting. In the central setting,

only one resistor divider is used, and the setting voltage is connected to HOTSET pins of all the phase ICs. To

reduce the influence of noise on the accuracy of over temperature setting, a 0.1uF capacitor should be placed next

to HOTSET pin of each phase IC. In the local setting, a resistor divider per phase is needed, and the setting voltage

is connected to HOTSET pin of each phase. The 0.1uF decoupling capacitor is not necessary. Use VBIAS as the

reference voltage. If RHOTSET1 is pre-selected, RHOTSET2 can be calculated as follows.

R_HOTSET1∗V_HOTSET

V_BIAS−V_HOTSET

(19)

R_{HOTSET 2}

=

Page 21 of 39

1/31/05

IR3081A

Phase Delay Timing Resistors RPHASE1 and RPHASE2

The phase delay of the interleaved multiphase converter is programmed by the resistor divider connected at

RMPIN+ or RMPIN- depending on which slope of the oscillator ramp is used for the phase delay programming of

phase IC, as shown in Figure 3.

If the upslope is used, RMPIN+ pin of the phase IC should be connected to RMPOUT pin of the control IC and

RMPIN- pin should be connected to the resistor divider. When RMPOUT voltage is above the trip voltage at

RMPIN- pin, the PWM latch is set. GATEL becomes low, and GATEH becomes high after the non-overlap time.

If down slope is used, RMPIN- pin of the phase IC should be connected to RMPOUT pin of the control IC and

RMPIN+ pin should be connected to the resistor divider. When RMPOUT voltage is below the trip voltage at

RMPIN- pin, the PWM latch is set. GATEL becomes low, and GATEH becomes high after the non-overlap time.

Use VBIAS voltage as the reference for the resistor divider since the oscillator ramp magnitude from control IC

tracks VBIAS voltage. Try to avoid both edges of the oscillator ramp for better noise immunity. Determine the ratio

of the programming resistors corresponding to the desired switching frequencies and phase numbers. If the resistor

RPHASEx1 is pre-selected, the resistor RPHASEx2 is determined as:

RA_PHASEx∗ R_PHASEx1

R_PHASEx2

=

(20)

1 − RA_PHASEx

Combined Over Temperature and Phase Delay Setting Resistors RPHASE1, RPHASE2 and RPHASE3

The over temperature setting resistor divider can be combined with the phase delay resistor divider to save one

resistor per phase.

Calculate the HOTSET threshold voltage VHOTSET corresponding to the allowed maximum temperature from

Equation (18). If the over temperature setting voltage is lower than the phase delay setting voltage,

VBIAS*RAPHASEx, connect RMPIN+ or RMPIN- pin between RPHASEx1 and RPHASEx2, and connect HOTSET pin

between RPHASEx2 and RPHASEx3. Pre-select RPHASEx1,

(RA_PHASEx∗V_BIAS−V_HOTSET)* R_PHASEx1

(21)

R_PHASEx2

=

V_BIAS∗(1− RA_PHASEx

)

V_HOTSET∗ R_PHASEx1

(22)

R_PHASEx3

=

V_BIAS*(1− RA_PHASEx)

If the over temperature setting voltage is higher than the phase delay setting voltage, VBIAS*RAPHASEx, connect

HOTSET pin between RPHASEx1 and RPHASEx2 and connect RMPIN+ or RMPIN- between RPHASEx2 and RPHASEx3

respectively. Pre-select RPHASEx1,

(V_HOTSET− RA_PHASEx∗V_BIAS)∗ R_PHASEx1

(23)

R_PHASEx2

=

V_BIAS−V_HOTSET

RA_PHASEx∗V_BIAS* R_PHASEx1

V_BIAS−V_HOTSET

(24)

R_PHASEx3

=

Bootstrap Capacitor CBST

Depending on the duty cycle and gate drive current of the phase IC, a 0.1uF to 1uF capacitor is needed for the

bootstrap circuit.

Decoupling Capacitors for Phase IC

0.1uF-1uF decoupling capacitors are required at VCC and VCCL pins of phase ICs.

Page 22 of 39

1/31/05

IR3081A

VOLTAGE LOOP COMPENSATION

The adaptive voltage positioning (AVP) is usually adopted in the computer applications to improve the transient

response and reduce the power loss at heavy load. Like current mode control, the adaptive voltage positioning loop

introduces extra zero to the voltage loop and splits the double poles of the power stage, which make the voltage

loop compensation much easier.

Resistors RFB and RDRP are chosen according to Equations (13) and (14), and the selection of compensation types

depends on the output capacitors used in the converter. For the applications using Electrolytic, Polymer or AL-

Polymer capacitors and running at lower frequency, type II compensation shown in Figure 12(a) is usually enough.

While for the applications using only ceramic capacitors and running at higher frequency, type III compensation

shown in Figure 12(b) is preferred.

For applications where AVP is not required, the compensation is the same as for the regular voltage mode control.

For converter using Polymer, AL-Polymer, and ceramic capacitors, which have much higher ESR zero frequency,

type III compensation is required as shown in Figure 12(b) with RDRP and CDRP removed.

CCP1

RFB

CFB

RCP

CCP

VO+

RCP

CCP

RFB1

FB

-

EAOUT

RFB

EAOUT

VO+

FB

VDAC

-

RDRP

+

VDRP

EAOUT

VDAC

RDRP

CDRP

+

VDRP

(a) Type II compensation

(b) Type III compensation

Figure 12. Voltage loop compensation network

Type II Compensation for AVP Applications

Determine the compensation at no load, the worst case condition. Choose the crossover frequency fc between 1/10

and 1/5 of the switching frequency per phase. Assume the time constant of the resistor and capacitor across the

output inductors matches that of the inductor, and determine RCP and CCP from Equations (25) and (26), where L

and C are the equivalent inductance of output inductors and the equivalent capacitance of output capacitor^Es

respec^Etively.

(2π ∗ f_C)²∗ L_E∗C_E∗ R_FB∗V_PWMRMP

(25)

R_CP

=

V_O* 1+ (2π * f_C*C * R_C)²

10 ∗ L_E∗C_E

(26)

C_CP

=

R_CP

C

CP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A

ceramic capacitor between 10pF and 220pF is usually enough.

Type III Compensation for AVP Applications

Determine the compensation at no load, the worst case condition. Assume the time constant of the resistor and

capacitor across the output inductors matches that of the inductor, the crossover frequency and phase margin of the

voltage loop can be estimated by Equations (27) and (28), where RLE is the equivalent resistance of inductor DCR.

R_DRP

f_C

=

(27)

1

2 *C_E∗G_CS* R_FB∗ R_LE

π

Page 23 of 39

1/31/05

IR3081A

180

π

θ_C1= 90 − A tan(0.5)∗

(28)

Choose the desired crossover frequency fc around fc1 estimated by Equation (27) or choose fc between 1/10 and

1/5 of the switching frequency per phase, and select the components to ensure the slope of close loop gain is -20dB

/Dec around the crossover frequency. Choose resistor RFB1 according to Equation (29), and determine CFB and

RDRP from Equations (30) and (31).

1

2

3

R_FB1

C_FB

=

R_FB

to

R_FB1

=

R_FB

(29)

1

(30)

=

4π ∗ f_C∗ R_FB1

(R_FB+ R_FB1) ∗C_FB

=

(31)

C_DRP

R_DRP

RCP and CCP have limited effect on the crossover frequency, and are used only to fine tune the crossover frequency

and transient load response. Determine RCP and CCP from Equations (32) and (33).

(2π ∗ f_C)²∗ L_E∗C_E∗ R_FB∗V_PWMRMP

(32)

R_CP

=

V_O

10 ∗ L_E∗C_E

C_CP

=

(33)

R_CP

CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A

ceramic capacitor between 10pF and 220pF is usually enough.

Type III Compensation for Non-AVP Applications

Resistor RFB is chosen according to Equations (13), and resistor RDRP and capacitor CDRP are not needed. Choose

the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase and select the desired phase

margin θc. Calculate K factor from Equation (34), and determine the component values based on Equations (35) to

(39),

θ_C

180

π

K = tan[ ∗(

4

+1.5)]

(34)

(35)

(36)

(37)

(38)

(39)

(2π ∗ L_E∗C_E∗ f_C)²∗V_PWMRMP

V_O∗ K

R_CP= R_FB

∗

K

C_CP

=

2π ∗ f_C∗ R_CP

1

C_CP1

C_FB

=

2π ∗ f_C∗ K ∗ R_CP

K

=

2π ∗ f_C∗ R_FB

1

R_FB1

=

2π ∗ f_C∗ K ∗C_FB

Page 24 of 39

1/31/05

IR3081A

CURRENT SHARE LOOP COMPENSATION

The crossover frequency of the current share loop should be at least one decade lower than that of the voltage loop

in order to eliminate the interaction between the two loops. A capacitor from SCOMP to ground is usually enough

for the share loop compensation. Choose the crossover frequency of current share loop (fCI) based on the

crossover frequency of voltage loop (fC), and determine the CSCOMP,

0.65* R_PWMRMP*V_I* I_O*G_{CS _ ROOM}* R_LE*[1+ 2π * f_CI*C_E*(V_OI_O)]* F_MI

(40)

C_SCOMP

=

V_O∗2π ∗ f_CI*1.05*10⁶

Where FMI is the PWM gain in the current share loop,

_PWMRMP*C_PWMRMP* f_SW*V _PWMRMP

R

=

(41)

F_MI

(V_I−V_PWMRMP−V_DAC)*(V_I−V_DAC

)

Page 25 of 39

1/31/05

IR3081A

DESIGN EXAMPLE 1 - VRM 10 2U CONVERTER

SPECIFICATIONS

Input Voltage: VI=12 V

DAC Voltage: VDAC=1.35 V

No Load Output Voltage Offset: VO_NLOFST=20 mV

Output Current: IO=105 ADC

Maximum Output Current: IOMAX=120 ADC

Output Impedance: RO=0.91 mꢀ

VCC Ready to VCC Power Good Delay: tVccPG=0-10mS

Soft Start Time: tSS=2 mS

Over Current Delay: tOCDEL<0.5mS

Dynamic VID Down-Slope Slew Rate: SRDOWN=2.5mV/uS

Over Temperature Threshold: TPCB=115 ºC

POWER STAGE

Phase Number: n=6

Switching Frequency: fSW=400 kHz

Output Inductors: L=220 nH, RL=0.47 mꢀ

Output Capacitors: AL-Polymer, C=560uF, RC= 7mꢀ, Number Cn=10

IR3081A EXTERNAL COMPONENTS

Oscillator Resistor Rosc

Once the switching frequency is chosen, ROSC can be determined from the curve in Figure 13. For switching

frequency of 400kHz per phase, choose ROSC=30.1kꢀ

Soft Start Capacitor CSS/DEL

Determine the soft start capacitor from the required soft start time.

70*10⁻⁶∗2*10⁻³

1.35− 20*10⁻³

I_CHG∗t_SS

C_{SS / DEL}

=

= 0.1uF

V_O

The soft start delay time is

_{SS / DEL}∗1.3 0.1*10⁻⁶∗1.3

C

t_SSDEL

=

=1.86mS

70*10⁻⁶

I_CHG

The power good delay time is

C

_{SS / DEL}*(3.735 −V_O−1.3) 0.1*10⁻⁶*(3.735 −1.33−1.3)

t_VccPG

=

= 1.58ms

70*10⁻⁶

I_CHG

Over current delay time is

_{SS / DEL}*0.115 0.1*10⁻⁶*0.115

C

t_OCDEL

=

= 0.29ms

40*10⁻⁶

I_OCDISCHG

Page 26 of 39

1/31/05

IR3081A

VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC

From Figure 15, the sink current of VDAC pin corresponding to 400kHz (ROSC=30.1kꢀ) is 76uA. Calculate the

VDAC down-slope slew-rate programming capacitor from the required down-slope slew rate.

76*10⁻⁶

I_SINK

SR_DOWN

, Choose CVDAC=33nF

= 30.4nF

C_VDAC

=

2.5*10⁻³/10⁻⁶

Calculate the programming resistor.

3.2*10⁻¹⁵

C_VDAC

3.2*10⁻¹⁵

R_VDAC= 0.5 +

= 0.5 +

= 3.5Ω

2

(33*10⁻⁹

)

From Figure 15, the source current of VDAC pin is 110uA. The VDAC up-slope slew rate is

110*10⁻⁶

33*10⁻⁹

I_SOURCE

C_VDAC

SR_UP

=

= 3.3mV / uS

Over Current Setting Resistor ROCSET

The room temperature is 25ºC and the target PCB temperature is 100 ºC. The phase IC die temperature is about 1

ºC higher than that of phase IC, and the inductor temperature is close to PCB temperature.

Calculate Inductor DC resistance at 100 ºC,

R_{L _ MAX}= R_{L _ ROOM}∗[1+3850*10⁻⁶∗(T_{L _ MAX}−T_ROOM)] = 0.47*10⁻³∗[1+3850*10⁻⁶∗(100− 25)] = 0.61mΩ

The current sense amplifier gain is 34 at 25ºC, and its gain at 101ºC is calculated as,

G_{CS _ MIN}= G_{CS _ ROOM}∗[1−1470 *10⁻⁶∗(T_{IC _ MAX}−T_ROOM)] = 34∗[1−1470 *10⁻⁶∗(101− 25)] = 30.2

Set the over current limit at 135A. From Figure 14, the bias current of OCSET pin (IOCSET) is 41uA with

ROSC=30.1kꢀ. The total current sense amplifier input offset voltage is 0.55mV, which includes the offset created by

the current sense amplifier input resistor mismatch.

Calculate constant KP, the ratio of inductor peak current over average current in each phase,

(12 −1.33)∗1.33/(220*10⁻⁹∗12∗ 400*10³∗ 2)

(V_I−V_O)∗V_O/(L ∗V_I∗ f_SW∗ 2)

K_P

=

= 0.3

I_LIMIT/ n

135/ 6

I_LIMIT

n

R_OCSET= [

∗ R_{L _ MAX}∗(1+ K_P) +V_{CS _ TOFST}]∗G_{CS _ MIN}/ I_OCSET

135

= (

∗0.61*10⁻³∗1.3+ 0.55*10⁻³)∗30.2 /(41*10⁻⁶) = 13.3kΩ

6

No Load Output Voltage Setting Resistor RFB and Adaptive Voltage Positioning Resistor RDRP

From Figure 14, the bias current of FB pin is 41uA with ROSC=30.1kꢀ.

0.61 *10 ⁻³∗ 20 *10 ⁻³− 0.55 *10 ⁻³∗ 6 ∗ 0.91 *10 ⁻³

41 *10 ⁻⁶∗ 0.61 *10 ⁻³

R_{L _ MAX}∗V_{O _ NLOFST}− V_{CS _ TOFST}∗ n ∗ R_O

R_FB

=

= 365Ω

I _FB∗ R_{L _ MAX}

365∗ 0.61*10⁻³∗30.2

6 ∗ 0.91*10⁻³

R

_FB∗ R_{L _ MAX}∗G_{CS _ MIN}

R_DRP

=

=1.21kΩ

n ∗ R_O

Page 27 of 39

1/31/05

IR3081A

Body Braking Related Resistors RBBFB and RBBDRP

N/A. The body braking during Dynamic VID is disabled.

IR3086A EXTERNAL COMPONENTS

PWM Ramp Resistor RPWMRMP and Capacitor CPWMRMP

Set PWM ramp magnitude VPWMRMP=0.8V. Choose 220pF for PWM ramp capacitor CPWMRMP, and calculate the

resistor RPWMRMP,

V_O

R_PWMRMP

=

V_IN∗ f_SW∗C_PWMRMP∗[ln(V_IN−V_DAC) − ln(V_IN−V_DAC−V_PWMRMP)]

1.33

=

=16.1kΩ , choose RPWMRMP=16.2kꢀ

12∗400*10³∗220*10⁻¹²∗[ln(12 −1.35) − ln(12 −1.35− 0.8)]

Inductor Current Sensing Capacitor CCS+ and Resistors RCS+ and RCS-

Choose CCS+=47nF, and calculate RCS+,

L R_L220*10⁻⁹/(0.47*10⁻³)

C_CS+

R_CS+

=

= 10.0kΩ

47*10⁻⁹

The bias currents of CSIN+ and CSIN- are 0.25uA and 0.4uA respectively. Calculate resistor RCS-,

0.25

0.4

0.25

0.4

R_CS−

=

∗ R_CS+

=

∗10.0*10³= 6.2kΩ , choose RCS-=6.19kꢀ

Over Temperature Setting Resistors RHOTSET1 and RHOTSET2

Use central over-temperature setting and set the temperature threshold at 115 ºC, which corresponds to the IC die

temperature of 116 ºC. Calculate the HOTSET threshold voltage corresponding to the temperature thresholds.

V_HOTSET= 4.73*10⁻³*T_J+1.241 = 4.73*10⁻³∗116 +1.241 = 1.79V

Pre-select RHOTSET1=10.0kꢀ,

10*10³∗1.79

6.8 −1.79

R

_HOTSET1∗V_HOTSET

=

R_{HOTSET 2}

=

= 3.57kΩ

V_BIAS−V_HOTSET

Phase Delay Timing Resistors RPHASE1 and RPHASE2

Use central over-temperature setting and set the temperature threshold at 115 ºC, which corresponds to the IC die

temperature of 116 ºC. Calculate the HOTSET threshold voltage corresponding to the temperature thresholds.

The phase delay resistor ratios for phases 1 to 6 at 400kHz of switching frequencies are RAPHASE1=0.628,

RAPHASE2=0.415, RAPHASE3=0.202, RAPHASE4=0.246, RAPHASE5=0.441 and RAPHASE5=0.637 starting from down-

slope. Pre-select RPHASE11=RPHASE21=RPHASE31=RPHASE41=RPHASE51= RPHASE61=10kꢀ,

RA_PHASE1

1− RA_PHASE1

0.628

1− 0.628

R_PHASE12

=

∗ R_PHASE11

=

∗10*10³= 16.9kΩ

RPHASE22=7.15kꢀ, RPHASE32=2.55kꢀ, RPHASE42=3.24kꢀ, PPHASE52=7.87kꢀ, RPHASE62=17.4kꢀ

Page 28 of 39

1/31/05

IR3081A

Bootstrap Capacitor CBST

Choose CBST=0.1uF

Decoupling Capacitors for Phase IC and Power Stage

Choose CVCC=0.1uF, CVCCL=0.1uF

VOLTAGE LOOP COMPENSATION

Type II compensation is used for the converter with AL-Polymer output capacitors. Choose the crossover frequency

fc=40kHz, which is 1/10 of the switching frequency per phase, and determine Rcp and CCP.

(2π ∗ f_C)²∗ L_E∗C_E∗ R_FB∗V_RAMP(2π ∗40∗10³)²∗(220∗10⁻⁹/6)∗(560∗10⁻⁶∗10)∗365∗0.8

R_CP

=

= 2.0kΩ

V_O* 1+ (2π * f_C*C *R_C)²

(1.35− 20∗10⁻³)* 1+ (2π *40*10³*560*10⁻⁶*7*10⁻³)²

10∗ (220∗10⁻⁹/ 6)∗(560∗10⁻⁶*10)

2.0∗10³

10∗ L_E∗C_E

, Choose CCP=68nF

= 71nF

C_CP

=

R_CP

Choose CCP1=47pF to reduce high frequency noise.

CURRENT SHARE LOOP COMPENSATION

The crossover frequency of the current share loop fCI should be at least one decade lower than that of the voltage

loop fC. Choose the crossover frequency of current share loop fCI=4kHz, and calculate CSCOMP,

R

_PWMRMP*C_PWMRMP* f_SW*V _PWMRMP16.2*10³*220*10⁻¹²*400*10³*0.8

F_MI

=

= 0.011

(V_I−V_PWMRMP−V_DAC)*(V_I−V_DAC

)

(12 − 0.8 −1.35)*(12 −1.35)

0.65* R_PWMRMP*V_I* I_O*G_{CS _ ROOM}* R_LE*[1+ 2π * f_CI*C_E*(V_OI_O)]* F_MI

V_O∗2π ∗ f_CI*1.05*10⁶

C_SCOMP

=

0.65*16.2*10³*12*105*34*(0.47*10⁻³6)*[1+ 2π *4*10³*560*10⁻⁶*10*(1.33−105*9.1*10⁻⁴) 105]*0.011

(1.33−105*9.1*10⁻⁴)∗2π ∗4*10³*1.05*10⁶

=

= 31.4nF

Choose CSCOMP=33nF.

Page 29 of 39

1/31/05

IR3081A

DESIGN EXAMPLE 2 - EVRD 10 HIGH FREQUENCY ALL-CERAMIC CONVERTER

SPECIFICATIONS

Input Voltage: VI=12 V

DAC Voltage: VDAC=1.3 V

No Load Output Voltage Offset: VO_NLOFST=20 mV

Output Current: IO=105 ADC

Maximum Output Current: IOMAX=120 ADC

Output Impedance: RO=0.91 mꢀ

VCC Ready to VCC Power Good Delay: tVccPG=0-10mS

Soft Start Time: tSS=3mS

Over Current Delay: tOCDEL<0.5mS

Dynamic VID Down-Slope Slew Rate: SRDOWN=2.5mV/uS

Over Temperature Threshold: TPCB=115 ºC

POWER STAGE

Phase Number: n=6

Switching Frequency: fSW=800 kHz

Output Inductors: L=100 nH, RL=0.5 mꢀ

Output Capacitors: Ceramic, C=22uF, RC= 2mꢀ, Number Cn=62

IR3081A EXTERNAL COMPONENTS

Oscillator Resistor Rosc

Once the switching frequency is chosen, ROSC can be determined from the curve in Figure 13 data sheet. For

switching frequency of 800kHz per phase, choose ROSC=13.3kꢀ

Soft Start Capacitor CSS/DEL

Determine the soft start capacitor from the required soft start time.

I

_CHG∗t_SS70*10⁻⁶∗3*10⁻³

V_O

, choose CSS/DEL=0.15uF

C_{SS / DEL}

=

= 0.16uF

1.3− 20*10⁻³

The soft start delay time is

_{SS / DEL}∗1.3 0.15*10⁻⁶∗1.3

C

t_SSDEL

=

= 2.8mS

70*10⁻⁶

I_CHG

The power good delay time is

C

_{SS / DEL}*(3.735 −V_O−1.3) 0.15*10⁻⁶*(3.735 −1.33−1.3)

t_VccPG

=

= 2.4ms

70*10⁻⁶

I_CHG

Over current delay time is

_{SS / DEL}*0.115 0.15*10⁻⁶*0.115

C

t_OCDEL

=

= 0.43ms

40*10⁻⁶

I_OCDISCHG

VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC

From Figure 15, the sink current of VDAC pin corresponding to 800kHz (ROSC=13.3kꢀ) is 170uA. Calculate the

VDAC down-slope slew-rate programming capacitor from the required down-slope slew rate.

Page 30 of 39

1/31/05

IR3081A

170*10⁻⁶

I_SINK

SR_DOWN

C_VDAC

=

= 68nF

2.5*10⁻³/10⁻⁶

Calculate the programming resistor.

3.2*10⁻¹⁵

C_VDAC

3.2*10⁻¹⁵

R_VDAC= 0.5 +

= 0.5 +

= 1.2Ω

2

(68*10⁻⁹

)

From Figure 15, the source current of VDAC pin is 250uA. The VDAC up-slope slew rate is

250*10⁻⁶

68*10⁻⁹

I_SOURCE

C_VDAC

SR_UP

=

= 3.7mV / uS

Over Current Setting Resistor ROCSET

The room temperature is 25ºC and the target PCB temperature is 100 ºC. The phase IC die temperature is about 1

ºC higher than that of phase IC, and the inductor temperature is close to PCB temperature.

Calculate Inductor DC resistance at 100 ºC,

R_{L _ MAX}= R_{L _ ROOM}∗[1+3850*10⁻⁶∗(T_{L _ MAX}−T_ROOM)] = 0.5*10⁻³∗[1+3850*10⁻⁶∗(100− 25)] = 0.64mΩ

The current sense amplifier gain is 34 at 25ºC, and its gain at 101ºC is calculated as,

G_{CS _ MIN}= G_{CS _ ROOM}∗[1−1470 *10⁻⁶∗(T_{IC _ MAX}−T_ROOM)] = 34∗[1−1470 *10⁻⁶∗(101− 25)] = 30.2

Set the over current limit at 135A. From Figure 14, the bias current of OCSET pin (IOCSET) is 90uA with

ROSC=13.3kꢀ. The total current sense amplifier input offset voltage is 0.55mV, which includes the offset created by

the current sense amplifier input resistor mismatch.

Calculate constant KP, the ratio of inductor peak current over average current in each phase,

(V_I−V_O)∗V_O/(L∗V_I∗ f_SW∗2) (12 −1.28)∗1.28 /(100*10⁻⁹∗12∗800*10³∗2)

K_P=

=

= 0.32

I_LIMIT/ n

135 / 6

R_LIMIT

n

R_OCSET= [

∗ R_{L _ MAX}∗(1+ K_P) +V_{CS _ TOFST}]∗G_{CS _ MIN}/ I_OCSET

135

6

= (

∗0.64*10⁻³∗1.32 + 0.55*10⁻³)*30.2 /(90*10⁻⁶) = 6.34kΩ

No Load Output Voltage Setting Resistor RFB and Adaptive Voltage Positioning Resistor RDRP

From Figure 14, the bias current of FB pin is 90uA with ROSC=13.3kꢀ.

0.64*10⁻³∗20*10⁻³− 0.55*10⁻³∗6∗0.91*10⁻³

R_{L _ MAX}∗V_{O _ NLOFST}−V_{CS _ TOFST}∗n∗ R_O

R_FB

=

=162Ω

90*10⁻⁶*0.64*10⁻³

I

_FB∗ R_{L _ MAX}

162∗0.64*10⁻³*30.2

6∗0.91*10⁻³

R

_FB∗ R_{L _ MAX}∗G_{CS _ MIN}

R_DRP

=

= 576Ω

n∗ R_O

Body Braking Related Resistors RBBFB and RBBDRP

N/A. The body braking during Dynamic VID is disabled.

Page 31 of 39

1/31/05

IR3081A

IR3086A EXTERNAL COMPONENTS

PWM Ramp Resistor RPWMRMP and Capacitor CPWMRMP

Set PWM ramp magnitude VPWMRMP=0.75V. Choose 100pF for PWM ramp capacitor CPWMRMP, and calculate the

resistor RPWMRMP,

V_O

R_PWMRMP

=

V_IN* f_SW*C_PWMRMP*[ln(V_IN−V_DAC) − ln(V_IN−V_DAC−V_PWMRMP)]

1.28

=

=18.2kΩ

3

−12

12∗800*10 ∗100*10

∗[ln(12 −1.3) − ln(12 −1.3− 0.75)]

Inductor Current Sensing Capacitor CCS+ and Resistors RCS+ and RCS-

Choose 47nF for capacitor CCS+, and calculate RCS+,

L R_L100*10⁻⁹/(0.5*10⁻³)

C_{CS +}

R_{CS +}

=

= 4.22kΩ

47*10⁻⁹

The bias currents of CSIN+ and CSIN- are 0.25uA and 0.4uA respectively. Calculate resistor RCS-,

0.25

0.4

0.25

0.4

R_CS−

=

∗ R_CS+

=

∗4.22*10³= 2.61kΩ

Combined Over Temperature and Phase Delay Setting Resistors RPHASEx1, RPHASEx2 and RPHASEx3

The over temperature setting resistor divider is combined with the phase delay resistor divider. Set the temperature

threshold at 115 ºC, which corresponds to the IC die temperature of 116 ºC, and calculate the HOTSET threshold

voltage corresponding to the temperature thresholds.

V_HOTSET= 4.73*10⁻³∗T_J+1.241 = 4.73*10⁻³∗116 +1.241 = 1.79V

The phase delay resistor ratios for phases 1 to 6 at 800kHz of switching frequencies are RAPHASE1=0.665,

RAPHASE2=0.432, RAPHASE3=0.198, RAPHASE4=0.206, RAPHASE5=0.401 and RAPHASE5=0.597 starting from down-

slope.

The over temperature setting voltage of phases 1, 2, 5, and 6 is lower than the phase delay setting voltage,

VBIAS*RAPHASEx. Pre-select RPHASE11=10kꢀ,

(RA_PHASEx∗V_BIAS−V_HOTSET)* R_PHASEx1(0.665∗6.8 −1.79)∗10*10³

R_PHASEx2

=

= 12.1kΩ

V_BIAS∗(1− RA_PHASEx

)

6.8∗(1− 0.665)

V_HOTSET∗ R_PHASEx1

1.79∗12.1*10³

6.8*(1− 0.665)

R_PHASEx3

=

= 7.87kΩ

V_BIAS*(1− RA_PHASEx)

RPHASE21=10kꢀ, RPHASE22=2.94kꢀ, RPHASE23=4.64kꢀ

RPHASE51=10kꢀ, RPHASE52=2.32kꢀ, RPHASE53=4.42kꢀ

RPHASE61=10kꢀ, RPHASE62=8.25kꢀ, RPHASE63=6.49kꢀ

The over temperature setting voltage of Phases 3 and 4 is higher than the phase delay setting voltage,

VBIAS*RAPHASEx. Pre-select RPHASEX1=10kꢀ,

(1.79 − 0.198∗6.8)∗10*10³

6.8−1.79

(V_HOTSET− RA_PHASE3∗V_BIAS)∗ R_PHASE31

R_PHASE32

=

= 887Ω

V_BIAS−V_HOTSET

RA_PHASE3∗V_BIAS* R_PHASE310.198∗6.8∗10*10³

R_PHASE33

=

= 2.67kΩ

V_BIAS−V_HOTSET

6.8 −1.79

Page 32 of 39

1/31/05

IR3081A

RPHASE41=10kꢀ, RPHASE42=768ꢀ, RPHASE43=2.80kꢀ

Bootstrap Capacitor CBST

Choose CBST=0.1uF

Decoupling Capacitors for Phase IC and Power Stage

Choose CVCC=0.1uF, CVCCL=0.1uF

VOLTAGE LOOP COMPENSATION

Type III compensation is used for the converter with only ceramic output capacitors. The crossover frequency and

phase margin of the voltage loop can be estimated as follows.

R_DRP

576

f_C1

=

= 146kHz

2π ∗ (62 ∗ 22 *10⁻⁶) ∗ 34 ∗162 ∗ (0.5 *10⁻³/ 6)

2π ∗ C_E∗ G_CS∗ R_FB∗ R_LE

180

π

θ_C1= 90 − A tan(0.5)∗

= 63°

2

3

2

3

Choose R_FB1

=

∗ R_FB

=

∗162 = 110Ω

Choose the desired crossover frequency fc (=140kHz) around fc1 estimated above, and calculate

1

, choose CFB=5.6nF

= 5.2nF

C_FB

=

4π ∗140*10³∗110

4π ∗ f_C∗ R_FB1

(R_FB+ R_FB1)∗C_FB(162 +110)∗5.6*10⁻⁹

C_DRP

=

= 2.7nF

R_DRP

576

(2π ∗ f_C)²∗ L_E∗C_E∗ R_FB∗V_RAMP(2π ∗140*10³)²∗(100*10⁻⁹/ 6)∗(22*10⁻⁶∗62)∗162*0.75

R_CP

C_CP

=

= 1.65kΩ

1.3− 20*10⁻³

V_O

10∗ (100*10⁻⁹/ 6)∗(22*10⁻⁶*62)

=

10∗ L_E∗C_E

=

= 27nF

1.65∗10³

R_CP

Choose CCP1=47pF to reduce high frequency noise.

CURRENT SHARE LOOP COMPENSATION

The crossover frequency of the current share loop f should be at least one decade lower than that of the voltage

loop f

C

. Choose the crossover frequency of current s^Ch^Iare loop fCI=3.5kHz

, and calculate CSCOMP,

R

_PWMRMP*C_PWMRMP* f_SW*V _PWMRMP18.2*10³*100*10⁻¹²*800*10³*0.75

F_MI

=

= 0.011

(V_I−V_PWMRMP−V_DAC)*(V_I−V_DAC

)

(12 − 0.75 −1.3)*(12 −1.3)

0.65* R_PWMRMP*V_I* I_O*G_{CS _ ROOM}* R_LE*[1+ 2

π

* f_CI*C_E*(V_OI_O)]* F_MI

C_SCOMP

=

V_O∗2

∗ f_CI*1.05*10⁶

π

0.65*18.2*10³*12*105*34*(0.5*10⁻³6)*[1+ 2π *3500*22*10⁻⁶*62*(1.33−105*9.1*10⁻⁴) 105]*0.011

(1.33−105*9.1*10⁻⁴)∗2π ∗3500*1.05*10⁶

=

= 20.6nF

Page 33 of 39

1/31/05

IR3081A

LAYOUT GUIDELINES

The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB

layout, therefore minimizing the noise coupled to the IC.

•

Dedicate at least one middle layer for a ground plane LGND.

Connect the ground tab under the control IC to LGND plane through a via.

Place the following critical components on the same layer as control IC and position them as close as possible

to the respective pins, ROSC, ROCSET, RVDAC, CVDAC, CVCC, and CSS/DEL. Avoid using any via for the

connection.

•

Place the compensation components on the same layer as control IC and position them as close as possible to

EAOUT, FB and VDRP pins. Avoid using any via for the connection.

Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS-, and avoid crossing over

the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes.

Control bus signals, VDAC, RMPOUT, IIN, VBIAS, and especially EAOUT, should not cross over the fast

transition nodes.

LGND PLANE

To VIN

VCC

LGND

VDAC

ROSC

RMPOUT

SS/DEL

PWRGD

VOSNS-

To

LGND

ENABLE

To Voltage

To SYSTEM

Remote Sense

Page 34 of 39

1/31/05

IR3081A

PCB Metal and Component Placement

• Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should

be ≥ 0.2mm to minimize shorting.

• Lead land length should be equal to maximum part lead length + 0.2 mm outboard extension + 0.05mm

inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard

extension will accommodate any part misalignment and ensure a fillet.

• Center pad land length and width should be equal to maximum part pad length and width. However, the

minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper and ≥

0.23mm for 3 oz. Copper)

• A single 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to

minimize the noise effect on the IC.

Page 35 of 39

1/31/05

IR3081A

Solder Resist

• The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder

resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non

Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads.

• The minimum solder resist width is 0.13mm, therefore it is recommended that the solder resist is

completely removed from between the lead lands forming a single opening for each “group” of lead

lands.

• At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a

fillet so a solder resist width of ≥ 0.17mm remains.

• The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto

the copper of 0.06mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is allowable

to have the solder resist opening for the land pad to be smaller than the part pad.

• Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high

aspect ratio of the solder resist strip separating the lead lands from the pad land.

• The single via in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm larger than

the diameter of the via.

Page 36 of 39

1/31/05

IR3081A

Stencil Design

• The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands.

Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm

pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower;

openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release.

• The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead

land.

• The land pad aperture should be striped with 0.25mm wide openings and spaces to deposit

approximately 50% area of solder on the center pad. If too much solder is deposited on the center pad

the part will float and the lead lands will be open.

• The maximum length and width of the land pad stencil aperture should be equal to the solder resist

opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the

lead lands when the part is pushed into the solder paste.

Page 37 of 39

1/31/05

IR3081A

PERFORMANCE CHARACTERISTICS

Figure 13 - Oscillator Frequency versus ROSC

1000

950

900

850

800

750

700

650

600

550

500

450

400

350

300

250

200

150

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100

ROSC (K Ohms)

Figure 14 - IFB, BBFB, & OCSET Bias Currents vs ROSC

125

115

105

95

85

75

65

55

45

35

25

15

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100

ROSC (K Ohm)

Figure 15 - VDAC Source & Sink Currents vc ROSC (includes OCSET

Bias Current)

325

300

275

250

225

200

175

150

125

100

75

ISINK

ISOURCE

50

25

0

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100

ROSC (K ohm)

Figure 16 - Bias Current Accuracy versus ROsC (includes

temperature and input voltage variation)

14%

12%

10%

8%

FB, BBFB, OCSET Bias

Current

VDAC Sink Current

6%

VDAC Source Current

4%

2%

0%

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100

ROSC (K Ohm)

Page 38 of 39

1/31/05

IR3081A

PACKAGE INFORMATION

28L MLPQ (5 x 5 mm Body) – θ_JA= 30^oC/W, θ_JC= 3^oC/W

Data and specifications subject to change without notice.

This product has been designed and qualified for the Consumer market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.

www.irf.com

Page 39 of 39

1/31/05


型号：	IR3081AM
厂家：	Infineon
描述：	XPHASETM VR 10 CONTROL IC XPHASETM VR 10控制IC 模拟IC 信号电路
文件：	总39页 (文件大小：1525K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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