IR3082_技术文档

Data Sheet No. PD94710

IR3082

XPHASE^TMAMD OPTERON^TM/ATHLON 64^TMCONTROL IC

DESCRIPTION

The IR3082 Control IC combined with an IR XPhase^TMPhase IC provides a full featured and flexible way

to implement a complete Opteron or Athlon64 power solution. The “Control” IC provides overall system

control and interfaces with any number of “Phase ICs” which each drive and monitor a single phase of a

multiphase converter. With simple 5 bit voltage programming and a few external components, the IR3082

is also well suited for general purpose multiphase applications. The XPhase^TMarchitecture results in a

power supply that is smaller, less expensive, and easier to design while providing higher efficiency than

conventional approaches.

FEATURES

•

5 bit VID with 1% overall system set point accuracy

•

Programmable Dynamic VID Slew Rate

+/-300mV Differential Remote Sense

Programmable 150kHz to 1MHz oscillator

Programmable VID Offset and Load Line output impedance

Programmable Softstart

Programmable Hiccup Over-Current Protection with Delay to prevent false triggering

Simplified Power Good output provides indication of proper operation and avoids false triggering

Operates from 12V input with 9.75V Under-Voltage Lockout

7.0V/5mA Bias Regulator provides System Reference Voltage

Small thermally enhanced 20L MLPQ package

APPLICATION CIRCUIT

POWER GOOD

12V

10

0.1uF

L

E

D

/

S

C

ENABLE

0

2

9

1

8

1

7

6

1

L

E

L

T

U

O

P

D

G

R

P

D

N

E

B

A

D

/

G

L

1

2

3

4

5

15

14

13

12

11

0.1uF

S

VID0

VID1

VID2

VID3

VID4

N

E

W

VID0

VID1

VID2

VID3

VID4

VCC

VBIAS

EAOUT

FB

S

M

R

IR3082

5 Wire Analog Bus

(to PHASE ICs)

CONTROL

IC

VDRP

-

S

N

S

O

V

T

C

S

O

R

E

S

C

O

C

A

D

V

N

RVDRP

I

6

7

8

9

0

1

C

ROCSET

S

O

R

RVDAC

RVFB

VCC SENSE

VSS SENSE

CVDAC

Page 1 of 1

12/17/04

IR3082

ORDERING INFORAMATION

Device

Order Quantity

3000 per reel

IR3082MTR

* IR3082M

100 piece strips

* Samples only

ABSOLUTE MAXIMUM RATINGS

Operating Junction Temperature……………..150^oC

Storage Temperature Range………………….-65^oC to 150^oC

ESD Rating………………………………………HBM Class 1C JEDEC standard

PIN #

1-5

6

PIN NAME

VID0-4

VOSNS-

ROSC

VDAC

OCSET

IIN

VDRP

FB

EAOUT

VBIAS

VCC

V_MAX

20V

0.5V

20V

10V

20V

n/a

V_MIN

-0.3V

-0.5V

-0.3V

n/a

I_SOURCE

1mA

10mA

1mA

5mA

1mA

20mA

50mA

1mA

50mA

1mA

I_SINK

1mA

10mA

1mA

5mA

1mA

20mA

10mA

50mA

1mA

20mA

1mA

7

8

9

10

11

12

13

14

15

16

17

18

19

20

LGND

RMPOUT

SS/DEL

PWRGD

ENABLE

20v

-0.3V

20V

Page 2 of 2

12/17/04

IR3082

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, these specifications apply over: 9.6V ≤ V_CC≤ 16V, -0.3V ≤ VOSNS- ≤ 0.3V,

0 ^oC ≤ T_J≤ 100 ^oC, ROSC = 24KΩ, CSS/DEL = 0.1µF +/-10%

PARAMETER

VDAC Reference

System Set-Point Accuracy

(Deviation from Table 1 per

test circuit in Figure 1 which

emulates in-VR operation)

TEST CONDITION

MIN

TYP

MAX

UNIT

10KΩ ≤ ROSC ≤ 91KΩ, RFB selected to

-1

1

%

provide 50mV VID offset

Source Current

Sink Current

Includes OCSET current

101

92

1.04

-5

0.5

110

100

1.24

0

119

108

1.44

5

µA

V

µA

µs

VIDx Input Threshold

VIDx Input Bias Current

VIDx 11111 Blanking Delay

Error Amplifier

0V ≤ VID0-4 ≤ VCC

Measure Time till PWRGD drives low

0.7

1

Input Offset Voltage

Measure V(FB) – V(VDAC) with EAOUT

tied to FB. Applies to all VID codes.

Note 2.

-5

1.5

6

mV

FB Bias Current

DC Gain

Gain Bandwidth Product

Corner Frequency

Slew Rate

Source Current

Sink Current

-53.5

90

6

-51

100

10

400

3.2

0.7

0.9

375

125

-48.5

110

µA

dB

MHz

Hz

V/µs

mA

mV

Note 1

45 deg Phase Shift, Note 1

Note 1

1.4

0.4

0.5

250

30

5

1

1.4

525

200

Max Voltage

Min Voltage

VBIAS–VEAOUT (referenced to VBIAS)

Normal operation or Fault mode

VDRP Buffer Amplifier

Input Offset Voltage

Source Current

Sink Current

Bandwidth

Slew Rate

IIN Bias Current

VBIAS Regulator

Output Voltage

Current Limit

V(VDRP) – V(IIN), 0.5V ≤ V(IIN) ≤ 5V

0.5V ≤ V(IIN) ≤ 5V

Note 1

-10

1.2

0.2

1

-1

3.0

1.4

6

10

-0.3

6

5.0

4.1

mV

mA

MHz

V/µs

µA

Note 1

-2

0.4

-5mA≤ I(VBIAS) ≤ 0

6.6

-35

7.0

-20

7.4

-6

V

mA

Enable Input

Threshold Voltage

Threshold Hysteresis

Bias Current

ENABLE rising

ENABLE falling

1.15

1.08

40

1.27

1.205

65

1.39

1.31

90

V

mV

µA

0V ≤ V(ENABLE) ≤ VCC

-5

0

5

Page 3 of 3

12/17/04

IR3082

PARAMETER

Soft Start and Delay

Start Delay (See Fig 10)

Soft Start Time (See Fig 10)

PWRGD Delay (See Fig 10)

OC Delay Time

TEST CONDITION

MIN

TYP

MAX

UNIT

1.2

0.85

1.0

150

0.95

1.9

1.95

2.0

250

1.3

2.6

3.0

350

1.6

ms

us

V

VID = 1.3V (VID4-0 = 01010)

SS/DEL to FB Input Offset

With FB = 0V, adjust V(SS/DEL) until

EAOUT drives high

Voltage

Charge Current

40

4

9.5

66

6

11

100

9

12.5

µA

µA/µA

Discharge Current

Charge/Discharge Current

Ratio

OC Discharge Current

Charge Voltage

Note 1

20

3.65

50

40

3.9

70

60

4.15

90

µA

V

mV

Delay Comparator Threshold

Relative to Charge Voltage, SS/DEL

rising

Relative to Charge Voltage, SS/DEL

Delay Comparator Threshold

85

115

145

mV

falling

Delay Comparator Hysteresis

Discharge Comparator

Threshold

15

175

35

225

50

275

mV

Over-Current Comparator

Input Offset Voltage

OCSET Bias Current

PWRGD Output

1V ≤ V(OCSET) ≤ 5V

-10

-54

0

10

-49

mV

µA

-51.5

Output Voltage

I(PWRGD) = 4mA

V(PWRGD) = 5.5V

150

0

300

10

mV

µA

Leakage Current

Oscillator

Switching Frequency

450

70

500

71

550

74

kHz

%

Peak Voltage (5V typical,

measured as % of VBIAS)

Valley Voltage (1V typical,

measured as % of VBIAS)

10

13

15

%

VCC Under-Voltage Lockout

Start Threshold

Stop Threshold

Hysteresis

9.0

8.4

550

9.75

9.0

750

10.4

9.6

1150

V

mV

Start – Stop

General

VCC Supply Current

VOSNS- Current

8

-4.5

10

-3.5

12.5

-2.5

mA

-0.3V ≤ VOSNS- ≤ 0.3V, All VID Codes

Note 1: Guaranteed by design, but not tested in production

Note 2: VDAC Output is trimmed to compensate for Error Amp input offsets errors

Page 4 of 4

12/17/04

IR3082

EAOUT

FB

+

-

IR3082

ERROR

AMP

RFB

OCSET

VDAC

+

-

+

"FAST"

VDAC

-

ISOURCE

ISINK

VDAC

BUFFER

AMP

SYSTEM

IOFFSET

IOCSET

IROSC

RVDAC

SET POINT

VOLTAGE

CVDAC

ROSC

BUFFER

AMP

CURRENT

SOURCE

+

GENERATOR

-

ROSC

+

ROSC

1.2V

-

VOSNS-

Figure 1 – System Set Point Test Circuit

PIN DESCRIPTION

PIN# PIN SYMBOL PIN DESCRIPTION

1-5

6

7

VID4-0

VOSNS-

ROSC

Inputs to VID D to A Converter.

Remote Sense Input. Connect to ground at the Load.

Connect a resistor to VOSNS- to program oscillator frequency and OCSET, FB, and

VDAC bias currents.

8

VDAC

Regulated voltage programmed by the VID inputs. Connect an external RC network

to VOSNS- to program Dynamic VID slew rate and provide compensation for the

internal Buffer Amplifier.

9

OCSET

Programs the hiccup over-current threshold through an external resistor tied to

VDAC and an internal current source. Over-current protection can be disabled by

connecting a resistor from this pin to VDAC to program the threshold higher than the

possible signal into the IIN pin from the Phase ICs but no greater than 5V (do not

float this pin as improper operation will occur).

10

IIN

Current Sense input from the Phase IC(s). If current feedback from the Phase ICs is

not required for implementing droop or over-current protection connect to the LGND

pin. To ensure proper operation do not float this pin.

11

12

VDRP

FB

Buffered IIN signal. Connect an external RC network to FB to program converter

output impedance.

Inverting input to the Error Amplifier. Converter output voltage is offset from the

VDAC voltage through an external resistor connected to the converter output voltage

at the load and an internal current source.

13

14

EAOUT

VBIAS

Output of the Error Amplifier.

6.8V/5mA Regulated output used as a system reference voltage for internal circuitry

and the Phase ICs.

15

16

17

18

VCC

LGND

RMPOUT

SS/DEL

Power Input for internal circuitry.

Local Ground for internal circuitry and IC substrate connection.

Oscillator Output voltage. Used by Phase ICs to program Phase Delay

Controls Converter Start-up and Over-Current Timing. Connect an external capacitor

to LGND to program.

19

20

PWRGD

ENABLE

Open Collector output that drives low during Start-Up and any external fault

condition. Connect external pull-up.

Enable Input. A logic low applied to this pin puts the IC into Fault mode. Do not float

this pin as the logic state will be undefined.

Page 5 of 5

12/17/04

IR3082

SYSTEM THEORY OF OPERATION

XPhase^TMArchitecture

The XPhase^TMarchitecture is designed for multiphase interleaved buck converters which are used in applications

requiring small size, design flexibility, low voltage, high current, and fast transient response. The architecture can

be used in any multiphase converter ranging from 1 to 16 or more phases where flexibility facilitates the design

trade-off of multiphase converters. The scalable architecture can be applied to other applications which require

high current or multiple output voltages.

As shown in Figure 2, the XPhase^TMarchitecture consists of a Control IC and a scalable array of phase converters

each using a single Phase IC. The Control IC communicates with the Phase ICs through a 5-wire analog bus, i.e.

bias voltage, phase timing, average current, error amplifier output, and VID voltage. The Control IC incorporates all

the system functions, i.e. VID, PWM ramp oscillator, error amplifier, bias voltage, and fault protections etc. The

Phase IC implements the functions required by the converter of each phase, i.e. the gate drivers, PWM comparator

and latch, over-voltage protection, and current sensing and sharing.

There is no unused or redundant silicon with the XPhase^TMarchitecture compared to others such as a 4 phase

controller that can be configured for 2, 3, or 4 phase operation. PCB Layout is easier since the 5 wire bus

eliminates the need for point-to-point wiring between the Control IC and each Phase. The critical gate drive and

current sense connections are short and local to the Phase ICs. This improves the PCB layout by lowering the

parasitic inductance of the gate drive circuits and reducing the noise of the current sense signal.

POWER GOOD

VR HOT

PHASE FAULT

12V

ENABLE

CIN

IR3082

CONTROL

IC

>> BIAS VOLTAGE

>> PHASE TIMING

<< CURRENT SENSE

>> PWM CONTROL

>> VID VOLTAGE

VID0

VID1

VID2

VID3

VID4

+SEN

CURRENT SHARE

VDD_CORE

IR3086

PHASE

IC

COUT

GND

-SEN

CCS RCS

CURRENT SHARE

IR3086

PHASE

IC

CCS RCS

ADDITIONAL PHASES

CONTROL BUS

INPUT/OUTPUT

Figure 2 – System Block Diagram

Page 6 of 6

12/17/04

IR3082

PWM Control Method

The PWM block diagram of the XPhase^TMarchitecture is shown in Figure 3. Feed-forward voltage mode control with

trailing edge modulation is used. A high-gain wide-bandwidth voltage type error amplifier in the Control IC is used

for the voltage control loop. An external RC circuit connected to the input voltage and ground is used to program the

slope of the PWM ramp and to provide the feed-forward control at each phase. The PWM ramp slope will change

with the input voltage and automatically compensate for changes in the input voltage. The input voltage can change

due to variations in the silver box output voltage or due to drops in the PCB related to changes in load current.

VIN

CONTROL IC

PHASE IC

SYSTEM

REFERENCE

VOLTAGE

BIASIN

50%

DUTY

CYCLE

PWM

LATCH

RAMP GENERATOR

VPEAK

RMPOUT

RAMPIN+

GATEH

GATEL

VOSNS+

VOUT

CLOCK

PULSE

GENERATOR

S

+

-

PWM

COMPARATOR

RESET

DOMINANT

VVALLEY

RPHS1

RAMPIN-

EAIN

COUT

-

R

VBIAS

VDAC

+

ENABLE

+

GND

RPHS2

+

-

PWMRMP

RPWMRMP

VBIAS

REGULATOR

RAMP

BODY

BRAKING

COMPARATOR

SLOPE

ADJUST

VOSNS-

EAOUT

VOSNS-

RAMP

DISCHARGE

CLAMP

-

CPWMRMP

SCOMP

VDAC

+

-

+

-

SHARE

CSCOMP

ADJUST

ERROR

AMP

ERROR

AMP

X

0.9

-

+

RVFB

RDRP

+

-

ISHARE

DACIN

CURRENT

SENSE

20mV

FB

CSIN+

CSIN-

10K

AMPLIFIER

CCS RCS

+

-

+

IFB

IROSC

X34

+

VDRP

AMP

VDRP

+

-

IIN

PHASE IC

SYSTEM

REFERENCE

VOLTAGE

BIASIN

PWM

LATCH

RAMPIN+

GATEH

GATEL

CLOCK

PULSE

GENERATOR

S

+

-

RPHS1

RPHS2

PWM

COMPARATOR

RESET

DOMINANT

RAMPIN-

EAIN

-

R

+

ENABLE

+

PWMRMP

RAMP

SLOPE

RPWMRMP

BODY

BRAKING

COMPARATOR

ADJUST

RAMP

DISCHARGE

CLAMP

-

CPWMRMP

SCOMP

-

+

SHARE

CSCOMP

ADJUST

ERROR

AMP

X

0.9

-

+

CURRENT

SENSE

AMPLIFIER

ISHARE

DACIN

20mV

-

CSIN+

CSIN-

10K

CCS RCS

+

-

+

X34

+

Figure 3 – IR3082 PWM Block Diagram

Frequency and Phase Timing Control

The oscillator is located in the Control IC and its frequency is programmable from 150kHz to 1MHZ by an external

resistor. The output of the oscillator is a 50% duty cycle triangle waveform with peak and valley voltages of

approximately 5V and 1V. This signal is used to program both the switching frequency and phase timing of the

Phase ICs. The Phase IC is programmed by resistor divider RRAMP1 and RRAMP2 connected between the VBIAS

reference voltage and the Phase IC LGND pin. A comparator in the Phase ICs detects the crossing of the oscillator

waveform with the voltage generated by the resistor divider and triggers a clock pulse that starts the PWM cycle.

The peak and valley voltages track the VBIAS voltage reducing potential Phase IC timing errors. Figure 4 shows the

Phase timing for an 8 phase converter. Note that both slopes of the triangle waveform can be used for

synchronization by swapping the RAMP+ and RAMP- pins, as shown in Figure 3.

Page 7 of 7

12/17/04

IR3082

50% RAMP

DUTY CYCLE

SLOPE = 80mV / % DC

VPEAK (5.0V)

SLOPE = 1.6mV / ns @ 200kHz

SLOPE = 8.0mV / ns @ 1MHz

VPHASE4&5 (4.5V)

)

C

I

M

O

R

VPHASE3&6 (3.5V)

VPHASE2&7 (2.5V)

FL

(

O

R

PT

VPHASE1&8 (1.5V)

VVALLEY (1.00V)

MN

O

A

C

R

CLK1

CLK2

CLK3

CLK4

CLK5

CLK6

CLK7

CLK8

S

E

S

L

U

P

K

C

O

L

C

I

E

S

A

H

P

Figure 4 – 8 Phase Oscillator Waveforms

PWM Operation

The PWM comparator is located in the Phase IC. Upon receiving a clock pulse, the PWM latch is set, the PWMRMP

voltage begins to increase, the low side driver is turned off, and the high side driver is then turned on. When the

PWMRMP voltage exceeds the Error Amp’s output voltage the PWM latch is reset. This turns off the high side

driver, turns on the low side driver, and activates the Ramp Discharge Clamp. The clamp quickly discharges the

PWMRMP capacitor to the VDAC voltage of the Control IC until the next clock pulse.

The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in

response to a load step decrease. Phases can overlap and go to 100% duty cycle in response to a load step

increase with turn-on gated by the clock pulses. An Error Amp output voltage greater than the common mode input

range of the PWM comparator results in 100% duty cycle regardless of the voltage of the PWM ramp. This

arrangement guarantees the Error Amp is always in control and can demand 0 to 100% duty cycle as required. It

also favors response to a load step decrease which is appropriate given the low output to input voltage ratio of most

systems. The inductor current will increase much more rapidly than decrease in response to load transients.

This control method is designed to provide “single cycle transient response” where the inductor current changes in

response to load transients within a single switching cycle maximizing the effectiveness of the power train and

minimizing the output capacitor requirements. An additional advantage is that differences in ground or input voltage

at the phases have no effect on operation since the PWM ramps are referenced to VDAC.

Page 8 of 8

12/17/04

IR3082

Body Braking^TM

In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in

response to a load step decrease is;

L ⋅ (I_MAX− I_MIN

)

T_SLEW

=

V_O

The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in

response to a load step decrease. The switch node voltage is then forced to decrease until conduction of the

synchronous rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout + V_BODY

_DIODE. The minimum time required to reduce the current in the inductor in response to a load transient decrease is

now;

L ⋅ (I_MAX− I_MIN

)

T_SLEW

=

V_O+V_BODYDIODE

Since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be

increased by 2X or more. This patent pending technique is referred to as “Body Braking” and is accomplished

through the “Body Braking Comparator” located in the Phase IC. If the Error Amp’s output voltage drops below 91%

of the VDAC voltage this comparator turns off the low side gate driver.

Figure 5 depicts PWM operating waveforms under various conditions.

PHASE IC

CLOCK

PULSE

EAIN

PWMRMP

VDAC

91% VDAC

GATEH

GATEL

STEADY-STATE

OPERATION

DUTY CYCLE INCREASE

DUE TO LOAD

INCREASE

DUTY CYCLE DECREASE

DUE TO VIN INCREASE

(FEED-FORWARD)

DUTY CYCLE DECREASE DUE TO LOAD

DECREASE (BODY BRAKING) OR FAULT

(VCC UV, OCP, VID=11111)

STEADY-STATE

OPERATION

Figure 5 – PWM Operating Waveforms

Lossless Average Inductor Current Sensing

Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor

and measuring the voltage across the capacitor. The equation of the sensing network is,

1

R_L+ sL

v_C(s) = v_L(s)

= i_L(s)

1+ sR_CSC_CS

Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time

constant of the inductor which is the inductance L over the inductor DCR (RL). If the two time constants match, the

voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense

resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of

inductor DC current, but affects the AC component of the inductor current.

Page 9 of 9

12/17/04

IR3082

The advantage of sensing the inductor current versus high side or low side sensing is that actual output current

being delivered to the load is obtained rather than peak or sampled information about the switch currents. The

output voltage can be positioned to meet a load line based on real time information. Except for a sense resistor in

series with the inductor, this is the only sense method that can support a single cycle transient response. Other

methods provide no information during either load increase (low side sensing) or load decrease (high side sensing).

An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer

from peak-to-average errors. These errors will show in many ways but one example is the effect of frequency

variation. If the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and

the output impedance of the converter will drop by about 10%. Variations in inductance, current sense amplifier

bandwidth, PWM prop delay, any added slope compensation, input voltage, and output voltage are all additional

sources of peak-to-average errors.

Current Sense Amplifier

A high speed differential current sense amplifier is located in the Phase IC, as shown in figure 6. Its gain decreases

with increasing temperature and is nominally 34 at 25ºC and 29 at 125ºC (-1470 ppm/ºC). This reduction of gain

tends to compensate the 3850 ppm/ºC increase in inductor DCR. Since in most designs the Phase IC junction is

hotter than the inductor these two effects tend to cancel such that no additional temperature compensation of the

load line is required.

The current sense amplifier can accept positive differential input up to 100mV and negative up to -20mV before

clipping. The output of the current sense amplifier is summed with the DAC voltage and sent to the Control IC and

other Phases through an on-chip 10KΩ resistor connected to the ISHARE pin. The ISHARE pins of all the phases

are tied together and the voltage on the share bus represents the total current through all the inductors and is used

by the Control IC for voltage positioning and current limit protection.

L

RL

Rcs

Ccs

Co

CSOUT

+

CS AMP

-

Figure 6 – Inductor Current Sensing and Current Sense Amplifier

Average Current Share Loop

Current sharing between phases of the converter is achieved by the average current share loop in each Phase IC.

The output of the current sense amplifier is compared with the share bus less a 20mV offset. If current in a phase is

smaller than the average current, the share adjust amplifier of the phase will activate a current source that reduces

the slope of its PWM ramp thereby increasing its duty cycle and output current. The crossover frequency of the

current share loop can be programmed with a capacitor at the SCOMP pin so that the share loop does not interact

with the output voltage loop.

Page 10 of 10

12/17/04

IR3082

IR3082 THEORY OF OPERATION

Block Diagram

The Block diagram of the IR3082 is shown in figure 7 and discussed in the following sections.

FAULT

LATCH

VCC

-

PWRGD

VDRP

+

VCC

COMPARATOR

UVLO

S

T

N

E

R

U

C

T

9.75V

9.0V

N

A

N

I

M

O

0.225V

-

DISCHARGE

COMPARATOR

R

E

V

O

T

E

S

-

R^D

+

ENABLE

COMPARATOR

+

-

ENABLE

-

+

-

+

DELAY

COMPARATOR

70mV

115mV

VDRP

AMP

F

O

=

D

I

V

-

OC

+

-

+

-

+

-

COMPARATOR

VCHG

3.9V

ON

1.270V

1.205V

IIN

OCSET

OC

+

-

DISCHG

CURRENT

40uA

700ns

BLANKING

SS/DEL

DISCHARGE

ON

DISABLE

IHICCUP

IDISCHG

6uA

-

+

1.3V

OFF

EAOUT

FB

+

-

ICHG

66uA

ERROR

AMP

+

-

SOFTSTART

CLAMP

SS/DEL

VID INPUT

COMPARATORS

IOCSET

IROSC

IFB

VID4

VID3

VID2

VID1

VID0

DIGITAL TO

ANALOG

CONVERTER

IROSC

(1 OF

5

LGND

VDAC

SHOWN)

+

-

+

"FAST"

VDAC

+

ISOURCE

ISINK

-

+

-

1.24V

VDAC

BUFFER

AMP

-

VOSNS-

50%

DUTY

CYCLE

RAMP GENERATOR

VBIAS

RMPOUT

IROSC

VBIAS

5.0V

1.0V

VBIAS

REGULATOR

+

-

+

-

7.0V

ROSC

BUFFER

AMP

CURRENT

SOURCE

+

GENERATOR

-

ROSC

Figure 7 – IR3082 Block Diagram

VID Control

A 5-bit VID voltage compatible with AMD’s Opteron/Athlon64, as shown in Table 1, is available at the VDAC pin.

The VID pins require an external bias voltage and should not be floated. The VID input comparators, with 1.2V

reference, monitor the VID pins and control the 6 bit Digital-to-Analog Converter (DAC) whose output is sent to the

VDAC buffer amplifier. The output of the buffer amp is the VDAC pin. The VDAC voltage is trimmed to compensate

for the input offsets of the Error Amp to provide 1% system set-point accuracy and is pre-positioned 50mV higher

than Vout listed in Table1 for load positioning. The actual VDAC voltage does not determine the system accuracy

and has a wider tolerance.

The IR3082 can accept changes in the VID code while operating and vary the DAC voltage accordingly. The

sink/source capability of the VDAC buffer amp is programmed by the same external resistor that sets the oscillator

frequency. The slew rate of the voltage at the VDAC pin can be adjusted by an external capacitor between VDAC

pin and the VOSNS- pin. A resistor connected in series with this capacitor is required to compensate the VDAC

buffer amplifier. Digital VID transitions result in a smooth analog transition of the VDAC voltage and converter

output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output voltage.

Page 11 of 11

12/17/04

IR3082

VID4 VID3 VID2 VID1 VID0 Vout (V)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.550

1.525

1.500

1.475

1.450

1.425

1.400

1.375

1.350

1.325

1.300

1.275

1.250

1.225

1.200

1.175

1.150

1.125

1.100

1.075

1.050

1.025

1.000

0.975

0.950

0.925

0.900

0.875

0.850

0.825

0.800

OFF⁴

Note: 4 Output disabled (Fault mode)

Table 1 – VID Table

Adaptive Voltage Positioning

Adaptive voltage positioning is needed to reduce the output voltage deviations during load transients and the power

dissipation of the load when it is drawing maximum current. The circuitry related to voltage positioning is shown in

Figure 8. Resistor RFB is connected between the Error Amp’s inverting input pin FB and the converter’s output

voltage. An internal current source whose value is programmed by the same external resistor that programs the

oscillator frequency pumps current into the FB pin. The error amp forces the converter’s output voltage lower to

maintain a balance at its inputs. RFB is selected to program the desired amount of fixed offset voltage below the

DAC voltage.

Page 12 of 12

12/17/04

IR3082

The voltage at the VDRP pin is a buffered version of the share bus and represents the sum of the DAC voltage and

the average inductor current of all the phases. The VDRP pin is connected to the FB pin through the resistor RVDRP.

Since the Error Amp will force the loop to maintain FB to be equal to the VDAC reference voltage, current will flow

into the FB pin equal to (VDRP-VDAC) / RVDRP. When the load current increases, the adaptive positioning voltage

increases accordingly. More current flows through the feedback resistor RFB, and makes the output voltage lower

proportional to the load current. The positioning voltage can be programmed by the resistor RVDRP so that the droop

impedance produces the desired converter output impedance. The offset and slope of the converter output

impedance are referenced to and therefore independent of the VDAC voltage.

Current Sense

Amplifier

Control IC

Phase IC

Error

Amplifier

VDAC

ISHARE

VDAC

CS+

CS-

EA

FB

+

-

+

-

10k

Vo

Rfb

Ifb

.

Rvdrp

VDRP

Droop

Amplifier

Current Sense

Amplifier

Phase IC

-

+

IIN

ISHARE

VDAC

CS+

CS-

+

-

10k

VDAC

Figure 8 - Adaptive voltage positioning

Inductor DCR Temperature Correction

If the thermal compensation of the inductor DCR provided by the temperature dependent gain of the current sense

amplifier is not adequate, a negative temperature coefficient (NTC) thermistor can be used for additional correction.

The thermistor should be placed close to the inductor and connected in parallel with the feedback resistor as shown

in Figure 9. The resistor in series with the thermistor is used to reduce the nonlinearity of the thermistor.

Control IC

Error

Amplifier

VDAC

EA

FB

+

-

Rfb

Vo

If b

Rfb

Rt

Rvdrp

VDRP

Droop

Amplifier

-

+

IIN

Figure 9 - Temperature compensation of inductor DCR

Page 13 of 13

12/17/04

IR3082

Remote Voltage Sensing

To compensate for impedance in the ground plane, the VOSNS- pin is used for remote sensing and connects

directly to the load. The VDAC voltage is referenced to VOSNS- to avoid additional error terms or delay related to a

separate differential amplifier. The capacitor connecting the VDAC and VOSNS- pins ensure that high speed

transients are fed directly into the error amp without delay.

Soft Start, Over-Current Fault Delay, and Hiccup Mode

The IR3082 has a programmable soft-start function to limit the surge current during the converter start-up. A

capacitor connected between the SS/DEL and LGND pins controls soft start as well as over-current protection delay

and hiccup mode timing. A charge current of 66uA and discharge current of 6uA control the up slope and down

slope of the voltage at the SS/DEL pin respectively. Soft start-up waveforms are shown in Figure 10.

Figure 11 depicts the various operating modes as controlled by the SS/DEL function. If there is no fault, the SS/DEL

pin will begin to be charged. The error amplifier output is clamped low until SS/DEL reaches 1.3V. The error

amplifier will then regulate the converter’s output voltage to match the SS/DEL voltage less the 1.3V offset until it

reaches the level determined by the VID inputs. The SS/DEL voltage continues to increase until it rises above 3.83V

and allows the PWRGD signal to be asserted. SS/DEL finally settles at 3.9V, indicating the end of the soft start.

Under Voltage Lock Out and VID=11111 faults as well as a low signal on the ENABLE input immediately sets the

fault latch causing SS/DEL to begin to discharge. The SS/DEL capacitor will continue to discharge down to 0.2V. If

the fault has cleared the fault latch will be reset by the discharge comparator allowing a normal soft start to occur.

A delay is included if an over-current condition occurs after a successful soft start sequence. This is required since

over-current conditions can occur as part of normal operation due to load transients or VID transitions. If an over-

current fault occurs during normal operation it will initiate the discharge of the capacitor at SS/DEL but will not set

the fault latch immediately. If the over-current condition persists long enough for the SS/DEL capacitor to discharge

below the 115mV offset of the delay comparator, the Fault latch will be set pulling the error amp’s output low

inhibiting switching in the phase ICs and de-asserting the PWRGD signal. The delay can be reduced by adding a

resistor in series with the delay capacitor. The delay comparator’s offset voltage is reduced by the drop in the

resistor caused by the discharge current. To prevent the charge current from creating an offset exceeding the

SS/DEL to FB input offset voltage the value of the resistor should be 10KΩ or less to avoid interference with the soft

start function.

The SS/DEL capacitor will continue to discharge until it reaches 0.2V and the fault latch is reset allowing a normal

soft start to occur. If an over-current condition is again encountered during the soft start cycle the fault latch will be

set without any delay and hiccup mode will begin. During hiccup mode the 11 to 1 charge to discharge ratio results

in a 9% hiccup mode duty cycle regardless of at what point the over-current condition occurs.

If SS/DEL pin is pulled below 0.9V, the converter can be disabled.

Under Voltage Lockout (UVLO)

The UVLO function monitors the IR3082’s VCC supply pin and ensures that IR3082 has a high enough voltage to

power the internal circuit. The IR3082’s UVLO is set higher than the minimum operating voltage of compatible

Phase ICs thus providing UVLO protection for them as well. During power-up the fault latch is reset when VCC

exceeds 9.75V and there is no other fault. If the VCC voltage drops below 9.0V the fault latch will be set. For

converters using a separate 5V supply for gate driver bias an external UVLO circuit can be added to prevent

operation until adequate voltage is present. A diode connected between the 5V supply and the SS/DEL pin provides

a simple 5V UVLO function.

Page 14 of 14

12/17/04

IR3082

Over Current Protection (OCP)

The current limit threshold is set by a resistor connected between the OCSET and VDAC pins. If the IIN pin voltage,

which is proportional to the average current plus DAC voltage, exceeds the OCSET voltage, the over-current

protection is triggered.

VID = 11111 Fault

VID code of 11111 will set the fault latch and disable the error amplifier. An 800ns delay is provided to prevent a

fault condition from occurring during Dynamic VID changes.

Power Good Output

The PWRGD pin is an open-collector output and should be pulled up to a voltage source through a resistor. During

soft start, the PWRGD remains low until the output voltage is in regulation and SS/DEL is above 3.83V. The

PWRGD pin becomes low if the fault latch is set. A high level at the PWRGD pin indicates that the converter is in

operation and has no fault, but does not ensure the output voltage is within the specification. Output voltage

regulation within the design limits can logically be assured however, assuming no component failure in the system.

Load Current Indicator Output

The IIN pin voltage represents the average current of the converter plus the DAC voltage. The load current can be

retrieved by subtracting the VDAC voltage from the IIN voltage.

System Reference Voltage (VBIAS)

The IR3082 supplies a 7.0V/5mA precision reference voltage from the VBIAS pin. The oscillator ramp trip points are

based on the VBIAS voltage so it should be used to program the Phase ICs phase delay to minimize phase errors.

Enable Input

Pulling the ENABLE pin below 1.27V sets the Fault Latch.

Page 15 of 15

12/17/04

IR3082

9.0V

UVLO

VCC

(12V)

1.27V

ENABLE

(VTT)

3.83V

1.3V

SS/DEL

VOUT

PWRGD

START

(ENABLE ENDS

FAULT MODE)

START DELAY

1.9ms

PWRGD

DELAY

2.0ms

NORMAL

OPERATION

POWER-DOWN

(VCC UVL

INITIATES

FAULT MODE)

SOFT START TIME

1.95ms

Figure 10 – Start-up Waveforms

9.0V

UVLO

VCC

(12V)

ENABLE

SS/DEL

3.785V

3.83V

1.3V

VOUT

PWRGD

OCP THRESHOLD

IOUT

START-UP

NORMAL OPERATION

OCP

DELAY

HICCUP OVER-CURRENT

PROTECTION

RE-START

AFTER OCP

CLEARS

POWER-DOWN

(ENABLE GATES

FAULT MODE)

(VOUT CHANGES DUE TO

LOAD AND VID CHANGES)

(VCC GATES

FAULT MODE)

Figure 11 – Operating Waveforms

Page 16 of 16

12/17/04

IR3082

APPLICATIONS INFORMATION

POWERGOOD

VRHOT

PHASE FAULT

12V

RCS-

CCS-

RVCC

QGATE

10 ohm

CCS+

RBIASIN 20k

DBST

RCS+

0

9

8

7

6

1

RGATE

DGATE

2

1

CVCC

0.1uF

E

S

A

-

+

T

L

N

I

N

I

N

I

N

I

CIN

S

C

A

D

F

S

H

P

R

S

A

I

C

CBST

VOUT SENSE+

VOUT+

H

P

B

1

15

14

13

12

11

RMPIN+

RMPIN-

VCCH

GATEH

PGND

GATEL

VCCL

2

3

4

5

IR3086

PHASE

IC

L

HOTSET

VRHOT

ISHARE

DISTRIBUTION

IMPEDANCE

COUT

L

E

D

/

S

R

P

CFB

ENABLE

VOUT-

2

1

M

P

0.1uF

R

M

O

C

S

E

S

A

D

N

I

M

CVCCL

C

V

N

L

A

E

W

P

G

L

E

H

P

R

D

RFB1

RFB

/

RVCC

S

C

6

7

8

9

0

1

VOUT SENSE-

P

RPWMRMP

M

R

3

1

E

S

A

M

W

P

0

2

9

8

7

6

1

CSCOMP

1

H

P

R

C

CVCC

L

E

L

T

U

O

P

D

G

R

D

N

E

B

A

D

/

G

L

1

2

3

4

5

15

14

13

12

11

S

VID0

VID1

VID2

VID3

VID4

N

E

W

VID0

VID1

VID2

VID3

VID4

VCC

VBIAS

EAOUT

FB

S

M

CCP

RCS-

P

RCP

R

IR3082

CONTROL

IC

CCS+

CCP1

CCS-

RBIASIN 20k

VDRP

DBST

RCS+

-

0

9

1

8

1

7

1

6

1

S

N

S

O

V

T

RDRP

2

C

S

O

R

E

S

C

O

1

2

C

A

D

V

E

S

A

-

N

+

T

L

I

N

I

N

I

N

I

CBST

N

I

S

C

A

D

F

S

H

P

R

S

A

I

C

6

7

8

9

0

1

C

H

P

B

1

15

RMPIN+

RMPIN-

VCCH

ROCSET

2

3

4

5

14

IR3086

PHASE

IC

GATEH

L

13

HOTSET

VRHOT

ISHARE

PGND

12

GATEL

ROSC RVDAC

CVDAC

11

VCCL

P

2

M

P

R

M

O

C

S

E

S

A

D

N

I

M

CVCCL

C

V

N

A

E

W

P

G

L

H

P

R

RVCC

6

7

8

9

0

1

P

RPWMRMP

M

R

3

2

E

S

A

M

W

P

CSCOMP

H

P

R

C

CVCC

RCS-

CCS+

CCS-

RBIASIN 20k

DBST

RCS+

0

2

9

1

8

7

1

6

1

3

E

S

A

-

+

T

L

N

I

N

I

N

I

CBST

N

I

S

C

A

D

F

S

H

P

R

S

A

I

C

H

P

B

1

15

RMPIN+

RMPIN-

VCCH

2

3

4

5

14

IR3086

PHASE

IC

GATEH

L

13

HOTSET

VRHOT

ISHARE

PGND

12

GATEL

11

VCCL

P

2

3

M

P

R

M

O

C

S

E

S

A

D

N

I

M

CVCCL

C

V

N

A

E

W

P

G

L

H

P

R

RVCC

6

7

8

9

0

1

P

RPWMRMP

M

R

3

E

S

A

M

W

P

CSCOMP

H

P

R

C

CVCC

RCS-

CCS+

CCS-

RBIASIN 20k

DBST

RCS+

0

9

1

8

1

7

1

6

1

2

1

4

E

S

A

-

+

T

L

N

I

N

I

N

I

CBST

N

I

S

C

A

D

F

S

H

P

R

S

A

I

C

H

P

B

1

15

RMPIN+

RMPIN-

VCCH

2

3

4

5

14

IR3086

HOTSET PHASE

GATEH

L

13

PGND

12

IC

VRHOT

GATEL

11

ISHARE

VCCL

P

2

4

M

R

P

M

O

C

S

E

S

A

D

N

I

M

CVCCL

C

V

A

E

W

P

G

L

H

P

R

RVCC

6

7

8

9

0

1

P

RPWMRMP

M

R

3

4

E

S

A

M

W

P

CSCOMP

H

P

R

C

CVCC

RCS-

CCS+

CCS-

RBIASIN 20k

DBST

RCS+

0

2

9

1

8

7

1

6

1

5

E

S

A

-

+

T

L

N

I

N

I

N

I

CBST

N

I

S

C

A

D

F

S

H

P

R

S

A

I

C

H

P

B

1

15

RMPIN+

RMPIN-

VCCH

2

3

4

5

14

IR3086

PHASE

IC

GATEH

L

13

HOTSET

VRHOT

ISHARE

PGND

12

GATEL

11

VCCL

P

2

5

M

P

R

M

O

C

S

E

S

A

D

N

I

M

CVCCL

C

V

N

A

E

W

P

G

L

H

P

R

RVCC

6

7

8

9

0

1

P

RPWMRMP

M

R

3

5

E

S

A

M

W

P

CSCOMP

H

P

R

C

CVCC

Figure 12 – IR3082/3086 5 Phase Converter for Opteron Processor

Page 17 of 17

12/17/04

IR3082

PERFORMANCE CHARACTERISTICS

Figure 13 - Oscillator Frequency vs. ROSC

Figure 14 IFB, IOCSET vs. ROSC

1050

950

850

750

650

550

450

350

250

150

120

110

100

90

80

70

60

50

40

30

20

10

20

30

40

50

60

70

80

90

10

20

30

40

50

60

70

80

90

ROSC (KOhm)

Figure 16 - Bias Current Accuracy vs. ROSC

Figure 15 - VDAC Source and Sink Currents vs. ROSC

5

4.5

4

FB, OCSET Bias Current

250

230

210

190

170

150

130

110

90

70

50

30

10

Isource

Isink

VDAC Sink Current

VDAC Source Current

3.5

3

2.5

2

1.5

1

0.5

0

10

20

30

40

50

60

70

80

90

10

20

30

40

50

60

70

80

90

ROSC (KOhm)

Figure 17 – Error Amplifier Frequency Response

200

150

100

50

Gain

Phase

0

-50

10

100

1K

10K

100K

1M

10M

100M

Page 18 of 18

12/17/04

IR3082

DESIGN PROCEDURES – IR3082 AND IR3086 CHIPSET

IR3082 EXTERNAL COMPONENTS

Oscillator Resistor Rosc

The oscillator of IR3082 generates a triangle waveform to synchronize the phase ICs, and the switching frequency

of the each phase converter equals the oscillator frequency, which is set by the external resistor ROSC according to

the curve in Figure 13.

Soft Start Capacitor CSS/DEL and Resistor RSS/DEL

Because the capacitor CSS/DEL programs three different time parameters, i.e. soft start time, over current latch

delay time, and the frequency of hiccup mode, they should be considered together while choosing CSS/DEL.

The SS/DEL pin voltage controls the slew rate of the converter output voltage, as shown in Figure 10. After the

ENABLE pin voltage rises above 1.23V, there is a soft-start delay time tSSDEL, after which the error amplifier output

is released to allow the soft start. The soft start time tSS represents the time during which the output voltage rises

from zero to Vo. tSS can be programmed by an external capacitor, which is determined by Equation (1).

I

_CHG⋅t_SS66⋅10⁻⁶⋅t_SS

(1)

C_{SS / DEL}

=

V_O

Once CSS/DEL is chosen, the soft start delay time tSSDEL, the over-current fault latch delay time tOCDEL, and the

delay time tVccPG from output voltage (Vo) in regulation to Power Good are fixed and shown in Equations (2), (3),

(4) and (5) respectively.

C

_{SS / DEL}⋅1.3

C

_{SS / DEL}⋅1.3

66⋅10⁻⁶

(2)

t_SSDEL

=

I_CHG

C_{SS / DEL}⋅0.09

C

_{SS / DEL}⋅0.09

6⋅10⁻⁶

(3)

(4)

t_OCDEL

=

I_DISCHG

C

_{SS / DEL}⋅(3.73−V_O−1.3)

C

_{SS / DEL}⋅(3.73−V_O−1.3)

66⋅10⁻⁶

t_VccPG

=

I_CHG

The hiccup mode duty cycle of over current protection is determined by the charge current ICHG and discharge

current IDISCHG of CSS/DEL and is fixed at 9%. However, the hiccup frequency is determined by the load current and

over-current set value.

If faster over-current protection is required, a resistor in series with the soft start capacitor CSS/DEL can be used to

reduce the over-current fault latch delay time tOCDEL, and the resistor RSS/DEL is determined by Equation (5).

Equation (1) for soft start capacitor CSS/DEL and Equation (4) for power good delay time tVccPG are unchanged,

while the equation for soft start delay time CSS/DEL (Equation 2) is changed to Equation (6).

t_OCDEL⋅ I_DISCHG

t_OCDEL⋅ 6⋅10⁻⁶

0.09 −

C_{SS / DEL}

6 ⋅10⁻⁶

(5)

R_SSDEL

=

I_DISCHG

Page 19 of 19

12/17/04

IR3082

C

_{SS / DEL}⋅(1.3− R_{SS / DEL}⋅ I_CHG

)

C

_{SS / DEL}⋅(1.3− R_{SS / DEL}⋅66⋅10⁻⁶)

66⋅10⁻⁶

(6)

t_SSDEL

=

I_CHG

VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC

The slew rate of VDAC down-slope SRDOWN can be programmed by the external capacitor CVDAC as defined in

Equation (7), where ISINK is the sink current of VDAC pin as shown in Figure 15. The resistor RVDAC is used to

compensate VDAC circuit and is determined by Equation (8). The slew rate of VDAC up-slope SRUP is proportional

to that of VDAC down-slope and is given by Equation (9), where ISOURCE is the source current of VDAC pin as

shown in Figure15.

I_SINK

(7)

(8)

(9)

C_VDAC

=

SR_DOWN

3.2⋅10⁻¹⁵

R_VDAC= 0.5 +

2

C_VDAC

I_SOURCE

SR_UP

=

C_VDAC

Over Current Setting Resistor ROCSET

The inductor DC resistance is utilized to sense the inductor current. The copper wire of inductor has a constant

temperature coefficient of 3850 PPM, and therefore the maximum inductor DCR can be calculated from Equation

(10), where RL_MAX and RL_ROOM are the inductor DCR at maximum temperature TL_MAX and room temperature

T_ROOM respectively.

R_{L _ MAX}= R_{L _ ROOM}⋅[1+ 3850 ⋅10⁻⁶⋅(T_{L _ MAX}−T_ROOM)]

(10)

The current sense amplifier gain of IR3086 decreases with temperature at the rate of 1470 PPM, which

compensates part of the inductor DCR increase. The phase IC die temperature is only a couple of degrees Celsius

higher than the PCB temperature due to the low thermal impedance of MLPQ package. The minimum current sense

amplifier gain at the maximum phase IC temperature TIC_MAX is calculated from Equation (11).

G_{CS _ MIN}= G_{CS _ ROOM}⋅[1−1470⋅10⁻⁶⋅(T_{IC _ MAX}−T_ROOM)]

(11)

The total input offset voltage (VCS_TOFST) of current sense amplifier in phase ICs is the sum of input offset

(VCS_OFST) of the amplifier itself and that created by the amplifier input bias currents flowing through the current

sense resistors RCS+ and RCS-.

V_{CS _ TOFST}= V_{CS _ OFST}+ I_{CSIN +}⋅ R_{CS +}− I_{CSIN −}⋅ R_{CS −}

(12)

The over current limit is set by the external resistor ROCSET as defined in Equation (13), where ILIMIT is the required

over current limit. IOCSET, the bias current of OCSET pin, changes with switching frequency setting resistor ROSC

and is determined by the curve in Figure 14. KP is the ratio of inductor peak current over average current in each

phase and is calculated from Equation (14).

I_LIMIT

R_OCSET= [

⋅ R_{L _ MAX}⋅(1+ K_P) +V_{CS _ TOFST}]⋅G_{CS _ MIN}/ I_OCSET

(13)

(14)

n

(V_I−V_O)⋅V_O/(L⋅V_I⋅ f_SW⋅2)

I_O/ n

K_P

=

Page 20 of 20

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No Load Output Voltage Setting Resistor RFB and Adaptive Voltage Positioning Resistor RDRP

A resistor between FB pin and the converter output is used to create output voltage offset VO_NLOFST, which is the

difference between VDAC voltage and output voltage at no load condition. Adaptive voltage positioning lowers the

converter voltage by Ro times Io, where Ro is the required output impedance of the converter.

RFB is not only determined by IFB, the current flowing out of the FB pin as shown in Figure 14, but also affected by

the total input offset voltage of current sense amplifiers. RFB and RDRP are determined by (15) and (16)

respectively.

R_{L _ MAX}⋅V_{O _ NLOFST}−V_{CS _TOFST}⋅ n ⋅ R_O

(15)

(16)

R_FB

=

I

_FB⋅ R_{L _ MAX}

R_FB⋅ R_{L _ MAX}⋅G_{CS _ MIN}

R_DRP

=

n ⋅ R_O

IR3086 EXTERNAL COMPONENTS

PWM Ramp Resistor RPWMRMP and Capacitor CPWMRMP

PWM ramp is generated by connecting the resistor RPWMRMP between a voltage source and PWMRMP pin as well

as the capacitor CPWMRMP between PWMRMP and LGND. Choose the desired PWM ramp magnitude VRAMP and

the capacitor CPWMRMP in the range of 100pF and 470pF, and then calculate the resistor RPWMRMP from Equation

(17). To achieve feed-forward voltage mode control, the resistor RRAMP should be connected to the input of the

converter.

V_O

(17)

R_PWMRMP

=

V_IN⋅ f_SW⋅C_PWMRMP⋅[ln(V_IN−V_DAC) − ln(V_IN−V_DAC−V_PWMRMP)]

Inductor Current Sensing Capacitor CCS+ and Resistors RCS+ and RCS-

The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS+ and capacitor

CCS+ in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage

across the capacitor CCS+ represents the inductor current. If the two time constants are not the same, the AC

component of the capacitor voltage is different from that of the real inductor current. The time constant mismatch

does not affect the average current sharing among the multiple phases, but affect the current signal ISHARE as well

as the output voltage during the load current transient if adaptive voltage positioning is adopted.

Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS+ and calculate RCS+ as

follows.

L R_L

(18)

R_{CS +}

=

C_{CS +}

The bias current flowing out of the non-inverting input of the current sense amplifier creates a voltage drop across

RCS+, which is equivalent to an input offset voltage of the current sense amplifier. The offset affects the accuracy of

converter current signal ISHARE as well as the accuracy of the converter output voltage if adaptive voltage

positioning is adopted. To reduce the offset voltage, a resistor RCS- should be added between the amplifier inverting

input and the converter output. The resistor RCS- is determined by the ratio of the bias current from the non-inverting

input and the bias current from the inverting input.

I_{CSIN +}

(19)

R_{CS −}

=

⋅ R_{CS +}

I_{CSIN −}

Page 21 of 21

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IR3082

If RCS- is not used, RCS+ should be chosen so that the offset voltage is small enough. Usually RCS+ should be less

than 2 kΩ and therefore a larger CCS+ value is needed.

Over Temperature Setting Resistors R^HOTSET1and RHOTSET2

The threshold voltage of VRHOT comparator is proportional to the die temperature TJ (ºC) of phase IC. Determine

the relationship between the die temperature of phase IC and the temperature of the power converter according to

the power loss, PCB layout and airflow etc, and then calculate HOTSET threshold voltage corresponding to the

allowed maximum temperature from Equation (20).

V_HOTSET= 4.73⋅10⁻³⋅T_J+1.241

(20)

There are two ways to set the over temperature threshold, central setting and local setting. In the central setting,

only one resistor divider is used, and the setting voltage is connected to HOTSET pins of all the phase ICs. To

reduce the influence of noise on the accuracy of over temperature setting, a 0.1uF capacitor should be placed next

to HOTSET pin of each phase IC. In the local setting, a resistor divider per phase is needed, and the setting voltage

is connected to HOTSET pin of each phase. The 0.1uF decoupling capacitor is not necessary. Use VBIAS as the

reference voltage. If RHOTSET1 is pre-selected, RHOTSET2 can be calculated as follows.

R

_HOTSET1⋅V_HOTSET

(21)

R_{HOTSET 2}

=

V_BIAS−V_HOTSET

Phase Delay Timing Resistors R^PHASE1and RPHASE2

The phase delay of the interleaved multiphase converter is programmed by the resistor divider connected at

RMPIN+ or RMPIN- depending on which slope of the oscillator ramp is used for the phase delay programming of

phase IC, as shown in Figure 3.

If the upslope is used, RMPIN+ pin of the phase IC should be connected to RMPOUT pin of the control IC and

RMPIN- pin should be connected to the resistor divider. When RMPOUT voltage is above the trip voltage at

RMPIN- pin, the PWM latch is set. GATEL becomes low, and GATEH becomes high after the non-overlap time.

If down slope is used, RMPIN- pin of the phase IC should be connected to RMPOUT pin of the control IC and

RMPIN+ pin should be connected to the resistor divider. When RMPOUT voltage is below the trip voltage at

RMPIN- pin, the PWM latch is set. GATEL becomes low, and GATEH becomes high after the non-overlap time.

Use VBIAS voltage as the reference for the resistor divider since the oscillator ramp magnitude from control IC

tracks VBIAS voltage. Try to avoid both edges of the oscillator ramp for better noise immunity. Determine the ratio

of the programming resistors, RAPHASEx, corresponding to the desired switching frequencies and phase numbers. If

the resistor RPHASEx1 is pre-selected, the resistor RPHASEx2 is determined as:

RA_PHASEx⋅ R_PHASEx1

(22)

R_PHASEx2

=

1− RA_PHASEx

Combined Over Temperature and Phase Delay Setting Resistors RPHASE1, RPHASE2 and RPHASE3

The over temperature setting resistor divider can be combined with the phase delay resistor divider to save one

resistor per phase.

Calculate the HOTSET threshold voltage VHOTSET corresponding to the allowed maximum temperature from

Equation (20). If the over temperature setting voltage is lower than the phase delay setting voltage,

VBIAS*RAPHASEx, connect RMPIN+ or RMPIN- pin between RPHASEx1 and RPHASEx2 and connect HOTSET pin

between RPHASEx2 and RPHASEx3 respectively. Pre-select RPHASEx1, then calculate RPHASEx2 and RPHASEx3,

Page 22 of 22

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IR3082

(RA_PHASEx⋅V_BIAS−V_HOTSET) ⋅ R_PHASEx1

(23)

(24)

R_PHASEx2

=

V_BIAS⋅(1− RA_PHASEx

)

V_HOTSET⋅ R_PHASEx1

V_BIAS⋅ (1− RA_PHASEx

R_PHASEx3

)

If the over temperature setting voltage is higher than the phase delay setting voltage, VBIAS times RAPHASEx,

connect HOTSET pin between RPHASEx1 and RPHASEx2 and connect RMPIN+ or RMPIN- between RPHASEx2 and

RPHASEx3 respectively. Pre-select RPHASEx1,

(V_HOTSET− RA_PHASEx⋅V_BIAS) ⋅ R_PHASEx1

(25)

R_PHASEx2

=

V_BIAS−V_HOTSET

RA_PHASEx⋅V_BIAS⋅ R_PHASEx1

V_BIAS−V_HOTSET

(26)

R_PHASEx3

=

Bootstrap Capacitor CBST

Depending on the duty cycle and gate drive current of the phase IC, a 0.1uF to 1uF capacitor is needed for the

bootstrap circuit.

Decoupling Capacitors for Phase IC

0.1uF-1uF decoupling capacitors are required at VCC and VCCL pins of phase ICs.

VOLTAGE LOOP COMPENSATION

The adaptive voltage positioning (AVP is usually used in the computer applications to improve the transient

response and reduce the power loss at heavy load. Like current mode control, the adaptive voltage positioning loop

introduces extra zero to the voltage loop and splits the double poles of the power stage, which make the voltage

loop compensation much easier.

Resistors RFB and RDRP are chosen according to Equations (15) and (16), and the selection of compensation types

depends on the capacitors used. For the applications using Electrolytic, Polymer or AL-Polymer capacitors, type II

compensation shown in Figure 18 (a) is usually enough. While for the applications with only ceramic capacitors,

type III compensation shown in Figure 18 (b) is preferred.

CCP1

RFB1

CFB

RCP

CCP

RCP

CCP

VO+

F B

VO+

F B

RFB

-

+

RFB

-

+

E AOUT

VDR P

VDAC

VDRP

VDAC

RDRP

(a) Type II compensation

(b) Type III compensation

Figure 18. Voltage loop compensation network

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IR3082

Type II Compensation

Determine the compensation at no load, the worst case condition. Choose the crossover frequency fc between 1/10

and 1/5 of the switching frequency per phase. Assume the time constant of the resistor and capacitor across the

output inductors matches that of the inductor, RCP and CCP can be determined by equations (27) and (28).

(2π ⋅ f_C)²⋅ L_E⋅C_E⋅ R_FB⋅V_PWMRMP

(27)

R_CP

=

1+ (2π ⋅ f_C⋅C_E⋅ R_CE)²⋅V_o

10⋅ L_E⋅C_E

R_CP

(28)

C_CP

=

where LE and RCE are the equivalent output inductance and ESR of output capacitors respectively. CCP1 is optional

and may be needed in some applications to reduce the jitter caused by the high frequency noise. A ceramic

capacitor between 10pF and 220pF is usually enough.

Type III Compensation

Determine the compensation at no load, the worst case condition. Choose the crossover frequency fc between 1/10

and 1/5 of the switching frequency per phase. Assume the time constant of the resistor and capacitor across the

output inductors matches that of the inductor, RCP and CCP can be determined by equations (29) and (30), where CE

is equivalent output capacitance.

(2π ⋅ f_C)²⋅ L_E⋅C_E⋅V_PWMRMP

(29)

R_CP

=

V_o

10⋅ L_E⋅C_E

(30)

C_CP

=

R_CP

Choose resistor RFB1 according to Equation (31), and determine CFB from Equations (32).

1

2

3

R_FB1

=

R_FB

to

R_FB1

=

R_FB

(31)

1

C_FB

=

(32)

4π ⋅ f_C1⋅ R_FB1

CCP1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. A

ceramic capacitor between 10pF and 220pF is usually enough.

CURRENT SHARE LOOP COMPENSATION

The crossover frequency of the current share loop should be at least one decade lower than that of the voltage loop

in order to eliminate the interaction between the two loops. A capacitor from SCOMP to LGND is usually enough for

most of the applications. Choose the crossover frequency of current share loop (fCI) based on the crossover

frequency of voltage loop (fC), and determine the CSCOMP,

0.65⋅ R_PWMRMP⋅V_I⋅ I_O⋅G_{CS _ ROOM}⋅ R_LE⋅[1+ 2π ⋅ f_CI⋅C_E⋅(V_OI_O)]⋅ F_MI

(33)

C_SCOMP

=

V_O⋅2π ⋅ f_CI⋅1.05⋅10⁶

Where FMI is the PWM gain in the current share loop,

R

_PWMRMP⋅C_PWMRMP⋅ f_SW⋅V_PWMRMP

(34)

C_SCOMP

=

(V_O−V_PWMRMP−V_DAC)⋅(V_I−V_DAC

)

Page 24 of 24

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IR3082

DESIGN EXAMPLE ― 5-PHASE OPTERON CONVERTER

SPECIFICATIONS

Input Voltage: VI=12 V

DAC Voltage: VDAC=1.3 V

No Load Output Voltage Offset: VO_NLOFST=15mV

Maximum Output Current: IOMAX=100 ADC

Output Impedance: RO=0.75 mΩ

Soft Start Time: tSS = 2 mS

Dynamic VID Down-Slope Slew Rate: SRDOWN=2.5mV/uS

Over Temperature Threshold: TPCB=115 ºC

POWER STAGE

Phase Number: n=5

Switching Frequency: fSW=600 kHz

Output Inductors: L=220 nH, RL=0.42 mΩ

Output Capacitors: C=47uF, RC= 2mΩ, Number Cn=32

IR3082 EXTERNAL COMPONENTS

Oscillator Resistor Rosc

Once the switching frequency is chosen, ROSC can be determined from the curve in Figure 13. For switching

frequency of 600kHz per phase, choose ROSC=18.2kΩ

Soft Start Capacitor CSS/DEL

Calculate the soft start capacitor from the required soft start time.

66⋅10⁻⁶⋅2⋅10⁻³

I_CHG⋅t_SS

, choose C

= 0.1uF

C_{SS / DEL}

=

= 0.0988uF

SS / DEL

1.3+ (50 −15)⋅10⁻³

V_O

The soft start delay time is

C

_{SS / DEL}⋅0.09

C

_{SS / DEL}⋅0.09

6⋅10⁻⁶

t_OCDEL

=

=1.5ms

I_DISCHG

0.1⋅10⁻⁶⋅(3.73−1.335−1.3)

66⋅10⁻⁶

C

_{SS / DEL}⋅(3.73−V_O−1.3)

t_VccPG

=

=1.64ms

I_CHG

VDAC Slew Rate Programming Capacitor CVDAC and Resistor RVDAC

From Figure 15, the sink current of VDAC pin corresponding to 600kHz (ROSC=18.2kΩ) is 125uA. Calculate the

VDAC down-slope slew-rate programming capacitor from the required down-slope slew rate.

I_SINK

125⋅10⁻⁶

SR_DOWN2.5⋅10⁻³/10⁻⁶

C_VDAC

=

= 50nF , Choose CVDAC=47nF

Calculate the programming resistor.

3.2⋅10⁻¹⁵

(47⋅10⁻⁹)²

R_VDAC= 0.5 +

= 0.5 +

= 2Ω

2

C_VDAC

Page 25 of 25

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IR3082

From Figure 15, the source current of VDAC pin is 170uA. The VDAC up-slope slew rate is

170⋅10⁻⁶

47⋅10⁻⁹

I_SOURCE

SR_UP

=

= 3.6mV / uS

C_VDAC

Over Current Setting Resistor ROCSET

The room temperature is 25ºC and the target PCB temperature is 100 ºC. The phase IC die temperature is about 1

ºC higher than that of phase IC, and the inductor temperature is close to PCB temperature.

Calculate Inductor DC resistance at 100 ºC,

R_{L _ MAX}= R_{L _ ROOM}⋅[1+3850⋅10⁻⁶⋅(T_{L _ MAX}−T_ROOM)] = 0.42⋅10⁻³⋅[1+3850⋅10⁻⁶⋅(100− 25)] = 0.54mΩ

The current sense amplifier gain is 34 at 25ºC, and its gain at 101ºC is calculated as,

G_{CS _ MIN}= G_{CS _ ROOM}⋅[1−1470 ⋅10⁻⁶⋅(T_{IC _ MAX}−T_ROOM)] = 34⋅[1−1470 ⋅10⁻⁶⋅(101− 25)] = 30.2

Set the over current limit at 115A. From Figure 14, the bias current of OCSET pin (IOCSET) is 65uA with

ROSC=18.2kΩ. The total current sense amplifier input offset voltage is 0.6mV, which includes the offset created by

the current sense amplifier input resistor mismatch.

Calculate constant KP, the ratio of inductor peak current over average current in each phase,

(12 −1.335)⋅1.335 /(220⋅10⁻⁹⋅12⋅600⋅10³⋅2)

(V_I−V_O)⋅V_O/(L⋅V_I⋅ f_SW⋅2)

K_P

=

= 0.147

I_LIMIT/ n

115 / 5

R_LIMIT

n

R_OCSET= [

⋅ R_{L _ MAX}⋅(1+ K_P) +V_{CS _ TOFST}]⋅G_{CS _ MIN}/ I_OCSET

115

= (

⋅0.54⋅10⁻³⋅1.147 + 0.6⋅10⁻³)⋅30.2 /(65⋅10⁻⁶) = 6.9kΩ

5

No Load Output Voltage Setting Resistor RFB and Adaptive Voltage Positioning Resistor RDRP

From Figure 14, the bias current of FB pin is 65uA with ROSC=18.2kΩ.

0.54 ⋅10 ⁻³⋅15 ⋅10 ⁻³− 0.6 ⋅10 ⁻³⋅ 5 ⋅ 0.75 ⋅10 ⁻³

R_{L _ MAX}⋅V_{O _ NLOFST}− V_{CS _ TOFST}⋅ n ⋅ R_O

R_FB

Select RFB = 232 Ω.

_FB⋅ R_{L _ MAX}⋅G_{CS _ MIN}

=

= 230Ω

65 ⋅10 ⁻⁶⋅ 0.54 ⋅10 ⁻³

I _FB⋅ R_{L _ MAX}

232⋅0.54⋅10⁻³⋅30.2

5⋅0.75⋅10⁻³

R

R_DRP

=

= 1.01kΩ

n⋅ R_O

Page 26 of 26

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IR3086 EXTERNAL COMPONENTS

PWM Ramp Resistor RRAMP and Capacitor CRAMP

Set PWM ramp magnitude VPWMRMP=0.8V. Choose 100pF for PWM ramp capacitor CPWMRMP, and calculate the

resistor RPWMRMP,

V_O

R_PWMRMP

=

V_IN⋅ f_SW⋅C_PWMRMP⋅[ln(V_IN−V_DAC) − ln(V_IN−V_DAC−V_PWMRMP)]

1.30

=

=17.9kΩ , choose RPWMRMP=18.2kΩ

12⋅600⋅10³⋅100⋅10⁻¹²⋅[ln(12 −1.30) − ln(12 −1.30 − 0.8)]

Inductor Current Sensing Capacitor CCS+ and Resistors RCS+ and RCS-

Choose CCS+=47nF and calculate RCS+,

L R_L220⋅10⁻⁹/(0.42⋅10⁻³)

R_{CS +}

=

=11.2kΩ

C_{CS +}

47⋅10⁻⁹

Choose R_{CS +}=11.5kΩ . The bias currents of CSIN+ and CSIN- are 0.25uA and 0.4uA respectively. Calculate resistor

RCS-,

0.25

0.4

0.25

0.4

R_{CS −}

=

⋅ R_{CS +}

=

⋅10.0⋅10³= 7.19kΩ , choose RCS-=7.15kΩ

Over Temperature Setting Resistors RHOTSET1 and RHOTSET2

Use central over temperature setting and set the temperature threshold at 115 ºC, which corresponds the IC die

temperature of 116 ºC. Calculate the HOTSET threshold voltage corresponding to the temperature thresholds.

V_HOTSET= 4.73⋅10⁻³⋅T_J+1.241 = 4.73⋅10⁻³⋅116 +1.241 =1.79V , choose RHOTSET1=20.0kΩ,

R

_HOTSET1⋅V_HOTSET20⋅10³⋅1.79

R_{HOTSET 2}

=

= 7.14kΩ

V_BIAS−V_HOTSET

6.8 −1.79

Phase Delay Timing Resistors RPHASE1 and RPHASE2

The phase delay resistor ratios for phases 1 to 5 at 600kHz of switching frequencies are RAPHASE1=0.646,

RAPHASE2=0.400, RAPHASE3=0.158, RAPHASE4=0.291 and RAPHASE5=0.561 starting from down-slope. Pre-

select RPHASE11=RPHASE21=RPHASE31=RPHASE41=RPHASE51= RPHASE61=20kΩ,

RA_PHASE1

0.646

R_PHASE12

=

⋅ R_PHASE11

=

⋅20⋅10³= 36.5kΩ

1− RA_PHASE1

1− 0.646

RPHASE22=13.3kꢀ, RPHASE32=3.74kꢀ, RPHASE42=8.2kꢀ, PPHASE52=25.5kꢀ

Bootstrap Capacitor CBST

Choose CBST=0.1uF

Decoupling Capacitors for Phase IC and Power Stage

Choose CVCC=0.1uF, CVCCL=0.1uF

Page 27 of 27

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IR3082

VOLTAGE LOOP COMPENSATION

All ceramic output capacitors are used in the design, type III compensation as shown in Figure 18(b) is used here.

Choose the desired crossover frequency fc =80 kHz and determine Rcp and CCP:

(2π ⋅ f_C)²⋅ L_E⋅C_E⋅ R_FB⋅V_PWMRMP(2π ⋅80⋅10³)²⋅(220⋅10⁻⁹/5)⋅(47⋅10⁻⁶⋅32)⋅230⋅0.8

R_CP

=

= 2.31kΩ

V_o

1.335

10⋅ (220⋅10⁻⁹/ 5)⋅(47⋅10⁻⁶⋅32)

2.31⋅10³

10⋅ L_E⋅C_E

, Choose CCP=33nF

C_CP

=

= 35.2nF

R_CP

1

2

1

2

R_FB1

=

⋅ R_FB

=

⋅230 =115Ω

Choose R_FB1=100ꢀ

1

, choose CFB=10nF

C_FB

=

= 8.54nF

4π ⋅80⋅10³⋅100

4π ⋅ f_C⋅ R_FB1

Choose CCP1=220pF to reduce high frequency noise.

CURRENT SHARE LOOP COMPENSATION

The crossover frequency of the current share loop fCI should be at least one decade lower than that of the voltage

loop fC. Choose the crossover frequency of current share loop fCI=10kHz, and calculate CSCOMP,

R

_PWMRMP⋅C_PWMRMP⋅ f_SW⋅V _PWMRMP18.2⋅10³⋅100⋅10⁻¹²⋅600⋅10³⋅0.8

F_MI

=

= 0.011

(V_I−V_PWMRMP−V_DAC)⋅(V_I−V_DAC

)

(12 − 0.8 −1.35)⋅(12 −1.35)

0.65⋅ R_PWMRMP⋅V_I⋅ I_O⋅G_{CS _ ROOM}⋅ R_LE⋅[1+ 2π ⋅ f_CI⋅C_E⋅(V_OI_O)]⋅ F_MI

V_O⋅2π ⋅ f_CI⋅1.05⋅10⁶

C_SCOMP

=

0.65⋅18.2⋅10³⋅12⋅100⋅34⋅(0.42⋅10⁻³5)⋅[1+ 2π ⋅10⋅10³⋅1504⋅10⁻⁶⋅(1.33−100⋅7.5⋅10⁻⁴) 100]⋅0.011

=

(1.33−100⋅7.5⋅10⁻⁴)⋅2π ⋅10⋅10³⋅1.05⋅10⁶

= 12.4nF

Choose CSCOMP=22nF

Page 28 of 28

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IR3082

LAYOUT GUIDELINES

The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB

layout, therefore minimizing the noise coupled to the IC.

•

Dedicate at least one middle layer for a ground plane LGND.

Connect the ground tab under the control IC to LGND plane through a via.

Place the following critical components on the same layer as control IC and position them as close as possible

to the respective pins, ROSC, ROCSET, RVDAC, CVDAC, CVCC, CSS/DEL and RCC/DEL. Avoid using any via for the

connection.

•

Place the compensation components on the same layer as control IC and position them as close as possible to

EAOUT, FB and VDRP pins. Avoid using any via for the connection.

Use Kelvin connections for the remote voltage sense signals, VOSNS+ and VOSNS-, and avoid crossing over

the fast transition nodes, i.e. switching nodes, gate drive signals and bootstrap nodes.

Control bus signals, VDAC, RMPOUT, IIN, VBIAS, and especially EAOUT, should not cross over the fast

transition nodes.

Page 29 of 29

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IR3082

METAL AND SOLDER RESIST

• The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder

resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non

Solder Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads.

• The minimum solder resist width is 0.13mm, therefore it is recommended that the solder resist is

completely removed from between the lead lands forming a single opening for each “group” of lead

lands.

• At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a

fillet so a solder resist width of ≥ 0.17mm remains.

• The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto

the copper of 0.06mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is allowable

to have the solder resist opening for the land pad to be smaller than the part pad.

• Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high

aspect ratio of the solder resist strip separating the lead lands from the pad land.

• The single via in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm larger than

the diameter of the via.

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IR3082

PCB METAL AND COMPONENT PLACEMENT

• Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should

be ≥ 0.2mm to minimize shorting.

• Lead land length should be equal to maximum part lead length + 0.2 mm outboard extension + 0.05mm

inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard

extension will accommodate any part misalignment and ensure a fillet.

• Center pad land length and width should be equal to maximum part pad length and width. However, the

minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper and ≥

0.23mm for 3 oz. Copper)

• A single 0.30mm diameter via shall be placed in the center of the pad land and connected to ground to

minimize the noise effect on the IC.

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IR3082

STENCIL DESIGN

• The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands.

Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm

pitch devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower;

openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release.

• The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead

land.

• The land pad aperture should be striped with 0.25mm wide openings and spaces to deposit

approximately 50% area of solder on the center pad. If too much solder is deposited on the center pad

the part will float and the lead lands will be open.

• The maximum length and width of the land pad stencil aperture should be equal to the solder resist

opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the

lead lands when the part is pushed into the solder paste.

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IR3082

PACKAGE INFORMATION

20L MLPQ (5 x 5 mm Body) – θ_JA= 30^oC/W, θ_JC= 3^oC/W

Data and specifications subject to change without notice.

This product has been designed and qualified for the Consumer market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.

www.irf.com

Page 33 of 33

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型号：	IR3082
厂家：	Infineon
描述：	XPHASE AMD OPTERON/ATHLON 64 CONTROL IC 的XPhase AMD皓龙/速龙64控制IC
文件：	总33页 (文件大小：444K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IR3082 [INFINEON]

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