IR3513Z [INFINEON]
XPHASE3TM POL CONTROL IC; XPHASE3TM POL控制IC
| 型号： | IR3513Z |
| 厂家： | 
Infineon |
| 描述： | XPHASE3TM POL CONTROL IC |
| 文件： | 总36页 (文件大小：734K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IR3513Z
DATASHEET
XPHASE3TM POL CONTROL IC
DESCRIPTION
The IR3513Z Control IC provides overall control of a scalable number of phases along with an internal gate driver,
current sense/sharing, and PWM. This allows the IR3513Z to implement a stand-alone single-phase regulator or
interface with additional Phase ICs to develop a power solution with any number of phases. With this arrangement, the
final solution requires only 1 IC per phase to deploy 1 to X phases. Other approaches require a control IC plus 1 to X
driver ICs or scalable “all-in-one” ICs that do not utilize all IC pins or circuitry leading to increased solution cost and size.
FEATURES
•
•
•
•
0.8V reference supports 0.8V to 5.1V output voltage with +/-0.5% system set point accuracy
Dynamic margin function provides ± 5 % reference offset
1 (stand-alone) to X phase operation with additional Phase IC
Programmable 250 KHz to 9 Mhz daisy-chain digital phase timing provides a per phase switching
frequency of 250 KHz to 1.5 MHz with no external components
Differential remote sense amplifier with 100kohm input impedance
IC bias linear regulator control with programmable output voltage and UVLO
Programmable converter current limit during soft-start, hiccup with delay during normal operation
Over voltage protection communicated to Phase ICs
System over voltage signal protects against failures such as a shorted high side MOSFET
Detection and protection of open remote sense lines
Open control loop protection
•
•
•
•
•
•
•
•
•
•
7V/2A gate drivers (4A GATEL sink current)
Integrated boot-strap synchronous PFET
Small thermally enhanced 32L 5 x 5mm MLPQ package
APPLICATION CIRCUIT
Figure 1 - IR3513Z Application Circuit
Page 1
May 11, 2009
IR3513Z
ORDERING INFORMATION
Device
Package
Order Quantity
IR3513ZMTRPBF
32 Lead MLPQ (5 x 5 mm body)
32 Lead MLPQ(5 x 5 mm body)
3000 per reel
* IR3513ZMPBF
100 piece strips
•
Samples only
PIN DESCRIPTION
PIN#
PIN SYMBOL
PIN DESCRIPTION
1
2
GATEH
BOOST
High-side driver output and input to GATEL non-overlap comparator.
Supply for high-side driver. An internal bootstrap synchronous PFET is connected
between this pin and the VCCP pin.
3
VCCP
Supply for low-side driver. An internal bootstrap synchronous PFET is connected
from this pin to the BOOST pin.
4
5
GATEL
PGND
LGND
CSIN+
CSIN-
Low-side driver output and input to GATEH non-overlap comparator.
Return for low side driver and reference for GATEH non-overlap comparator.
Local Ground for internal circuitry and the IC substrate connection.
Non-Inverting input to the current sense amplifier and input to debug comparator.
6, 24
7
8
Inverting input to the current sense amplifier and input to synchronous rectification
disable comparator.
9
ENABLE
PG
Enable input. A logic low applied to this pin puts the IC into fault mode. Do not float
this pin as the logic state will be undefined.
10
11
Open drain output that drives low during startup and under any external fault
condition. Connect external pull-up.
MARGIN
Tri-state input with internal pull-up to 1.425 V. Low/High voltage shifts the Error
Amplifier reference voltage Up/Down 5%. V(MARGIN) should not be biased to a
voltage greater than V(VCCL).
12
13
VOSEN-
VOSEN+
VCCL
Inverting remote sense amplifier input. Connect to ground at the load.
Non-inverting remote sense amplifier input. Connect to output at the load.
14, 28
Output of the voltage regulator, power input for clock oscillator circuitry and other
internal circuitry. Connect a decoupling capacitor to LGND.
15
16
17
18
19
VOUT
OVSNS
FB
Remote sense amplifier output.
Over voltage sense input during normal operation.
Inverting input to the Error Amplifier.
Output of the Error Amplifier.
EAOUT
IIN
Average current input signal from active and inactive phase IC(s). This pin is also
used to communicate an over voltage condition to the phase IC(s).
20
OCSET
An external resistor tied to VREF along with a fixed internal current source
programs the constant output current limit and hiccup over-current thresholds.
Over-current protection can be disabled by programming the threshold higher than
the possible signal on the IIN pin, but no greater than 5V (do not float this pin).
21
22
VREF
Reference voltage for the Error Amplifier. An external RC network to LGND
programs the margin slew rate and compensates the internal buffer amp.
SS/DEL
An external capacitor to LGND programs converter startup and over current
protection delay timing. It is also used to compensate the constant output current
loop during soft start.
Page 2
May 11, 2009
IR3513Z
PIN DESCRIPTION CONTINUED
23
ROSC/OVP
A resistor to LGND to program the oscillator frequency and the OCSET bias current.
Oscillator frequency equals the phase switching frequency. The pin voltage is 0.6V
during normal operation and higher than 1.6V if over-voltage condition is detected.
25
26
27
29
30
31
32
CLKOUT
PHSOUT
PHSIN
Frequency is equivalent to the phase switching frequency multiplied by the number
of phases. Connect to CLKIN pins of phase ICs.
Phase timing output switching at the phase frequency. Connect to PHSIN pin of the
first phase IC.
Feedback input of the phase timing clock. Connect to the PHSOUT pin of the last
phase IC.
VCCLFB
VCCLDRV
VCC
Non-inverting input of the voltage regulator error amplifier. Output voltage of the
regulator is programmed by a resistor divider connected to VCCL.
Output of the VCCL regulator error amplifier to control an external transistor. The pin
senses the input of the power supply through a resistor at power-up.
Power Input for under voltage lockout (UVLO) detection and supply for internal IC
circuits.
SW
Return for high-side driver and reference for GATEL non-overlap comparator.
Page 3
May 11, 2009
IR3513Z
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specifications are not implied.
Operating Junction Temperature……………..0 to 150oC
Storage Temperature Range………………….-65oC to 150oC
MSL Rating………………………………………2
Reflow Temperature…………………………….260oC
PIN #
PIN NAME
VMAX
VMIN
ISOURCE
ISINK
1
GATEH
34V
-0.3VDC, -5V
for 100ns
3A for 100ns, 100mA DC 3A for 100ns, 100mA DC
2
3
4
BOOST
VCCP
34V
8V
-0.3V
-0.3V
1A for 100ns, 100mA DC 3A for 100ns, 100mA DC
n/a
5A for 100ns, 200mA DC
GATEL
8V
-0.3VDC, -5V
for 100ns
5A for 100ns, 200mA DC 5A for 100ns, 200mA DC
5
6, 24
7
PGND
LGND
0.3V
n/a
-0.3V
n/a
5A for 100ns, 200mA DC
n/a
1mA
1mA
5mA
1mA
20mA
1mA
1mA
1mA
25mA
25mA
1mA
1mA
10mA
1mA
1mA
1mA
1mA
1mA
100mA
10mA
1mA
1mA
50mA
1mA
n/a
20mA
1mA
1mA
1mA
1mA
1mA
5mA
5mA
1mA
5mA
1mA
1mA
25mA
5mA
1mA
1mA
1mA
5mA
100mA
10mA
1mA
1mA
1mA
1mA
CSIN+
CSIN-
8V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.5V
-0.5V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
8
8V
9
ENABLE
PG
3.5V
VCCL + 0.3V
8V
10
11
12
13
14, 28
15
16
17
18
19
20
21
22
23
25
26
27
29
30
31
32
MARGIN
VOSEN-
VOSEN+
VCCL
1.0V
8V
8V
VOUT
8V
OVSNS
FB
8V
8V
EAOUT
IIN
8V
8V
OCSET
VDAC
8V
3.5V
8V
SS/DEL
ROSC/OVP
CLKOUT
PHSOUT
PHSIN
VCCLFB
VCCLDRV
VCC
8V
8V
8V
8V
3.5V
10V
18V
34V
SW
-0.3V DC, -5V 3A for 100ns, 100mA DC
for 100ns
Note: Maximum GATEH – SW = 8V, Maximum BOOST – GATEH = 8V
Page 4
May 11, 2009
IR3513Z
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
4.75V ≤ VCCL ≤ 7.5V, 4.75V ≤ VCCP ≤ 7.5V, 8V ≤ VCC ≤ 16V, -0.3V ≤ VOSEN- ≤ 0.3V, 0 oC ≤ TJ ≤ 125 oC,
7.75 kΩ ≤ ROSC ≤ 50 kΩ
ELECTRICAL CHARACTERISTICS
The electrical characteristics involve the spread of values guaranteed within the recommended operating conditions.
Typical values represent the median values, which are related to 25°C. 7.75KΩ ≤ ROSC ≤ 50.0 KΩ, CSS/DEL = 0.1µF +/-
10%, CGATEH = 3.3nF, CGATEL = 6.8nF (unless otherwise specified).
PARAMETER
VREF Reference
System Set-Point Accuracy MARGIN = OPEN
TEST CONDITION
MIN
TYP
MAX
UNIT
796
755
835
50
800
760
840
88
804
765
845
116
0.675
2.3
mV
mV
mV
µA
V
(per test circuit in Fig. 2)
MARGIN = 0V
MARGIN = VCCL
Include OCSET current
Margin Low
Source & Sink Currents
Margin Input Thresholds
0.475
2.1
0.575
2.2
Margin High
V
MARGIN Float Voltage
MARGIN Pull-up resistor
Oscillator
1.325
3
1.425
4
1.55
6
V
Kꢀ
ROSC Voltage
0.575
0.600
0.625
1
V
V
CLKOUT High Voltage
I(CLKOUT)=-10mA, measure V(VCCL)–
V(CLKOUT)
CLKOUT Low Voltage
CLKOUT Phase Delay
I(CLKOUT)= 10mA
1
V
Measure time from CLKIN < 1V to GATEH
> 1V
40
75
125
ns
PHSOUT Frequency
PHSOUT Frequency
PHSOUT Frequency
PHSOUT High Voltage
PHSOUT Low Voltage
PHSIN Threshold Voltage
Enable Input
ROSC=50.0 Kꢀ
225
450
1.35
250
500
1.50
275
550
1.65
1
kHz
kHz
MHz
V
ROSC=24.5 Kꢀ
ROSC=7.75 Kꢀ
I(PHSOUT)= -1mA
I(PHSOUT)= 1mA
Compare to V(VCCL)
1
V
30
50
70
%
Threshold Voltage
Threshold Voltage
Hysteresis
ENABLE rising
ENABLE falling
815
765
25
850
800
50
885
835
75
mV
mV
mV
µA
ns
Bias Current
0V ≤ V(ENABLE) ≤ 3.3V
-5
0
5
Blanking Time
Noise Pulse < 100ns will not register an
ENABLE state change. Note 1
75
250
400
Page 5
May 11, 2009
IR3513Z
PARAMETER
Over-Current Comparator
Input Offset Voltage
TEST CONDITION
1V ≤ V(OCSET) ≤ 3.3V
MIN
TYP
MAX
UNIT
-70
-40
-10
mV
605
/ Rosc(kꢀ )
OCSET Bias Current
-5%
+5%
µA
Over-Current Delay Counter
Over-Current Delay Counter
Over-Current Delay Counter
Over-Current Limit Amplifier
Input Offset Voltage
ROSC = 7.75 Kꢀ (PHSOUT=1.5MHz)
ROSC = 15.0 Kꢀ (PHSOUT=800kHZ)
ROSC = 50.0 Kꢀ (PHSOUT=250kHz)
4096
2048
1024
Cycle
Cycle
Cycle
-10
0.50
35
0
15
1.75
75
mV
mA/V
uA
Transconductance
Note 1
Note 1
1.00
55
Sink Current
Unity Gain Bandwidth
0.75
2.00
3.00
kHz
Over Voltage Detection (OVD) Comparator
Threshold Offset Rising
Threshold Offset Falling
Threshold Hysteresis
Compare to V(VREF)
60
-15
55
85
5
105
25
mV
mV
mV
ns
Compare to V(VREF)
70
90
80
Propagation Delay to IIN
Measure time from V(VOUT) > V(VREF)
(250mV overdrive) to V(IIN) transition to
> 0.9 * V(VCCL).
180
IIN Pull-up Resistance
5
0
20
1
ꢀ
OVSNS Input Bias Current
0V ≤ V(OVSNS) ≤ V(VCCL),
-1
µA
Over Voltage Protection (OVP) Comparator
OVP Threshold
Step V(ISHARE) up until GATEL drives
high. Compare to V(VCCL)
-1.0
0
-0.8
40
0
V
Propagation Delay
V(VCCL)=5V, Step V(ISHARE) up from
V(DACIN) to V(VCCL). Measure time to
V(GATEL)>4V.
70
ns
Propagation Delay to ROSC
Measure time from V(VO) > V(VDAC)
(250mV overdrive) to V(ROSC/OVP)
transition to >1V. Note 1.
90
300
ns
V
OVP ROSC High Voltage
Measure V(VCCL)-V(ROSC/OVP)
0
0.5
6.4
1.2
9.0
Remote Sense Differential Amplifier
Unity Gain Bandwidth
Input Offset
Note 1
3.0
MHz
%
Relative to [V(VOSEN+) - V(VOSEN-)].
1.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 5.5V
0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 1.5V
-0.2
-3
0
0
0.2
3
mV
mA
mA
Source Current
Sink Current
0.5V≤ V(VOSEN+) - V(VOSEN-) ≤ 5.5V
0.5
1.0
1.7
Vout=0.5V
Vout=5.5V
1
11
4
25
9
34
Slew Rate
Note 1
2
4
8
V/us
kꢀ
V
Input Impedance
63
100
185
5.5
0.1
250
VOSEN+ Input Voltage Range V(VCCL)=7V
High Voltage
Low Voltage
V(VCCL) – V(VO)
V(VCCL)=7V
0.03
V
mV
Page 6
May 11, 2009
IR3513Z
PARAMETER
Soft Start and Delay
Start Delay
TEST CONDITION
MIN
TYP
MAX
UNIT
1.0
0.9
0.4
75
2.2
1.5
1.3
125
1.4
3.5
4.5
3.8
300
1.9
ms
ms
ms
us
V
Soft Start Time
PG Delay
OC Delay Time
V(IIN) – V(OCSET) = 500 mV
SS/DEL to FB Input Offset
Voltage
With FB = 0V, adjust V(SS/DEL) until
EAOUT drives high
0.7
Charge Current
30
2
50
4
65
6
µA
µA
Discharge Current
Charge/Discharge Current
Ratio
10
12
17
µA/µA
Charge Voltage
2.8
3
3.3
V
Delay Comparator Threshold
Relative to Charge Voltage, SS/DEL
rising – Note 1
80
mV
Delay Comparator Threshold
Delay Comparator Hysteresis
Relative to Charge Voltage, SS/DEL
falling – Note 1
120
mV
Note 1
30
mV
mV
Discharge Comparator
Threshold
125
200
275
Error Amplifier
Input Offset Voltage
FB Bias Current
DC Gain
Measure V(FB) – V(VREF). Note 2
-1
-1
0
0
1
1
mV
µA
dB
Note 1
Note 1
Note 1
100
20
110
30
120
40
Bandwidth
MHz
V/µs
mA
mA
mV
mV
mV
Slew Rate
7
12
20
Sink Current
0.40
5
0.85
8
1.00
12
Source Current
Maximum Voltage
Minimum Voltage
Measure V(VCCL) – V(EAOUT)
500
780
120
500
950
250
1000
Open Voltage Loop Detection
Threshold
Measure V(VCCL) - V(EAOUT), Relative
to Error Amplifier maximum voltage.
100
Open Voltage Loop Detection
Delay
Measure PHSOUT pulse numbers from
V(EAOUT) = V(VCCL) to PG = low.
8
Pulses
Headroom Control
Activation Voltage
V(VCC) – V(CSIN-)
2.7
-640
-18.5
5
2.95
-470
-13.5
8
3.3
-300
-9
V
FB Bias Current
V(VCC) – V(CSIN-) = 1.0V
uA
uA
uA
PG Comparator Threshold
PG Comparator Hysteresis
13.5
VCC Under Voltage Lockout Comparator (UVLO)
Start Threshold
6.9
6.5
7.4
7.0
7.9
7.5
V
V
Stop Threshold
Hysteresis
Start – Stop
350
450
650
mV
Page 7
May 11, 2009
IR3513Z
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Open Sense Line Detection
Sense Line Detection Active
Comparator Threshold Voltage
150
40
200
60
250
90
mV
mV
%
Sense Line Detection Active
Comparator Offset Voltage
V(VOUT) < [V(VOSEN+) – V(LGND)] / 2
Compare to V(VCCL)
VOSEN+ Open Sense Line
Comparator Threshold
87.5
0.36
250
90
92.5
0.44
750
VOSEN- Open Sense Line
Comparator Threshold
0.40
500
V
Sense Lines Detection Source
Currents
V(VOUT) = 100mv
uA
VCCL Regulator Amplifier
Reference Feedback Voltage
VCCLFB Bias Current
VCCLDRV Sink Current
UVLO Start Threshold
UVLO Stop Threshold
Hysteresis
1.15
-1
1.19
0
1.23
1
V
uA
mA
%
10
30
94
86
8.5
Compare to V(VCCL)
Compare to V(VCCL)
Compare to V(VCCL)
90
98
90
82
%
7.0
9.5
%
Gate Drivers
GATEH Source Resistance
GATEH Sink Resistance
GATEL Source Resistance
GATEL Sink Resistance
GATEH Source Current
BOOST – SW = 7V. Note 1
BOOST – SW = 7V. Note 1
VCCP – PGND = 7V. Note 1
VCCP – PGND = 7V. Note 1
1.0
1.0
1.0
0.4
2.0
2.5
2.5
2.5
1.0
ꢀ
ꢀ
ꢀ
ꢀ
A
BOOST=7V,GATEH=2.5V,SW=0V. Note
1
GATEH Sink Current
GATEL Source Current
GATEL Sink Current
GATEH Rise Time
GATEH Fall Time
BOOST=7V,GATEH=2.5V,SW=0V. Note
1
2.0
2.0
4.0
5
A
A
VCCP=7V, GATEL=2.5V, PGND=0V
Note 1
VCCP=7V, GATEL=2.5V, PGND=0V
Note 1
A
BOOST – SW = 7V, measure 1V to 4V
transition time
10
10
20
10
40
ns
ns
ns
ns
ns
BOOST - SW = 7V, measure 4V to 1V
transition time
5
GATEL Rise Time
GATEL Fall Time
VCCP – PGND = 7V, Measure 1V to 4V
transition time
10
5
VCCP – PGND = 7V, Measure 4V to 1V
transition time
GATEL low to GATEH high
delay
BOOST = VCCP = 7V, SW = PGND =
0V, measure time from GATEL falling to
1V to GATEH rising to 1V
10
10
20
GATEH low to GATEL high
delay
BOOST = VCCP = 7V, SW = PGND =
0V, measure time from GATEH falling to
1V to GATEL rising to 1V
Ta=25 oC Note 1
20
80
40
ns
Disable Pull-Down Resistance
130
kꢀ
Page 8
May 11, 2009
IR3513Z
PARAMETER
PWM Comparator
TEST CONDITION
MIN
TYP
MAX
UNIT
PWM Ramp Slope
mV/
DC%
42
-5
52.5
57
Input Offset Voltage
Minimum Pulse Width
Note 1
Note 1
0
5
mV
ns
65
80
75
Minimum GATEH Turn-off
Time
20
160
ns
Current Sense Amplifier
CSIN+/- Bias Current
-200
-50
0
0
200
50
nA
nA
CSIN+/- Bias Current
Mismatch
Note 1
Input Offset Voltage
CSIN+ = CSIN- = VREF. Measure input
referred offset from VREF
-1
0
1
mV
Gain
Csin+=25mV+Csin-
30.5
4.8
33.0
6.8
35.5
8.8
V/V
Unity Gain Bandwidth
C(IIN)=10pF. Measure at IIN.
Note 1
MHz
Slew Rate
Note 1
Note 1
6
V/µs
mV
mV
V
Differential Input Range
Differential Input Range
Common Mode Input Range
Rout at TJ = 25 oC
-10
-5
50
50
-0.2
2.3
2.9
3.6
500
500
Note3
3.7
3.0
3.7
4.7
kꢀ
kꢀ
kꢀ
µA
µA
Rout at TJ = 65 oC
4.6
Rout at TJ = 125 oC
ISHARE Source Current
ISHARE Sink Current
Share Adjust Amplifier
Input Offset Voltage
Differential Input Range
Gain
5.4
Note 1
Note 1
-3
-1
4
0
3
1
6
mV
V
CSIN+ = CSIN- = VREF, Adjust V(IIN)
from V(Ramp floor) – 10mV to V(Ramp
floor) + 10mV and measure change in
PWM Ramp Start Voltage. Note 1.
5.0
V/V
Unity Gain Bandwidth
Note 1
4
8.5
17
kHz
mV
Maximum PWM Ramp Adjust
Voltage
CSIN+ = CSIN- = VREF, EAOUT
=LGND, and V(IIN) = V(Ramp floor) -
100mV. Maximum adjust voltage
=V(PWMRMP) – V(Ramp floor)
90
150
250
Minimum PWM Ramp Adjust
Voltage
CSIN+ = CSIN- = VREF, EAOUT
=LGND, and V(ISHARE) = V(Ramp
floor) + 100mV. Minimum adjust voltage
= V(PWMRMP) – V(Ramp floor)
-230
130
-70
mV
Body Brake Comparator
Threshold Voltage Increasing
Compare to V(Ramp floor)
-225
-315
40
-125
-215
90
-25
-115
140
70
mV
mV
mV
ns
Threshold Voltage decreasing Compare to V(Ramp floor)
Threshold Hysteresis
Propagation Delay
VCCL = 5V. Measure time from EAOUT
20
40
< V(VREF) (200mV overdrive) to
GATEL transition to < 4V.
Page 9
May 11, 2009
IR3513Z
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Synchronous Rectification Disable Comparator
Threshold Voltage
The ratio of V(CSIN-) / V(VREF), below
63
75
89
%
which V(GATEL) is always low.
Negative Current Comparator
Input Offset Voltage
Note 1
-16
0
16
mV
ns
Propagation Delay Time
Apply step voltage to V(CSIN+) –
V(CSIN-). Measure time to V(GATEL)<
1V.
200
400
Bootstrap Diode
Forward Voltage
I(BOOST) = 30mA, 6V ≤ VCCL ≤ 7V
180
260
470
-60
mV
mV
Debug Comparator
Threshold Voltage
PG Output
Compare to V(VCCL)
-260
-150
Output Voltage
I(PG) = 4mA
150
0
300
10
mV
µA
V
Leakage Current
VCC PG Activation Threshold
V(PG) = 5.5V
I(PG)=4mA, V(PG)<300mV
1
2
3.5
Output Under Voltage Comparator
Threshold Voltage Falling
Threshold Voltage Rising
Threshold Hysteresis
0.600
0.660
20
0.665
0.715
50
0.730
0.770
90
V
V
mV
General
VCC Supply Current
VCCL Supply Current
VCCP Supply Current
BOOST Supply Current
SW Floating Voltage
V(VCC) – V(VOUT) > 2.5V
1.1
9
3.0
14
6.1
19
mA
mA
uA
mA
V
V(VCCP)=7V, V(BOOST)=7V
4V ≤ V(BOOST) ≤ 30V
50
1.2
150
3.5
0.3
300
5.8
Measured in the application
Note 1: Guaranteed by design, but not tested in production
Note 2: VREF Output is trimmed to compensate for Error & Remote Sense Amp input offsets
Note 3: VCCL-0.5V or VCC – 2.5V, whichever is lower
Page 10
May 11, 2009
IR3513Z
SYSTEM SET POINT TEST
ERROR
AMPLIFIER
IR3513
VREF
BUFFER
AMPLIFIER
EAOUT
FB
+
1k
-
+
ISOURCE
ISINK
INTERNAL
VREF
VREF
OCSET
-
RVREF
IOCSET-
IOCSET
IROSC
CVREF
ROSC BUFFER
AMPLIFIER
CURRENT
SOURCE
GENERATOR
0.6V
IROSC
LGND
+
-
RROSC
ROSC
VOUT
REMOTE SENSE
AMPLIFIER
EAOUT
SYSTEM
SET POINT
VOSNS-
VOLTAGE
50K
50K
VOSEN+
VOSEN-
+
-
50K
50K
Figure 2 - System Set Point Test Circuit
Page 11
May 11, 2009
IR3513Z
SYSTEM THEORY OF OPERATION
PWM Control Method
The PWM block diagram of the XPhaseTM architecture is shown in Figure 3. Feed-forward voltage mode control with
trailing edge modulation is used. A voltage-type error amplifier with high-gain (110dB) and wide-bandwidth is used for
the control loop. It is not unity gain stable. The power-stage input voltage is sensed by the IR3513Z, and optional phase
ICs, to provide feed-forward control. The PWM ramp slope will change with the input voltage and automatically
compensate for changes in the input voltage. The input voltage can change due to variations in the silver box output
voltage or due to the wire and PCB-trace voltage drop related to changes in load current.
VOSNS+
VOSNS-
IR3513 CONTROL IC
VCC
CLOCK GENERATOR
VIN
CLK
D
Q
VCCH
IC BIAS
PWM
LATCH
GATEH
CBST
REMOTE SENSE +
VOUT
S
PWM
COMPARATOR
SW
RESET
DOMINANT
COUT
-
R
VCCL
+
GND
GATEL
PGND
ENABLE
+
VID6-
BODY
BRAKING
COMPARATOR
REMOTE SENSE -
REMOTE SENSE
AMPLIFIER
RAMP
DISCHARGE
CLAMP
SHARE ADJUST
ERROR AMPLIFIER
+
CURRENT
SENSE
AMPLIFIER
+
+
VID6
VID6
+
-
CSIN+
CSIN-
-
VREF
3K
CCS RCS
ERROR
VID6
VID6+
+
-
-
AMPLIFIER
VO
FB
PHSOUT
CLKIN
PHASE IC
VCC
CLK
D
Q
VCCH
PWM
LATCH
RCOMP
CCOMP
GATEH
CBST
PHSIN
EAIN
RFB1
CCOMP1
S
RFB
PWM
COMPARATOR
SW
RESET
DOMINANT
CFB
-
R
VCCL
+
GATEL
PGND
ENABLE
+
-
VID6
BODY
BRAKING
COMPARATOR
RAMP
DISCHARGE
CLAMP
SHARE ADJUST
ERROR AMPLIFIER
+
CURRENT
SENSE
AMPLIFIER
+
VID6
VID6
+
ISHARE
DACIN
-
CSIN+
CSIN-
-
3K
CCS RCS
VID6
VID6+
+
-
Control Bus to
Power Bus to
additional Phases
additional Phases
Figure 3 - PWM Block Diagram
Frequency and Phase Timing Control
The oscillator system clock frequency is programmable from 500 kHz to 9 MHZ by an external resistor. The IR3513Z
system clock signal (CLKOUT) is connected to CLKIN of all the phase ICs. The phase timing of the phase ICs is
controlled by the daisy chain loop, where the IR3513Z phase clock output (PHSOUT) is connected to the phase clock
input (PHSIN) of the first phase IC, and PHSOUT of the first phase IC is connected to PHSIN of the second phase IC,
etc. The last phase IC (PHSOUT) is connected back to PHSIN of the control IC to complete the loop. During power up,
the IR3513Z sends out clock signals from both CLKOUT and PHSOUT pins and detects the feedback at PHSIN pin to
determine the phase number and monitor any fault in the daisy chain loop. Figure 4 shows the phase timing for a four-
phase converter. For single-phase operation, PHSOUT (pin 26) and PHSIN (pin 27) must be shorted together to
prevent an Open Control Loop fault from occurring.
Page 12
May 11, 2009
IR3513Z
Control IC CLKOUT
(Phase IC CLKIN)
Control IC PHSOUT
(Phase IC1 PHSIN)
Phase IC1
PWM Latch SET
Phase IC 1 PHSOUT
(Phase IC2 PHSIN)
Phase IC 2 PHSOUT
(Phase IC3 PHSIN)
Phase IC 3 PHSOUT
(Phase IC4 PHSIN)
Phase IC4 PHSOUT
(Control IC PHSIN)
Figure 4 - Five Phase Oscillator Waveforms
PWM Operation
Upon receiving the falling edge of a clock pulse, the PWM latch is set; the PWM ramp voltage begins to increase; the
low side driver is turned off, and the high side driver is then turned on after the non-overlap time. When the PWM ramp
voltage exceeds the error amplifier’s output voltage the PWM latch is reset. This turns off the high side driver and then
turns on the low side driver after the non-overlap time and activates the ramp discharge clamp. The ramp discharge
clamp quickly discharges the PWM ramp capacitor to the output voltage of the share adjust amplifier in the phase IC
until the next clock pulse.
The PWM latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in
response to a load step decrease. Phases can overlap and go up to 100% duty cycle in response to a load step
increase with turn-on gated by the clock pulses. An error amplifier output voltage greater than the common mode input
range of the PWM comparator results in up to 100% duty cycle regardless of the voltage of the PWM ramp. This
arrangement guarantees the error amplifier is always in control and can demand 0 to 100% duty cycle as required. It
also favors response to a load step decrease, which is appropriate given the low output to input voltage ratio of most
systems. The inductor current will increase much more rapidly than decrease in response to load transients. An
additional advantage of the architecture is that differences in ground or input voltage at the phases have no effect on
operation since the PWM ramps are referenced to VREF.
Figure 5 depicts PWM operating waveforms under various conditions.
Page 13
May 11, 2009
IR3513Z
Figure 5 - PWM Operating Waveforms
Body BrakingTM
In a conventional synchronous buck converter, the minimum time required to reduce the current in the inductor in
response to a load step decrease is;
L*(IMAX − IMIN
)
TSLEW
=
VO
The slew rate of the inductor current can be significantly increased by turning off the synchronous rectifier in response
to a load step decrease. The switch node voltage is then forced to decrease until conduction of the synchronous
rectifier’s body diode occurs. This increases the voltage across the inductor from Vout to Vout + VBODYDIODE. The
minimum time required to reduce the current in the inductor in response to a load transient decrease is now;
L*(IMAX − IMIN
VO +VBODYDIODE
)
TSLEW
=
Since the voltage drop in the body diode is often higher than the output voltage, the inductor current slew rate can be
increased by 2X or more. This patent pending technique is referred to as “body braking” and is accomplished through
the “body braking comparator”. If the error amplifier’s output voltage drops below the VREF voltage or a programmable
voltage, this comparator turns off the low side gate driver.
Lossless Average Inductor Current Sensing
Inductor current can be sensed by connecting a series resistor and a capacitor network in parallel with the inductor and
measuring the voltage across the capacitor, as shown in Figure 6. The equation of the sensing network is,
1
RL + sL
1+ sRCSCCS
vC (s) = vL (s)
= iL (s)
1+ sRCSCCS
Usually the resistor Rcs and capacitor Ccs are chosen so that the time constant of Rcs and Ccs equals the time
constant of the inductor which is the inductance L over the inductor DCR (RL). If the two time constants match, the
voltage across Ccs is proportional to the current through L, and the sense circuit can be treated as if only a sense
resistor with the value of RL was used. The mismatch of the time constants does not affect the measurement of inductor
DC current, but affects the AC component of the inductor current.
Page 14
May 11, 2009
IR3513Z
L
v
L
L
R
R
L
i
O
V
CS
CS
C
C
Current
Sense Amp
c
vCS
CSOUT
Figure 6 - Inductor Current Sensing and Current Sense Amplifier
The advantage of sensing the inductor current versus high side or low side sensing is that actual output current being
delivered to the load is obtained rather than peak or sampled information about the switch currents. The output voltage
can be positioned to meet a load line based on real time information. Except for a sense resistor in series with the
inductor, this is the only sense method that can support a single cycle transient response. Other methods provide no
information during either load increase (low side sensing) or load decrease (high side sensing).
An additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from
peak-to-average errors. These errors will show in many ways but one example is the effect of frequency variation. If the
frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance
of the converter will drop by about 10%. Variations in inductance, current sense amplifier bandwidth, PWM prop delay,
any added slope compensation, input voltage, and output voltage are all additional sources of peak-to-average errors.
Current Sense Amplifier
A high speed differential current sense amplifier is included in both the IR3513Z and optional phase ICs, as shown in
Figure 6. Its gain is nominally 33 at 25ºC, and the 3850 ppm/ºC increase in inductor DCR should be compensated in the
voltage loop feedback path.
The current sense amplifier can accept positive differential input up to 50mV and negative up to -10mV before clipping.
The output of the current sense amplifier is summed with the VREF voltage and sent to other phases through an on-
chip 3Kꢀ resistor connected to the ISHARE pin. The ISHARE pins of all the phases are tied together and the voltage on
the share bus represents the average current through all the inductors and is used by the control IC for voltage
positioning and current limit protection. The input offset of this amplifier is calibrated to +/- 1mV in order to reduce the
current sense error.
The input offset voltage is the primary source of error for the current share loop. In order to achieve very small input
offset error and superior current sharing performance, the current sense amplifier continuously calibrates itself. This
calibration algorithm creates ripple on ISHARE bus with a frequency of fsw/896.
Average Current Share Loop
Current sharing between phases of the converter is achieved by the average current share loop in each phase IC. The
output of the current sense amplifier is compared with average current at the share bus. If current in a phase is smaller
than the average current, the share adjust amplifier of the phase will pull down the starting point of the PWM ramp
thereby increasing its duty cycle and output current; if current in a phase is larger than the average current, the share
adjust amplifier of the phase will pull up the starting point of the PWM ramp thereby decreasing its duty cycle and output
current. The current share amplifier is internally compensated so that the crossover frequency of the current share loop
is much slower than that of the voltage loop and the two loops do not interact.
Page 15
May 11, 2009
IR3513Z
IR3513Z THEORY OF OPERATION
Block Diagram
The IR3513Z Block diagram is shown in Figure 7, and specific features are discussed in the following sections.
ENABLE
VCC
COMPARATOR
SS CLEARED
FAULT LATCH1
-
+
ENABLE
250nS
BLANKING
PG
400K
DISABLE
OC after VRRDY
VCCL UVLO
FAULT LATCH1
DELAY
COMPARATOR
VR READY
LATCH
850mV
800mV
S
Q
VCC UVLO
OC before VRRDY
SET
DOMINANT
+
OC
RESET
IROSC
S
Q
R
-
VCCLDRV
VCCLFB
RESET
DOMINANT
80mV
120mV
OC DELAY
COUNTER
PHSOUT
VCCL REGULATOR
DISCHARGE
COMPARATOR
HEADROOM
CONTROL
AMPLIFIER
INTERNAL
CIRCUIT
BIAS
R
VCCL
OC
RESET
+
-
3.2V
UV CLEARED
FAULT LATCH2
-
OPEN SENSE LINE
OPEN DAISY CHAIN
OV
+
UNDER
S
Q
OPEN CONTROL LOOP
0.2V
VOLTAGE
MONITOR
0.94
0.86
OV
SET
1.19V
VCCL OUTPUT
COMPARATOR
+
7.4V
7.0V
8-Pulse
Delay
DOMINANT
VCCL UVLO
UVLO
COMPARATOR
OC LIMIT
COMPARATOR
+
R
VCCL UVLO
0V@START
300mV
VCCL
-
+
-
+
-
-
VCC
IIN
EAOUT
SS/DEL
OCSET
-
1.425V
4K
OPEN CONTROL
LOOP
COMPARATOR
+
-
VREF=0.84V
VID4
IROSC
INTERNAL
VREF
IOCSET
2.2V
MARGIN INPUT
COMPARATORS
SOFT
START
CLAMP
OC LIMIT
AMPLIFIER
1.4V
DISABLE
+
+
+
-
0.8V
-
MARGIN
EAOUT
FB
VREF=0.76V
+
-
VDACFAST
IDCHG
+
4.5uA
ERROR
AMPLIFIER
0.897X
0.575V
DETECTION
PULSE
OV
HR
+
VID4
OV
HEADROOM CONTR
VCCL*0.9
0.4V
ISOURCE
ISINK
HEADROOM CONTROL
AMPLIFIER
COMPARATOR
IROSC
IOCSET-
-
+
VCC
OVSNS
-
+
-
CSIN-
EN
+
OPEN SENSE LINE
HR
85mV
5mV
-
2.95V
VREF BUFFER
AMPLIFIER
-
50K
VREF
VOUT
+
EN
VCCL-0.5V
50K
50K
REMOTE SENSE
AMPLIFIER
+
-
VOSEN+
VOSEN-
ROSC BUFFER
AMPLIFIER
+
IVOSEN-
IROSC
CURRENT
SOURCE
GENERATOR
IVOSEN+
50K
4
OPEN SENSE
LINE DETECT
COMPARATORS
0V
60mV
VIDSEL
-
+
INV
VCCL
VCCL
0.6V
-
ROSC/OVP
DETECTION PULSE
IVOSEN-
200mV
+
-
OSCILLATOR (4 PHASE APPLICATION WAVEFORM SHOWN)
VID0
OPEN DAISY CHAIN
RESET
CLKOUT
PHSOUT
PHSIN
VCCL UVLO
ODC
VID0
GATEH
DRIVER
BOOST
CLK
D
Q
GATEH
SW
PWM LATCH
GATEH NON-
PWM
COMPARATOR
GATEH NON-
OVERLAP
COMPARATOR
-
OVERLAP LATCH
D
Q
Q
EAIN
-
CLK
Q
S
R
+
SET
+
DOMINANT
RESET
DOMINANT
PHSIN
100% DC LIMIT
RMPOUT
GATEL NON-1V
OVERLAP
PWM RAMP
GENERATOR
GATEL NON-
OVERLAP LATCH
VCC
COMPARATOR
1V
VCCL
CALIBRATION
+
PWM RESET
DACIN-SHARE_ADJ
-100mV
Q
S
R
-
SET
DOMINANT
-200mV
BODY BRAKING
COMPARATOR
GATEL
DRIVER
+
-
VCCP
GATEL
PGND
OVP
COMPARATOR
VCCL
-
+
0.8V
+
RESET
DOM
SYNCHRONOUS
RECTIFICATION
DISABLE
150mV
IIN
R
-
+
-
DEBUG OFF
(LOW=OPEN)
Q
S
NEGATIVE CURRENT
COMPARATOR
COMPARATOR
-
+
SHARE
ADJUST
AMPLIFIER
GATEL ENABLE
LATCH
DEBUG
CURRENT SENSE
AMPLIFIER
-
+
COMPARATOR
3K
+
IROSC
CSIN-
CSIN+
-
X33
+
-
CALIBRATION
+
+
X
CALIBRATION
0.75
LGND
IROSC
Figure 7 - Block Diagram
Page 16
May 11, 2009
IR3513Z
VREF Control
The MARGIN input comparators monitor the MARGIN pin and control the internal reference voltage whose output is
sent to the VREF buffer amplifier. The output of the buffer amplifier is the VREF pin. The VREF voltage, input offsets of
error amplifier and remote sense differential amplifier are post-package trimmed to provide 0.8% system set-point
accuracy. The actual VREF voltage does not determine the system accuracy, which has a wider tolerance.
The IR3513Z can accept changes in the MARGIN input while operating and vary the VREF voltage accordingly. The
slew rate of the voltage at the VREF pin can be adjusted by an external capacitor between VREF pin and LGND pin. A
resistor connected in series with this capacitor is required to compensate the VREF buffer amplifier. Margin transitions
result in a smooth analog transition of the VREF voltage and converter output voltage minimizing inrush currents in the
input and output capacitors and overshoot of the output voltage.
Remote Voltage Sensing
VOSEN+ and VOSEN- are used for remote sensing and are connected directly to the load. The remote sense
differential amplifier with high speed, low input offset and low input bias current ensures accurate voltage sensing and
fast transient response.
Start-up Sequence
The IR3513Z has a programmable soft-start function to limit the surge current during the converter start-up. A capacitor
connected between the SS/DEL and LGND pins controls soft start timing, over-current protection delay and hiccup
mode timing. A charge current of 52.5uA (typical) and discharge current of 4.5uA (typical) control the up and down slope
of the voltage at the SS/DEL pin respectively.
Figure 8 shows normal converter start-up. If there is no fault, the SS/DEL pin will start charging. The error amplifier
output EAOUT is clamped low until SS/DEL reaches 1.4V. The error amplifier will then regulate the converter’s output
voltage to match the SS/DEL voltage, less the 1.4V offset, until the converter output reaches the level determined by the
VREF (0.8 V typically) inputs. The SS/DEL voltage continues to increase until it rises above 3.12V and allows the PG
signal to be asserted. SS/DEL finally settles at 3.2V indicating the end of the soft start.
VCCL under voltage lock out, over current, as well as a low signal on the ENABLE input immediately sets the fault latch,
which causes the EAOUT pin to drive low turning off the phase IC drivers. The PG pin also drives low, and SS/DEL
begins to discharge until the voltage reaches 0.2V. If the fault has cleared the fault latch will be reset by the discharge
comparator allowing a normal soft start to occur.
Other fault conditions, such as over voltage, open sense lines, and open daisy chain, set different fault latches, which
start discharging SS/DEL, pull down EAOUT voltage and drive PG low. However, the latches can only be reset by
cycling VCCL power.
If SS/DEL pin is pulled below 0.7V, the converter can be disabled.
Page 17
May 11, 2009
IR3513Z
VCC
ENABLE
0.8V
VREF
3.2V
3.12V
1.4V
SS/DEL
EAOUT
VOUT
PG
SOFT START
TIME
START DELAY
PG DELAY TIME
NORMAL OPERATION
Figure 8 - Start-up sequence
Constant Over-Current Control during Soft Start
The over-current limit threshold is set by a resistor connected between OCSET and VREF pins. If the IIN pin voltage,
which is proportional to the average current plus VREF voltage, exceeds the OCSET voltage during soft start, the
constant over-current control is activated.
Figure 9 shows the constant over-current control with delay during soft start. The delay is required since over-current
conditions can occur as part of normal operation due to inrush current.
If an over-current occurs during soft start (before PG is asserted), the SS/DEL voltage is regulated by the over current
amplifier to limit the output current below the threshold set by OCSET voltage. If the over-current condition persists after
the delay time is reached, the fault latch will be set pulling the error amplifier’s output low and inhibiting switching in the
phase ICs. The SS/DEL capacitor will discharge until it reaches 0.2V and the fault latch is reset allowing a normal soft
start to occur. If an over-current condition is again encountered during the soft start cycle, the constant over-current
control actions will repeat and the converter will be in hiccup mode. The delay time is controlled by a counter, which is
triggered by the oscillator. The counter values vary with switching frequency per phase in order to have a similar delay
time for different switching frequencies.
Over-Current Hiccup Protection after Soft Start
The over current limit threshold is set by a resistor connected between OCSET and VREF pins. Figure 9 shows the
constant over-current control with delay after PG is asserted. The delay is required since over-current conditions can
occur as part of normal operation due to load transients or margin transitions.
If the IIN pin voltage, which is proportional to the average current plus VREF voltage, exceeds the OCSET voltage after
PG is asserted, it will initiate the discharge of the capacitor at SS/DEL. If the over-current condition persists long enough
for the SS/DEL capacitor to discharge below the 120mV offset of the delay comparator, the fault latch will be set pulling
the error amplifier’s output low and inhibiting switching in the phase ICs and de-asserting the PG signal. The output
current is not controlled during the delay time. The SS/DEL capacitor will discharge until it reaches 200 mV and the fault
latch is reset allowing a normal soft start to occur. If an over-current condition is again encountered during the soft start
cycle, the over-current action will repeat and the converter will be in hiccup mode.
Page 18
May 11, 2009
IR3513Z
ENABLE
3.2V
3.12V
3.08V
1.4V
SS/DEL
EA
VOUT
VRRDY
OCP THRESHOLD
IOUT
HICCUP OVER-CURRENT
PROTECTION (OUTPUT
SHORTED)
OVER-CURRENT
PROTECTION
(OUTPUT SHORTED)
NORMAL
START-UP
NORMAL
START-UP
OCP
DELAY
NORMAL
OPERATION
START-UP WITH
OUTPUT SHORTED
POWER-DOWN
(OUTPUT
NORMAL
SHORTED)
OPERATION
Figure 9 - Constant over-current control waveforms during and after soft start
Linear Regulator Output (VCCL)
The IR3513Z has a built-in linear regulator controller, and only an external NPN transistor is needed to create a linear
regulator. The output voltage can be programmed between 4.75V and 7V by the resistor divider at VCCLFB pin. The
regulator output powers the gate drivers of the phase ICs and circuits in the control IC, and the voltage is usually
programmed to optimize the converter efficiency. The linear regulator can be compensated by a 4.7uF capacitor at the
VCCL pin. As with any linear regulator, due to stability reasons, there is an upper limit to the maximum capacitor value
that can be used at this pin and it is a function of the number of phases used in the multiphase architecture and their
switching frequency. Figure 10 shows the stability plots for the linear regulator with 5 phases switching at 750 kHz.
Figure 10 - VCCL regulator stability with 5 phases and PHSOUT equals 750 kHz
Page 19
May 11, 2009
IR3513Z
VCCL Under Voltage Lockout (UVLO)
The IR3513Z IC monitors both the Vcc and VCCL for under voltage condition. During power up, the fault latch will be
reset if VCCL is above 94% (typical) of the voltage set by resistor divider at VCCLFB pin and the VCC exceeds 7.5V
(typical). If VCCL voltage drops below 86% (typical) of the set value or VCC drops below 7V (typical), the fault latch will
be set.
Power Good (PG)
The PG pin is an open-collector output and should be pulled up to a voltage source through a resistor. During soft start,
the PG remains low until the output voltage is in regulation and SS/DEL is above 3.12V. The PG pin becomes low if the
fault latch, over voltage latch, open sense line latch, or open daisy chain latch is set. A high level at the PG pin indicates
that the converter is in operation and has no fault, but does not ensure the output voltage is within the specification.
Output voltage regulation within the design limits can logically be assured however, assuming no component failure in
the system.
Open Voltage Loop Detection
The output voltage range of error amplifier is detected all the time to ensure the voltage loop is in regulation. If any fault
condition forces the error amplifier output above VCCL-0.3V for 8 switching cycles, the fault latch is set. The fault latch
can only be cleared by cycling power to VCCL.
Load Current Indicator Output
The IIN pin voltage represents the average current of the converter plus the VREF voltage. The load current information
can be retrieved by a differential amplifier which subtracts the VREF voltage from the IIN voltage.
Enable Input
Pulling the ENABLE pin below 0.8V sets the Fault Latch and a voltage above 0.85V enables the soft start of the
converter.
Over Voltage Protection (OVP)
Output over-voltage can occur during normal operation if a high side MOSFET short or other failure occurs. The over-
voltage protection comparator monitors the OVSNS pin voltage. If the OVSNS pin voltage exceeds VREF by 85mV, as
shown in Figure 11, the ROSC/OVP pin voltage is driven to V(VCCL) - 1V sending an over voltage signal to the host
system. The ROSC/OVP pin can also be connected to a crowbar circuit, which pulls the converter input low in over
voltage conditions.
The over voltage condition also sets the over voltage fault latch, which pulls the error amplifier output low to turn off the
converter output. At the same time IIN pin (ISHARE of phase ICs) is pulled up to VCCL to communicate the over
voltage condition to phase ICs (if present), as shown in Figure 11. The OVP circuit overrides the normal PWM operation
and will fully turn-on the low side MOSFET within approximately 150ns. The low side MOSFET will remain on until
ISHARE pin voltage drops below V(VCCL) - 800mV, which signals the end of over voltage condition. An over voltage
fault condition is latched in the IR3513Z and can only be cleared by cycling power to VCCL.
In the event of a high side MOSFET short before power up, the OVP flag is activated with as little supply voltage as
possible, as shown in Figure 12. The OVSN pin is compared against a fixed voltage of 1.73V (typical) for OVP
conditions at power-up. The ROSC/OVP pin will be pulled higher than 1.6V with VCCLDRV voltage as low as 1.8V. An
external MOSFET or comparator should be used to disable the silver box, activate a crowbar, or turn off the supply
source. The 1.8V threshold is used to prevent false over-voltage triggering caused by pre-charging of output capacitors.
Page 20
May 11, 2009
IR3513Z
OVP
THRESHOLD
OVSNS
VREF
+ 85mV
VCCL-800 mV
IIN
(ISHARE)
GATEH
GATEL
FAULT
LATCH
ERROR
AMPLIFIER
OUTPUT
VREF
(EAOUT)
AFTER
OVP
NORMAL OPERATION
OVP CONDITION
Figure 11 Over-voltage protection during normal operation
12V
VCCL+0.7V
VCC
VCCL+0.7V
1.8V
VCCLDRV
OVSN
VCCL UVLO
ROSC/OVP
1.6V
Figure 12 - Over-voltage protection during power-up
Page 21
May 11, 2009
IR3513Z
Pre-charging of the converter output voltage may trigger OVP. If the converter output is pre-charged above 1.73V as
shown in Figure 17, ROSC/OVP pin voltage will be higher than 1.6V when VCCLDRV voltage reaches 1.8V.
ROSC/OVP pin voltage will be VCCLDRV-1V and rise with VCCLDRV voltage until VCCL is above UVLO threshold,
after which ROSC/OVP pin voltage will be VCCL-1V. The converter cannot start unless the over voltage condition stops
and VCCL is cycled. If the converter output is pre-charged 130mV above VREF but lower than 1.73V, as shown in
Figure 17, the converter will soft start until SS/DEL voltage is above 3.92V (4.0V-0.08V). Then, over voltage comparator
is activated and fault latch is set.
12V
VCCL+0.7V
VCC
VCCL+0.7V
VCCLDRV
1.8V
OUTPUT
VOLTAGE
(VOSEN+)
1.73V
VCCL UVLO
ROSC/OVP
1.6V
Figure 13 - Over-voltage protection with pre-charging converter output Vo > 1.73V
Figure 14 - Over-voltage protection with pre-charging converter output VREF + 0.13V <Vo < 1.73V
Page 22
May 11, 2009
IR3513Z
During a MARGIN up to a MARGIN down event (80mV excursion on VREF), OVP may be triggered since the OVP
threshold is a fixed 85mV above VREF. This can occur due to large output capacitance and light/no load operation
where the output voltage remains high while the OVP threshold falls.
The overall system must be considered when designing for OVP. In many cases the over-current protection of the AC-
DC or DC-DC converter supplying the multiphase converter will be triggered and provide effective protection without
damage as long as all PCB traces and components are sized to handle the worst-case maximum current. If this is not
possible, a fuse can be added in the input supply to the multiphase converter.
Error Amplifier Head Room Control
In high converter output voltage applications, there may not be enough head room in error amplifier and current sense
amplifiers of phase ICs when VCC is just above UVLO start and stop thresholds. A head room control circuit is
implemented to ensure V(VCC) – V(VO) > 2.5V by sourcing extra current to the resistor connecting to FB pin. When this
circuit is activated, the converter voltage is lower than the required and therefore the PG is also driven low.
Open Remote Sense Line Protection
If either remote sense line VOSEN+ or VOSEN- or both is open, the output of remote sense amplifier (VOUT) drops.
The IR3513Z monitors VO pin voltage continuously. If VOUT voltage is lower than 200 mV, two separate pulse currents
are applied to VOSEN+ and VOSEN- pins respectively to check if the sense lines are open. If VOSEN+ is open, a
voltage higher than 90% of V(VCCL) will be present at VOSEN+ pin and the output of open line detect comparator will
be high. If VOSEN- is open, a voltage higher than 400mV will be present at VOSEN- pin and the output of open line
detect comparator will be high. The open sense line fault latch is set, which pulls error amplifier output low immediately
and shut down the converter. SS/DEL voltage is discharged, and the fault latch can only be reset by cycling VCCL
power.
Open Daisy Chain Protection
IR3513Z checks the daisy chain every time it powers up. It starts a daisy chain pulse on the PHSOUT pin and detects
the feedback at PHSIN pin. If no pulse comes back after 30 CLKOUT pulses, the pulse is restarted again. If the pulse
fails to come back the second time, the open daisy chain fault is registered, and SS/DEL is not allowed to charge. The
fault latch can only be reset by cycling the power to VCCL.
After powering up, the IR3513Z monitors PHSIN pin for a phase input pulse equal or less than the number of phases
detected. If PHSIN pulse does not return within the number of phases in the converter, another pulse is started on
PHSOUT pin. If the second started PHSOUT pulse does not return on PHSIN, an open daisy chain fault is registered.
Phase Number Determination
After a daisy chain pulse is started, the IR3513Z checks the timing of the input pulse at PHSIN pin to determine the
phase number.
Output Voltage Under-voltage Monitoring
The IR3513Z compares the FB pin to a voltage, V, equal to 0.897×Vref. If the FB pin is 50mV (typical) below the
aforementioned V, the output voltage under-voltage monitor will trigger, pulling the PG pin low. The output voltage
under-voltage monitor does not effect switching of the phases or soft start.
Page 23
May 11, 2009
IR3513Z
Fault Table
The Fault Table below describes the different faults that can occur and how IR3513Z would react to protect the supply
and the load from possible damage. The fault types that can occur are listed in row 1. Row 2 has the method that a fault
is cleared. The first 4 faults are latched in the UV fault latch and the VCCL power has to be recycled by switching off the
input and switching it back on for the converter to work again. The rest of the faults (except for UVLO Vout) are latched
in the SS fault latch and do not need to recycle the VCCL power in order for IR3513Z to resume operation. IR3513Z will
automatically resume operation when these fault conditions no longer apply in the system. Most of the faults disable the
error amplifier (EA) and discharge the soft start capacitor. All the faults flag PGood. PGood returns back to high when
the faults are cleared. The delay row shows how long it takes IR3513Z to react after detecting a fault condition. Delays
are provided to minimize the possibility of nuisance faults.
Fault table
Fault Type
Disable
Open
Daisy
Open
Control
Loop
Open
Sense
Line
Over
Voltage
VCC
UVLO UVLO
VCCL
OC
Before
Start-up
OC After
Start-up
VOUT
UVLO
Fault
Clearing
Method
Recycle VCCL
Resume Normal Operation when Condition Clears
Error Amp
Disabled
ROSC/OVP
& IIN drive
high until
OV clears
SS/DEL
Discharge
Flags
PGood
Delay?
Yes
Yes
No
No
Yes
No
No
No
Yes
PHSOUT
Pulses.
Count
8
30
Clock
Pulses
No
No
250 ns
Blank
Time
No
SS/DEL
Discharge
PHSOUT
Pulses
Programm Threshold
ed by
ROSC
value
Page 24
May 11, 2009
IR3513Z
APPLICATIONS INFORMATION
Figure 15 - Scalable Master (IR3513Z) & Slave (IR3505Z) POL modules with programmable output voltage and
redundant OVP sense
Page 25
May 11, 2009
IR3513Z
DESIGN PROCEDURES
IR3513Z EXTERNAL COMPONENTS
Oscillator Resistor Rosc
The oscillator of IR3513Z generates square-wave pulses to synchronize the phase ICs. The switching frequency of
the each phase converter equals the PHSOUT frequency, which is set by the external resistor ROSC according to the
curve in Figure 16. The CLKOUT frequency equals the switching frequency multiplied by the phase number.
IR3513 Frequency vs. ROSC Resistor
55
50
45
40
35
RROSC
30
Nominal Spec
25
20
15
10
5
200
300
400
500
600
700
800
900
1000 1100 1200 1300 1400 1500 1600
Frequency (KHz)
Figure 16 Operational Frequency vs Rosc Resistor
Soft Start Capacitor CSS/DEL
The CSS/DEL capacitor programs four different time parameters, i.e. soft start delay time, soft start time, VR ready
delay time and over-current fault latch delay time after VR ready. These parameters can be calculated with the
following equations:
C
SS / DEL *1.4
CSS / DEL *1.4
52.5*10−6
(1)
(2)
(3)
Tssdelay
=
=
ICHG
C
SS / DEL *Vref
CSS / DEL *0.8
52.5*10−6
Tss =
=
ICHG
CSS / DEL *(3.12 −Vref ) CSS / DEL *2.32
TPG _ delay
=
=
=
52.5*10−6
ICHG
CSS / DEL *120*10−3
CSS / DEL *120*10−3
(4)
TOC _ delay
=
.
52.5*10−6
ICHG
Page 26
May 11, 2009
IR3513Z
Over Current Setting Resistor ROCSET
The inductor DC resistance is utilized to sense the inductor current. The copper wire of the inductor has a constant
temperature coefficient of 3850 ppm/°C, and therefore the maximum inductor DCR can be calculated from (5).
RL_MAX and RL_ROOM are the inductor DCR value at maximum temperature (TL_MAX) and room temperature
(T_ROOM), respectively.
RL _ MAX = RL _ ROOM ∗[1 + 3850 *10−6 ∗ (TL _ MAX − TROOM )]
(5)
The total input offset voltage (VCS_TOFST) of current sense amplifier in phase ICs is the sum of input offset (VCS_OFST)
of the amplifier itself and that created by the amplifier input bias current flowing through the current sense resistor
RCS.
VCS _ TOFST = VCS _ OFST + ICSIN + ∗ RCS
(6)
The over-current limit is set by the external resistor, ROCSET, as defined in (7), where ILIMIT is the required over current
limit. IOCSET, the bias current of OCSET pin, changes with switching frequency set by resistor ROSC and is determined
by equation (9). GCS is the gain of the current sense amplifier. In a multiphase architecture the peak to peak ripple of
the net inductor current is much smaller than the stand alone phase due to interleaving. The ratio of the peak to
average current in this case can be approximated using (8).
ILIMIT
ROCSET = [
∗ RL _ MAX ∗(1+ KP ) +VCS _ TOFST ]∗GCS / IOCSET
(7)
n
m
m +1
n
⎡
⎤
VI ⋅ D ⋅(1− D)⋅ n ⋅(D − )⋅(
− D)
⎢
⎥
⎦
n
⎣
(8)
(9)
KP =
(
ILIMIT / n ⋅ L ⋅ fsw ⋅ 2⋅ D ⋅(1− D)
)
600
Iocset =
Rosc(KΩ)
Where
ILIMIT=Maximum over current limit
n=Number of phases
KP=Ratio of the peak to average current for the inductor
GCS=Gain of the current sense amplifier
IOCSET= Determined by the ROSC and given (9)
D=Vo/VI
m=Maximum integer that doesn’t exceed (n*D)
Vout Programming Resistor RFB1 and RFB3
The Feedback pin (FB) is connected to an external resistor divider to set the output voltage. The error amplifier has a
0.8 V reference (Typical) and the output voltage is determined by selecting resistor divider values (See Figure 1).
RFB1 *0.8
RFB3
=
(10)
Vout − 0.8
Page 27
May 11, 2009
IR3513Z
VCCL Programming Resistor RVCCLFB1 and RVCCLFB2
Since VCCL voltage is proportional to the MOSFET gate driver loss and inversely proportional to the MOSFET
conduction loss, the optimum voltage should be chosen to maximize the converter efficiency. VCCL linear
regulator consists of an external NPN transistor, a ceramic capacitor and a programmable resistor divider. Pre-
select RVCCLFB1, and calculate RVCCLFB2 from (11).
RVCCLFB1 *1.19
RVCCLFB2
=
(11)
VCCL −1.19
VCCL Capacitor CVCCL
The capacitor is selected based on the stability requirement of the linear regulator and the load current to be driven.
The linear regulator supplies the bias and gate drive current of the phase ICs. A 4.7uF normally ensures stable VCCL
performance for most applications.
VCCL Regulator Drive Resistor RVCCLDRV
The drive resistor is primarily dependent on the load current requirement of the linear regulator and the minimum
input voltage requirements. The following equation gives an estimate of the average load current of the switching
phase ICs.
(12)
Idrive _ avg = (Qgb + Qgt ) ⋅ n + IVCCL _ PHS ⋅ (n − 1) + IVCCL _ C
Qgb and Qgt are the gate charge of the top and bottom FET, IVCCL_PHS is the VCCL current of the phase IC-s,
IVCCL_C is the VCCL current of the controller and n is the number of phases. For a minimum input voltage and a
maximum VCCL, the maximum RVCCLDRV required to use the full pull-down current of the VCCL driver is given by
VI (min) − 0.7 −VCCL(max)
(13)
RVCCLDRV
=
Idrive _ avg / βmin
Due to limited pull down capability of the VCCLDRV pin, make sure the following condition is satisfied.
VI (max) − 0.7 −VCCL(min)
(14)
< 10mA
RVCCLDRV
In the above equation, VI( min) and VI( max) is the minimum and maximum anticipated input voltage. If the above
condition is not satisfied there is a need to use a device with higher βmin or Darlington configuration can be used
instead of a single NPN transistor.
Inductor Current Sensing Capacitor CCS and Resistor RCS
The DC resistance of the inductor is utilized to sense the inductor current. Usually the resistor RCS and capacitor CCS
in parallel with the inductor are chosen to match the time constant of the inductor, and therefore the voltage across
the capacitor CCS represents the inductor current. If the two time constants are not the same, the AC component of
the capacitor voltage is different from that of the real inductor current. The time constant mismatch does not affect the
average current sharing among the multiple phases, but affects the current signal ISHARE.
Measure the inductance L and the inductor DC resistance RL. Pre-select the capacitor CCS and calculate RCS as
follows.
L RL
(15)
RCS
=
CCS
Page 28
May 11, 2009
IR3513Z
Bootstrap Capacitor CBST
Depending on the duty cycle and gate drive current of the phase IC, a capacitor in the range of 0.1uF to 1uF is
needed for the bootstrap circuit.
Decoupling Capacitors for Phase IC
0.1uF-1uF decoupling capacitors are required at VCC and VCCL pins of phase ICs.
Over-voltage Resistors ROV1 and ROV2
The over-voltage resistors are used to set the voltage at the OVSNS pin. If the voltage of the OVSNS pin exceeds
VREF by 85mV then the over-voltage protection will be activated and the error amplifier voltage will be pulled down
turning the converter off. The over-voltage fault is latched, which means that the power to the converter has to be
recycled for the fault to clear. Choose VOVSNS a certain value ∆V below VREF. VREF is typically 0.8 V. The over-
voltage threshold will then be ∆V+85mV. Select ROV1. ROV2 is calculated based on (16).
VOVSNS * ROV1
ROV 2
=
(16)
VOUT −VOVSNS
VREF Slew Rate Programming Capacitor CVREF and Resistor RVREF
The slew rate of MARGIN down-slope can be programmed by the external capacitor CVREF as defined in (17), where
ISINK is the sink current of the VREF pin. The slew rate of MARGIN up-slope is the same as that of down-slope. The
resistor RVREF is used to compensate the VREF circuit and can be calculated as shown in (18).
132*10−6
ISINK
CVREF
=
=
(17)
(18)
SRMARGIN
SRMARGIN
3.2 ∗10−15
RVREF = 0.5 +
2
CVREF
Type III Compensation
Choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase, the desired phase
margin θc and Rfb1 (see Figure 17). Determine the component values based on the equations below. wc is 2*π*fc
(the crossover angular frequency), Le is the equivalent inductance of the converter, C is the output capacitance, Rst is
the total equivalent resistance in series with the inductor, Rc is the output capacitance ESR and R is the load
resistance.
1
(19)
Ccp =
K ⋅ Rfb1
1
(20)
Rcp =
Ccp ⋅ wz1
1
(21)
Cfb =
wz2 ⋅ Rfb1
1
(22)
Ccp1 =
wp2 ⋅ Rcp
Page 29
May 11, 2009
IR3513Z
1
(23)
Rfb2 =
wp1⋅Cfb
where,
wc
wz1 =
(24)
(25)
10
1− sin(θc)
1+ sin(θc)
wz2 = wc ⋅
wp1 = wc ⋅
1+ sin(θc)
1− sin(θc)
(26)
(27)
(28)
wp2 = 1.4 ⋅ wp1
(wc4 ⋅t42 + wc2 ⋅t22 )((1− b ⋅ wc2 )2 + a2 ⋅ wc2 )(R + Rst)
K =
Gpwm ⋅ H ⋅t5 ⋅t6 ⋅ R
where Gpwm is the gain of the PWM generator, H is the gain of the feedback filter and
Le + C(R ⋅ Rst + R ⋅ Rc + Rst ⋅ Rc)
a =
(29)
(30)
R + Rst
R + Rc
R + Rst
wc2
b = Le ⋅C
(31)
(32)
t1 = 1−
wz1⋅ wz2
wc2
t2 = 1−
wp1⋅ wp2
1
1
(33)
(34)
t3 =
+
wz1 wz2
1
1
t4 =
+
wp1 wp2
t5 = (1− b ⋅ wc2 + wc2 ⋅ Rc ⋅C ⋅ a)2 + wc2 (Rc ⋅C(1− b ⋅ wc2 ) − a)2 (35)
t6 = wc4 (t2 ⋅t3 − t1 ⋅t4 )2 + wc2 (t1 ⋅t2 + wc2 ⋅t3 ⋅t4 )2
(36)
Page 30
May 11, 2009
IR3513Z
Ccp1
Cf b
Ccp
Rfb2
Rcp
Rfb1
Vout
-
2
3
EAout
1
+
Rf b3
Vref
Figure 17 Voltage Loop Compensation Network
Page 31
May 11, 2009
IR3513Z
LAYOUT GUIDELINES
The following layout guidelines are recommended to reduce the parasitic inductance and resistance of the PCB
layout, therefore minimizing the noise coupled to the IC.
• Dedicate at least one middle layer for a ground plane.
• Separate analog bus (EAIN, DACIN and ISHARE) from digital bus (CLKIN, PHSIN, and PHSOUT) to reduce
the noise coupling.
• Connect PGND to LGND pins to the ground plane through vias
• Place current sense resistors and capacitors (RCS and CCS) close to IC. Use Kelvin connection for the inductor
current sense wires, but separate the two wires by ground polygon. The wire from the inductor terminal to
CSIN- should not cross over the fast transition nodes, i.e. switching nodes, gate drive outputs and bootstrap
nodes.
• Place the IC, gate drive side as close as possible to the MOSFETs to reduce the parasitic resistance and
inductance of the gate drive paths.
• Place the input ceramic capacitors close to the drain of top MOSFET and the source of bottom MOSFET.
•
•
Page 32
May 11, 2009
IR3513Z
PCB Metal and Component Placement
• Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be ≥
0.2mm to minimize shorting.
• Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension + 0.05mm
inboard extension. The outboard extension ensures a large and inspectable toe fillet, and the inboard
extension will accommodate any part misalignment and ensure a fillet.
• Center pad land length and width should be equal to maximum part pad length and width. However, the
minimum metal to metal spacing should be ≥ 0.17mm for 2 oz. Copper (≥ 0.1mm for 1 oz. Copper and ≥
0.23mm for 3 oz. Copper)
• Four 0.30mm diameter vias shall be placed in the center of the pad land and connected to ground to
minimize the noise effect on the IC.
• No PCB traces should be routed nor vias placed under any of the 4 corners of the IC package. Doing so can
cause the IC to rise up from the PCB resulting in poor solder joints to the IC leads.
Page 33
May 11, 2009
IR3513Z
Solder Resist
• The solder resist should be pulled away from the metal lead lands by a minimum of 0.06mm. The solder
resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all Non Solder
Mask Defined (NSMD). Therefore pulling the S/R 0.06mm will always ensure NSMD pads.
• The minimum solder resist width is 0.13mm.
• At the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a
fillet so a solder resist width of ≥ 0.17mm remains.
• The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist onto the
copper of 0.06mm to accommodate solder resist mis-alignment. In 0.5mm pitch cases it is allowable to have
the solder resist opening for the land pad to be smaller than the part pad.
• Ensure that the solder resist in-between the lead lands and the pad land is ≥ 0.15mm due to the high aspect
ratio of the solder resist strip separating the lead lands from the pad land.
• The four vias in the land pad should be tented or plugged from bottom board side with solder resist.
Page 34
May 11, 2009
IR3513Z
Stencil Design
• The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands.
Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch
devices the leads are only 0.25mm wide, the stencil apertures should not be made narrower; openings in
stencils < 0.25mm wide are difficult to maintain repeatable solder release.
• The stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead
land.
• The land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately
50% area of solder on the center pad. If too much solder is deposited on the center pad the part will float
and the lead lands will be open.
• The maximum length and width of the land pad stencil aperture should be equal to the solder resist opening
minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands
when the part is pushed into the solder paste.
Page 35
May 11, 2009
IR3513Z
APPLICATIONS PACKAGE INFORMATION
32L MLPQ (5 x 5 mm Body) – θJA = 22.4 oC/W, θJC = 0.86 oC/W
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. www.irf.com
www.irf.com
Page 36
May 11, 2009
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