IR3725MTRPBF [INFINEON]
INPUT POWER MONITOR WITH DIGITAL INTERFACE; 带有数字接口的输入电源监视器
| 型号： | IR3725MTRPBF |
| 厂家： | 
Infineon |
| 描述： | INPUT POWER MONITOR WITH DIGITAL INTERFACE |
| 文件： | 总19页 (文件大小：768K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IR3725
Data Sheet
INPUT POWER MONITOR
WITH DIGITAL INTERFACE
FEATURES
DESCRIPTION
Accurate power, current, or voltage reporting
1.5 % maximum power error
1.0 % maximum current error
Serial digital interface
The IR3725 is a highly configurable power monitor IC
that uses proprietary digital technology to measure a
12V rail current, its voltage, or its average power over a
user specified time interval. Configuration and result
reporting are managed through a serial digital interface.
The current is measured as a voltage across a shunt
resistance, an input inductor, or a copper trace
resistance.
SMBus and I2C compatible
Programmable averaging interval
Flexible current sensing
Resistive or Inductor DCR
Applications
Synchronous rectified buck converters
Multiphase converters
12pin 3x4 DFN lead free
RoHS Compliant
The real time voltage and current signals are multiplied,
digitized, and averaged over a user selectable
averaging interval providing TruePower™ measurement
of highly dynamic loads.
TYPICAL APPLICATION CIRCUIT
Input
Capacitors
3.3V
+12V
Buck Regulators
L
DCR
CCS1
CCS2
To system
Controller
VDD
IR3725
I2C
2
ALERT#
VO
VT
VCS2
VCS1
ADDR
RT
0.1 uF
GND
+12V Return
ORDERING INFORMATION
Device
Package
Order Quantity
IR3725MTRPBF
IR3725MPBF
12 lead DFN (4x3 mm body)
12 lead DFN (4x3 mm body)
3000 piece reel
Sample Quantity
Page 1 of 19
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2008_12_09
IR3725
Data Sheet
ABSOLUTE MAXIMUM RATINGS
All voltages referenced to GND
Operating Junction Temperature.... -10°C to 150oC
Storage Temperature Range.......... -65oC to 150oC
Thermal Impedance (θJC)..........................1.6 °C/W
Thermal Impedance (θJA)...........................30 °C/W
ESD Rating ......... HBM Class 1C JEDEC Standard
MSL Rating ..................................................Level 2
Reflow Temperature ..................................... 260°C
VDD: ................................................................3.9V
ALERT#:...........................................................3.9V
ALERT#.............................................< VDD + 0.3V
VCS1, VCS2, VO...........................................25.0V
All other Analog and Digital pins......................3.9V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ELECTRICAL SPECIFICATIONS Unless otherwise specified, these specifications apply:
VDD = 3.3V ± 5%, 0oC ≤ TJ ≤ 125oC, 8V ≤ VO ≤ 23.5V, and operation in the typical application circuit. See notes
following table.
PARAMETER
BIAS SUPPLY
TEST CONDITION
NOTE
MIN
TYP
MAX
UNIT
VDD Turn-on Threshold, VDDUP
VDD Turn-off Threshold, VDDDN
VDD UVLO Hysteresis
VDD Operating Current
VDD Shutdown Current
VOLTAGE REFERENCE
VT Voltage
3.1
V
V
2.4
75
mV
μA
μA
RT = 25.5 kΩ
700
18
1000
100
Config Reg enable bit d4=1
RT = 25.5 kΩ
1.40
20
1.50
25.5
1.60
45.3
V
Reference load, RT
1
kꢀ
VOLTAGE SENSOR
Voltage, full scale, VFS
CURRENT SENSOR
23.5
1.48
V
V
Voltage, Current Gain, VIG
DIGITIZER
RT = 25.5 kꢀ
Internal Sampling frequency
External Sampling frequency
POWER INFORMATION
Minimum Averaging Interval
Maximum Averaging Interval
Driven from internal clock
Driven from external clock
512
kHz
kHz
922
1024
1126
Config Reg [d3..d0] = b‘0000
Config Reg [d3..d0] = b‘1000
1
1
0.85
217
1
1.15
295
ms
ms
256
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IR3725
Data Sheet
PARAMETER
ACCURACY
TEST CONDITION
NOTE
MIN
TYP
MAX
UNIT
VO=12V, DCR voltage = 75 mV,
RT=25.5kꢀ, RCS1=RCS2=1.5kꢀ
2
Power measurement error
Voltage measurement error
1, 2
%
Tj = 0 - 85 °C
1.5
1.5
1.3
1.6
1.0
VO=12 V, DCR voltage = 75mV,
RT=25.5kꢀ, RCS1=RCS2=1.5kꢀ
1, 2
1, 2
%
%
Tj = 0 – 85 °C
VO=12V, DCR voltage = 75 mV,
RT=25.5kꢀ, RCS1=RCS2=1.5kꢀ
Current measurement error
Tj = 0 – 85 °C
NOTES:
1.
2.
Guaranteed by design, not tested in production
Assumes no error contributed by external components
BLOCK DIAGRAM
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IR3725
Data Sheet
PIN DESCRIPTION
NAME
NUMBER I/O LEVEL DESCRIPTION
VCS1
VCS2
VO
1
2
Analog 12V Current sensing input 1
Analog 12V Current sensing input 2
Analog 12V Voltage sensing input
3
VT
4
Analog
0V
Thermistor sensing input
IC bias supply and signal ground
3.3V bias supply
GND
VDD
5
6
3.3V
EXTCLK
ADDR
SCL
7
3.3V Digital Input for optional external clock
3.3V Digital Bus Address selection input
3.3V Digital Bus Clock; Input only
8
9
SDA
10
11
12
3.3V Digital Bus Data; Input / Open drain output
ALERT#
NC
3.3V Digital Programmable output function; Open drain output clamped to VDD
Do not connect
IC PIN FUNCTIONS
VDD PIN
VT FUNCTION
This pin provides operational bias current to circuits
internal to the IR3725. Bypass it with a high quality
ceramic capacitor to the GND pin.
A voltage internal to the IR3725 drives the VT pin
while the pin current is monitored and used to set the
amplitude of the switched current source IT. This pin
should be connected to GND through a precision
resistor network RT. This network may include
provision for canceling the positive temperature
coefficient of the inductor’s DC resistance (DCR).
GND PIN
This pin returns operational bias current to its source.
It is also the reference to which the voltage VO is
measured, and it sinks the reference current
established by the external resistor RT.
ALERT# FUNCTION
The ALERT# pin is a multi-use pin. During normal
use it can be configured via the serial bus as an open
drain ALERT# pin that will be driven logic low when
new data is available in the output register. After the
output register has been read via the serial bus the
ALERT# will be released to its high resistance state.
This pin can also be programmed to pull low when
the output exceeds the programmable level.
VO PIN
This pin is to be electrically connected to the location
in the circuit where voltage for the power calculation
is desired to be monitored. Power accuracy may be
degraded if the voltage at this pin is below VOmin
.
VCS1 AND VCS2 PINS
The average current into these pins is used to
calculate power. Current sources internal to the
IR3725 will null the average voltage between this pin
pair.
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IR3725
Data Sheet
ADDR PIN
SCL
The ADDR pin is an input that establishes the serial
bus address. Valid addresses are selected by
grounding, floating, or wiring to VDD the ADDR pin.
Table 1, “User Selectable Addresses”, provides a
mapping of possible selections. Bypass this pin to
GND with a high quality ceramic capacitor when
floated.
SCL is the serial bus clock and is capable of
functioning with a rate as low as 10 kHz. It will
continue to function as the rate is increased to 400
kHz. This device is considered a slave, and therefore
uses the SCL as an input only.
SDA
SDA is monitored as data input during master to
slave transactions, and is driven as data output
during slave to master transactions as indicated in
the Packet Protocol section to follow.
Table 1 User selectable addresses
ADDR pin configuration
Bus Address
b’1110 000
b’1110 010
b’1110 110
Low
Open
High
EXTCLK
This pin is a Schmitt trigger input for an optional
externally provided square wave clock. The duty ratio
of this externally provided clock, if used, shall be
between 40% and 60%. If no external clock is
connected, the internal clock will be used. Connect
this pin to GND if no external clock is used.
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IR3725
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
(One device tested using “Resistor Sensing Circuit”, VDD = 3.3 V, CCS2 = 10 u F, RT = 25.5 k ꢀ, 90 mV full scale
uses RCS1 = RCS2 = 1.5 k ꢀ, 25 mV full scale uses RCS1 = RCS2 = 432 ꢀ, 9 mV full scale uses RCS1 = RCS2 = 150 ꢀ.
Each data point is average of eight samples.)
IR3725 PowerMode - Transfer Function (90 mV VDCR full scale)
IR3725 PowerMode - Error [%] (90 mV VDCR full scale)
20%
250
200
150
100
50
18%
16%
14%
12%
10%
8%
Vo = 7 V
Vo = 12 V
Vo = 20 V
Vo = 7 V
Vo = 12 V
Vo = 20 V
6%
4%
2%
0%
0
0.00
0.02
0.04
0.06
0.08
0.00
0.02
0.04
0.06
0.08
V
DCR [V]
VDCR [V]
IR3725 PowerMode - Error [%] (9 mV VDCR full scale)
IR3725 PowerMode - Error [%] (25 mV VDCR full scale)
20%
18%
16%
14%
12%
10%
8%
20%
18%
16%
14%
12%
10%
8%
Vo = 7 V
Vo = 12 V
Vo = 20 V
Vo = 7 V
Vo = 12 V
Vo = 20 V
6%
6%
4%
4%
2%
2%
0%
0%
0.000
0.005
0.010
0.015
0.020
0.025
0.000 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008
VDCR [V]
V
DCR [V]
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IR3725
Data Sheet
IR3725 CurrentMode - Error [%] (25 mV VDCR full scale)
IR3725 CurrentMode - Error [%] (90 mV VDCR full scale)
20%
20%
18%
16%
14%
12%
10%
8%
18%
16%
14%
12%
10%
8%
Vo = 7 V
Vo = 12 V
Vo = 20 V
Vo = 7 V
Vo = 12 V
Vo = 20 V
6%
6%
4%
4%
2%
2%
0%
0%
0.00
0.02
0.04
DCR [V]
0.06
0.08
0.000
0.005
0.010
0.015
0.020
0.025
V
VDCR [V]
IR3725 CurrentMode - Error [%]
IR3725 CurrentMode - Error [%] (9 mV VDCR full scale)
20%
14%
12%
10%
8%
18%
16%
14%
12%
10%
8%
Vo = 7 V
Vo = 12 V
Vo = 20 V
90 mV FS
25 mV FS
9 mV FS
6%
4%
6%
2%
4%
0%
2%
-2%
0%
0.000
0.010
0.020
DCR [V]
0.030
0.040
0.000
0.002
0.004
0.006
0.008
V
VDCR [V]
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IR3725
Data Sheet
FUNCTIONAL DESCRIPTION
Please refer to the Functional Description Diagram
below. Power flow through the inductor is the product
of output voltage VO times the inductor current IL. An
average voltage VDCR will be developed across the
inductor as a result of current flow IL. This voltage will
result in a net current flow imbalance into the VCS
pins that is equal to VDCR / (Rcs1 + Rcs2). A voltage
nulling circuit inside the IC sinks enough current to
equalize the voltages of Vcs1 and Vcs2. The current
required to balance the voltages of these two nodes
is reported as a fraction of the current VIG / RT using
256 as the denominator. Current will be reported as
an integer number of counts in two’s compliment
binary format with a range of -256 to 256. Positive
values will be reported when current flow is in the
direction of the current flow arrow in the diagram
below.
The voltage is reported as a positive integer number
of counts equal to (voltage * 256) / VFS. VFS is defined
in the ELECTRICAL SPECIFICATIONS.
Power is reported as an integer number of counts in
two’s compliment binary format with a range of -256
to 256. Positive values will be reported when current
flow is in the direction of the current flow arrow in the
diagram below. Power expressed in counts will be
(power * 256) / (IFS * VFS) where IFS equals VIG*(Rcs1
+ Rcs2) / (RT*DCR). The full scale power PFS is the
product of full-scale voltage and full scale current.
IL
12V in
L
DCR
RCS1A
RCS2A
RCS1B
RCS2B
CCS1
CCS2
VCS1
VDD
VCS2
VO
SDA
SCL
IR3725
ALERT#
ADDR
EXTCLK
VT
Rs
RT
GND
Rth
Rp
Figure 1 Functional Description Diagram
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IR3725
Data Sheet
RESISTOR CURRENT SENSING APPLICATION
The voltage on the shunt resistor of the circuit below
is directly proportional to the current from the source.
Shunts developing 5 mV to 75 mV at IFS have been
used. Accuracy is enhanced at the higher voltage.
Select RT to be a 25.5 kꢀ 1% or better initial
tolerance resistor. Sinking current capability of VCS1
or VCS2 is VIG / RT.
Chose RCS1 and RCS2 such that this current through
either of them develops the same voltage that is
developed by the shunt at full scale current.
C
CS2 is the integrator capacitor and should have a
ceramic dielectric with a value between 0.1 μF and
10 μF.
SHUNT
12 V Power
Source
RCS1
RCS2
CCS2
VDD
VDD
VCS2
VCS1
VO
VDD
SDA
Bypass
Cap
IR3725
VT
SCL
ALERT#
ADDR
RT
GND
Figure 2 Resistor Sensing Circuit
Page 9 of 19
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IR3725
Data Sheet
INDUCTOR DCR CURRENT SENSING APPLICATION
Referring to the Functional Description Diagram, it
can be seen that the shunt function can be
accomplished by the DC resistance of the inductor
that is already present. Omitting the resistive shunt
reduces BOM cost and increases efficiency. In
exchange for these two significant advantages two
easily compensated design complications are
introduced, a time constant and a temperature
coefficient.
The inductor voltage sensed between the Rcs1
resistors is not simply proportional to the inductor
current, but rather is expressed in the Laplace
equation below.
A second equation is used to set the full-scale
inductor current.
VIG
RT
RCS1 + RCS2
)
. Let
IFS
=
⋅
DCR
RCS1 +RCS2 = Rsum and solve for Rsum.
Select a standard value CCS1 that is larger than
4 ⋅L
DCR ⋅Rsum
. Solve for Req.
We now know Req and Rsum, but we do not know
the individual resistor values RCS1 or RCS2. The next
step is to solve for them simultaneously. By
substituting Rsum into the Req equation the following
can be written:
L
⎛
⎞
⎟
V = Ι ⋅DCR 1+ s
⎜
L
L
DCR
⎝
⎠
This inductor time constant is canceled when
RCS1 ⋅RCS2
Req
=
, which can then be rearranged to
L
RCS1 ⋅RCS2
RCS1 +RCS2
Rsum
= 2⋅
⋅CCS1 .
DCR
RC2S1 −RCS1 ⋅Rsum +Req ⋅Rsum = 0 .
RCS1 ⋅RCS2
RCS1 +RCS2
Let
= Req .
Note that this equation is of the form
ax2 + bx + c = 0 where a=1, b=-Rsum, and
c=Req•Rsum. The roots of this quadratic equation
will be RCS1 and RCS2. Use the higher value resistor
as RCS1 in order to minimize ripple current in CCS1
.
Req
1+ 1− 4 ⋅
RSUM
RCS1 = RSUM
⋅
2
Req
1− 1− 4⋅
RSUM
RCS2 = RSUM
⋅
2
Page 10 of 19
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IR3725
Data Sheet
THERMAL COMPENSATION FOR INDUCTOR DCR CURRENT
SENSING
⎛
⎜
⎞
⎟
⎟
⎠
The positive temperature coefficient of the inductor
DCR can be compensated if RT varies inversely
proportional to the DCR. DCR of a copper coil, as a
function of temperature, is approximated by
⎛
⎞
⎟
⎟
⎠
1
1
⎜
β⋅
−
⎜
Rth (T) = Rth (T0 ) ⋅ e⎝⎜
(2)
T
T0
⎝
where Rth(T) is the thermistor resistance at some
DCR(T) = DCR(TR ) ⋅ (1+ (T −TR ) ⋅TCRCu ) .
(1)
temperature T, Rth(T0) is the thermistor resistance at
the reference temperature T0, and β is the material
constant provided by the thermistor manufacturer.
Kelvin degrees are used in the exponential term of
equation 2. If RS is large and RP is small, the
curvature of the equivalent network resistance can be
reduced from the curvature of the thermistor alone.
Although the exponential equation 2 can never
compensate linear equation 1 at all temperatures, a
spreadsheet can be constructed to minimize error
over the temperature interval of interest. The
resistance RT of the network shown as a function of
temperature is
TR is some reference temperature, usually 25 °C, and
TCRCu is the resistive temperature coefficient of
copper, usually assumed to be 0.39 %/°C near room
temperature. Note that equation 1 is linearly
increasing with temperature and has an offset of
DCR(TR) at the reference temperature.
If RT incorporates a negative temperature coefficient
thermistor then temperature effects of DCR can be
minimized. Consider a circuit of two resistors and a
thermistor as shown in the RT network below.
1
RT (T) = Rs +
(3)
1
1
Rs
+
Rp Rth (T)
using Rth(T) from equation 2.
Equation 4 may be written as a function of
temperature using equations 1 and 3 as follows:
Rp
Rth
VIG
(
RCS1 + RCS2
DCR(T)
)
.
(4)
IFS (T) =
⋅
RT (T)
Figure 3 RT Network
If Rth is an NTC thermistor then the resistance of the
network will decrease as temperature increases.
Unfortunately, most thermistors exhibit far more
variation with temperature than copper wire. One
equation used to model thermistors is
With Rs and Rp as additional free variables, use a
spreadsheet to solve equation 4 for the desired full
scale current while minimizing the IFS(T) variation
over temperature.
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IR3725
Data Sheet
ERROR MANAGEMENT
Component value errors external to the IR3725
contribute to power and current measurement error.
The power reported by the IR3725 is a function not
only of actual power or current, but also of products
and quotients of RT, RCS1, RCS2, DCR (or RSHUNT), as
well as parameters internal to the IR3725. The
tolerance of these components increases the total
power or current error. Small signal resistors are
typically available in 1% tolerance, but 0.1% parts are
available. Shunts are also available at 1% or 0.1%
tolerance. The DCR tolerance of inductors can be
5%, but 3% are available. Fortunately, it is not typical
that worst-case errors would systematically stack in
one direction. It is statistically likely that a high going
value would be paired with a low going value to
somewhat cancel the error. Because of this,
Quantization error occurs in digital systems because
the full scale is partitioned into a finite number of
intervals and the number of the interval containing
the measured value is reported. It is not likely that the
measured value would correspond exactly to the
center of the interval. The error could be as large as
half the width of the interval. With a binary word size
of eight, full scale is partitioned into 255 intervals.
Consider a measurement made near full scale. Any
signal in this interval is less than ± .2% (one-half of
100% / 256) away from the interval’s center, and
would therefore never have more error than that due
to quantization. On the other hand, consider a
measurement at one-tenth full scale. One-half of an
interval size at this level corresponds to 2% of the
reported value! Relative quantization error increases
as the measured value becomes small compared to
the full-scale value.
tolerances can be added in quadrature (RSS). As an
example, a 3% DCR used with a 1% RT, a 1% RCS,
and 1.5% IR3725 contributes
Quantization error can be reduced by averaging a
sequence of returned values.
(0.03)2 + (0.01)2 + (0.01)2 + (0.015)2 ≈ 3.6%
error to a typical system.
LAYOUT GUIDELINES
The following guidelines will minimize noise and
error. Refer to the Functional Description Diagram.
1. Bypass VDD to GND with a high quality
ceramic capacitor.
5. VO should sense the voltage at the point of
interest. Bypass VO to GND with a high
quality ceramic capacitor near the IC.
6. Use an isolated dedicated ground plane
connected only to grounded components
associated with the IC in the figure. Connect
this dedicated ground plane at one location
to the ground of the monitored voltage.
7. Do not connect pin 12 to any electrically
active node.
2. Place Ccs2 close to IC pins Vcs1 and Vcs2.
Route Vcs1 and Vcs2 to the current sensing
element as a differential pair.
3. Sense the current sensing element at its
terminals, Kelvin style. Current and power
will be over reported if printed wire board
resistance is included between the sense
points.
4. If inductor DCR current sensing is used,
place the compensating thermistor near the
inductor. Route the thermistor leads back to
the vicinity of the IC with differential routing.
Void any vias going to ground along the path
back until near the IC. Locate the thermistor
network (not the thermistor) near the IC.
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IR3725
Data Sheet
CONFIGURATION REGISTER
A configuration register is maintained via the serial
bus MFR_SPECIFIC_00 command, code # D0h. The
low order nibble (d3, d2, d1, d0) contains a binary
number N from zero to eight. The averaging interval
is 2N milliseconds. N defaults to zero on start up.
The results of a configuration register change will be
reflected in the OUTPUT REGISTER after previously
requested operations have completed. Initialize the
configuration register after start up.
The next bit (d4) is to be used as a function shutdown
bit. b’1 commands an energy saving shutdown mode,
and power on default b’0 commands fully functioning
mode.
BIT #
CONFIGURATION REGISTER
d0
d1
Averaging interval (LSB)
Averaging interval
d2
d3
d4
d5
Averaging interval
Averaging interval (MSB)
Shutdown
d5 high enables the EXTCLK pin to receive the
external clock signal, and default d5 low enables the
internal clock.
External clock
d6
d7
d8
d9
d10
d11
d12
d13
d14
d15
OUTPUT config (LSB)
OUTPUT config (MSB)
ALERT# configuration
ALERT# threshold (LSB + 2)
ALERT# threshold
ALERT# threshold
ALERT# threshold
ALERT# threshold
ALERT# threshold
ALERT# threshold (MSB)
The next two bits (d7, d6) program the output
parameter. B’00 causes power to be measured and is
the power on default state. B’01 causes voltage to be
measured. B’10 causes current to be measured. B’11
is not defined and should not be used.
The next bit (d8) is used to configure the ALERT#
pin. b’0 is the power on default, and commands
ALERT# to be pulled low when new data is available.
b’1 programs the ALERT# to pull low when the
programmable threshold level is exceeded, whether it
is power, voltage, or current.
Register bits (d15...d9) are the ALERT# threshold
register. If the output register is larger than this
register, and if (d8) is b’1, then the ALERT# pin will
pull low. The two least significant bits of the output
register are not represented in the ALERT# threshold
register. d15…d9 defaults to zero on start up.
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IR3725
Data Sheet
OUTPUT REGISTER
The output register is loaded with a two’s compliment
factor of voltage, current, or power, depending on the
last request loaded into the configuration register.
Serial bus “Direct Data Format” is used. The value of
the output register is to be multiplied by a scale factor
that is derived below to yield power, voltage, or
current in engineering units of watts, volts, or amps.
Maximum power is the product of maximum voltage
and maximum current.
There is but one output register, and it holds the
measurement type (voltage, current, or power) last
requested by the configuration register. It is
incumbent upon the user to establish correct
configuration before requesting a read.
READ_VOUT, READ_IOUT, and READ_POUT are
equivalent in that each returns the contents of the
same output register.
The range of valid output register values is indicated
in Table 2 below.
BIT#
OUTPUT REGISTER
d15:d0
Output variable, D0 is LSB
Table 2 Output Register Range of Returned
Values
Parameter
Returned value
(twos compliment
binary)
0100 0000 0000 0000
0000 0000 0000 0000
0100 0000 0000 0000
1100 0000 0000 0000
0100 0000 0000 0000
1100 0000 0000 0000
Returned
value
(decimal)
256
0
256
-256
256
-256
RESERVED COMMAND
CODES
Command codes D2h through D5h, D7h, and D8h
are reserved for manufacturing use only and could
lead to undesirable device behavior.
FS voltage
Zero voltage
+FS current
-FS current
+FS power
-FS power
A binary point is implicitly located to the left of the first
six least significant figures, as in the example below.
SYYY YYYY YY.00 0000
The “S” above is the twos compliment sign bit, and
the “Y’s” are the twos compliment integers. Six zeros
pad out the two byte response. These padding zeros
could be considered a factor of the slope, which is
allowed by the Direct Data Format. The output
register multiplied by its scale factor Kx yields the
requested quantity in engineering units, volts, amps,
or watts.
The equations below convert digital counts to
engineering units:
Voltage = counts * VFS / 256
Current = counts * VIG * (RCS1+RCS2) /
(RT * DCR * 256)
Power = counts * VFS*VIG*(Rcs1 + Rcs2) /
(RT*DCR*256)
Page 14 of 19
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IR3725
Data Sheet
PACKET PROTOCOL
S
W
R
A
=
=
=
=
=
=
Start Condition
Bus write (0)
Bus read (1)
Acknowledge, = 0 for ACK, =1 for NACK
Stop Condition
P
master to slave
=
slave to master
Bus Write CONFIGURATION Register
S
S
Slave Address
see Table 1
W A
Command Code
A
A
Data Byte Low
A
A
Data Byte High
A P
0
A
1
1
0
1
0
0
0
0
A P
d10 d9 d8
d7 d6 d5 d4 d3 d2 d1 d0
d15
d14
d13
d12
d11
Bus Read CONFIGURATION Register
Slave
Address
see
Table 1
Slave
Address
See
Table 1
S
S
W
0
A
Command Code A S
R A
Data Byte Low
A
A
Data Byte High
A P
1 P
d7 d6 d5 d4 d3 d2 d1 d0
1 A
d15 d14 d13 d12 d11 d10 d9
d8
A 1 1 0 1 0 0 0 0 A S
Bus READ_VOUT (Output Register for Configuration register Data Byte Low = 01XXXXXX)
Slave
Address
see
Slave
Address
See
S
S
W
0
A
Command Code A S
R A
1 A
Data Byte Low
A
A
Data Byte High
A P
1 P
d7 d6 d5 d4 d3 d2 d1 d0
d15 d14 d13 d12 d11 d10 d9
d8
d8
d8
A 1 0 0 0 1 0 1 1 A S
Table 1
Table 1
Bus READ_IOUT (Output Register for Configuration register Data Byte Low = 10XXXXXX)
Slave
Address
see
Slave
Address
See
S
S
W
0
A
Command Code A S
R A
1 A
Data Byte Low
A
A
Data Byte High
A P
1 P
d7 d6 d5 d4 d3 d2 d1 d0
d15 d14 d13 d12 d11 d10 d9
A 1 0 0 0 1 1 0 0 A S
Table 1
Table 1
Bus READ_POUT (Output Register for Configuration register Data Byte Low = 00XXXXXX)
Slave
Address
see
Slave
Address
See
S
S
W
0
A
Command Code A S
R A
1 A
Data Byte Low
A
A
Data Byte High
A P
1 P
d7 d6 d5 d4 d3 d2 d1 d0
d15 d14 d13 d12 d11 d10 d9
A 1 0 0 1 0 1 1 0 A S
Table 1
Table 1
Page 15 of 19
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2008_12_09
IR3725
Data Sheet
PCB PAD AND COMPONENT PLACEMENT
The figure below shows a suggested pad and component placement.
Page 16 of 19
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2008_12_09
IR3725
Data Sheet
SOLDER RESIST
The figure below shows a suggested solder resist placement.
Page 17 of 19
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2008_12_09
IR3725
Data Sheet
STENCIL DESIGN
The figure below shows a suggested solder stencil design.
Page 18 of 19
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2008_12_09
IR3725
Data Sheet
PACKAGE INFORMATION
4 X 3 MM 12L DFN LEAD FREE
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
Page 19 of 19
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2008_12_09
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