IR38064MTRPBF_技术文档

DCDC Converter

Digital SupIRBuck

IR38064

35A Single-input Voltage, Synchronous

Buck Regulator with PMBus Interface

FEATURES

DESCRIPTION



Internal LDO allows single 21V operation

The IR38064 PMBus SupIRBuck™ is an easy-to-use,

fully integrated and highly efficient DC/DC regulator

with I2C/PMBus interface. The onboard PWM controller

Output Voltage Range: 0.5V to 0.875*PVin

0.5% accurate Reference Voltage

and MOSFETs make IR38064

a

space-efficient

solution, providing accurate power delivery for low

output voltage and high current applications.

Programmable Switching Frequency up to

1.5MHz using Rt/Sync pin or PMBus



Internal Soft-Start with Pre-Bias Start-up

The IR38064 can be comprehensively configured via

PMBus and the configuration stored in internal

memory. In addition, PMBus commands allow run-time

control, fault status and telemetry.

Enable input with Voltage Monitoring Capability

Remote Sense Amplifier with True Differential

Voltage Sensing



Fast mode I2C and 400 kHz PMBus interface

Sequencing and tracking capable

The IR38064 can also operate as a standard analog

regulator without any programming and can provide

current and temperature telemetry in an analog format.

Selectable analog mode or digital mode

66 PMBus commands for configuration, control,

fault protection and telemetry.



Thermally compensated current limit with

configurable overcurrent responses

APPLICATIONS



Optional light load efficiency mode

Server Applications

External synchronization with Smooth Clocking

Netcomm applications

Dedicated output voltage sensing protection

which remains active even when Enable is low.

Embedded telecom Systems

Distributed Point Of Load Architectures



Integrated MOSFETs and Bootstrap diode

Operating junction temp: -40^oC<Tj<125^oC

Small Size 5mmx7mm PQFN

Pb-Free (RoHS Compliant)

ORDERING INFORMATION

Standard Pack

Form Quantity

Tape

Base

Part

Package

Type

Orderable Part

Application Description

Number

QFN

5x7 mm

Standard part, 1.2Vout

IR38064

&

4000

IR38064MTRPBF

Reel

1

Rev 3.7

Mar 14, 2018

IR38064

BASIC APPLICATION

5.5V <Vin<21V

P1V8

Track_EN

PVin

Vin

Boot

SW

Vo

Vcc/

LDO_out

Vsns

RS+

PGood

Rt/SYNC

RS-

En/FCCM

Vp

RSo

Fb

Comp

LGnd

ADDR

PGnd

Figure 1: Typical Application Circuit

Figure 2: Performance Curve

PINOUT DIAGRAM

Note: Pins 23 and 26 are connected internally

but appear separated externally (refer to

assembly drawing)

Figure 3: IR38064 package (Top View) 5mm x 7mm PQFN

2

Rev 3.7

Mar 14, 2018

IR38064

BLOCK DIAGRAM

VCC

Vin

P1V8

LDO

VLDOref

LDO

LGND

COMP

-

OT_Fault

+

UVcc

OC_Fault

BOOT

PVIN

VCC

UVcc

FAULT

CONTROL

UVEN

Fault

Vcc

+

Fault

HDrv

Vp

E/A

HDin

VDAC2

Vcc

-

Track_EN

Vcc

GATE

DRIVE

LOGIC

OV_Fault

FCCM

SW

FB

RT/

Sync

VCC

LDrv

LDin

EN/

FCCM

PGND

CONTROL AND FAULT LOGIC

Rso

PGood

RS-

RS+

ISense

TMON

Current Sense

IMON

SDA/IMON

SCL/OCSet

SMBus

Interface,

OCSet

TMON

Temperature

Sense

Logic, Command and Status registers

SAlert/TMON

Vcc

ADDR

Vsns

Figure 4: IR38064 Simplified Block Diagram

3

Rev 3.7

Mar 14, 2018

IR38064

PIN DESCRIPTIONS

PIN #

PIN NAME

PIN DESCRIPTION

Input voltage for power stage. Bypass capacitors between PVin and PGND should

be connected very close to this pin and PGND. Typical applications use 4 X22 uF

input capacitors and a low ESR, low ESL 0.1uF decoupling capacitor in a

0603/0402 case size. A 3.3nF capacitor may also be used in parallel with these

input capacitors to reduce ringing on the Sw node.

1

PVIN

Supply voltage for high side driver. A 0.1uF capacitor should be connected from this

pin to the Sw pin. For PVin > 16V, it is recommended to use a 1 ohm to 4.02 ohm

resistor in series with the boot capacitor.

2

3

Boot

Pull low to enable tracking function. For normal, non-tracking operation, connect a

100 kOhm resistor from this pin to P1V8. An alternative to using 100 kohm to P1V8

is to connect a 750 kohm resistor from Track_En# to LGND when the Track_En#

pin is not used for a tracking function. One of these two options must be used to

disable tracking functionality. The 100kOhm is the preferred method.

¯T¯r¯a¯c¯k¯_¯E¯n¯ *

4

5

Vp

Used for sequencing and tracking applications. Leave open if not used.

Sense pin for OVP and PGood

Vsns

Inverting input to the error amplifier. This pin is connected directly to the output of

the regulator or to the output of the remote sense amplifier, via resistor divider to

set the output voltage and provide feedback to the error amplifier.

6

FB

Output of error amplifier. An external resistor and capacitor network is typically

connected from this pin to FB to provide loop compensation.

7

COMP

8

9

RSo

RS-

RS+

Remote Sense Amplifier Output

Remote Sense Amplifier input. Connect to ground at the load.

Remote Sense Amplifier input. Connect to output at the load.

10

Power Good status pin. Output is open drain. Connect a pull up resistor from this

pin to VCC. If the power good voltage before VCC UVLO needs to be limited to <

500 mV, use a 49.9K pullup, otherwise a 4.99K pullup will suffice.

11

PGood

Power ground. This pin should be connected to the system’s power ground plane.

Bypass capacitors between PVin and PGND should be connected very close to the

PVIN pin (pin 1) and this pin.

12,25

13

PGND

LGND

Signal ground for internal reference and control circuitry.

In analog mode, use an external resistor from this pin to GND to set the switching

frequency. The resistor should be placed very close to the pin. This pin can also be

used for external synchronization. In digital mode this pin is typically left floating

however a 15K resistor from this pin to GND may be used instead of floating the

pin.

14

RT/Sync

Enable pin to turn on and off the IC. In analog mode, also serves as a mode pin,

forcing the converter to operate in CCM when pulled to<3.1V.

15

16

EN/FCCM

ADDR

A resistor should be connected from this pin to LGnd to set the PMBus address

offset for the device. It is recommended to provide a placement for a 10 nF

capacitor in parallel with the offset resistor. If communication is not needed, as in

analog mode, this pin should be left floating

4

Rev 3.7

Mar 14, 2018

IR38064

PIN #

PIN NAME

PIN DESCRIPTION

SMBus ¯A¯le¯r¯t line; open drain SMBALERT# pin. This should be pulled up to 3.3V-

5V with a 1K-5K resistor; this pin provides a voltage proportional to the junction

temperature if digital communication is not needed, as in analog mode.

S¯¯A¯L¯E¯R¯T¯

/TMON

17

SMBus data serial input/output line; This should be pulled up to 3.3V-5V with a 1K-

5K resistor; this pin provides a voltage proportional to the output current if digital

communication is not needed, as in analog mode.

18

19

SDA/IMON

SCL/OCSet

SMBus clock line; This should be pulled up to 3.3V-5V with a 1K-5K resistor. This

pin is used to set OC thresholds if digital communication is not needed, as in analog

mode. In analog mode recommend 4.7KΩ for the pull-up to VCC or pull down to

GND when setting the OCP value.

This is the supply for the digital circuits; bypass with a minimum 2.2uF capacitor to

PGnd. A 10uF capacitor is recommended.

20

21

22

P1V8

Vin

Input Voltage for LDO.

Bias Voltage for IC and driver section, output of LDO. Add 10 uF bypass cap from

this pin to PGnd.

VCC

23,26

24

NC

SW

NC

Switch node. This pin is connected to the output inductor.

*Design has simulated the Track_En# input threshold test for a 750K over:



the temperature range of -40 to 150degC,

Vcc of 4.5V to 5.5V

Over all corners of silicon

5

Rev 3.7

Mar 14, 2018

IR38064

ABSOLUTE MAXIMUM RATINGS

Stresses beyond these listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

These are stress ratings only and functional operation of the device at these or any other conditions beyond those

indicated in the operational sections of the specifications are not implied.

PVin, Vin

-0.3V to 25V

VCC

-0.3V to 6V

P1V8

-0.3V to 2 V

SW

-0.3V to 25V (DC), -4V to 25V (AC, 100ns)

-0.3V to 31V

BOOT

PGD, other Input/output pins

BOOT to SW

-0.3V to 6V (Note 1)

-0.3V to 6V (DC), -0.3V to 6.5V (AC, 100ns)

-0.3V to + 0.3V

PGND to GND, RS- to GND

THERMAL INFORMATION

Junction to Case Thermal Resistance Ɵ_JC-TOP

30^oC/W

Junction to Ambient Thermal Resistance Ɵ_JA

Junction to PCB Thermal Resistance Ɵ_J-PCB

Storage Temperature Range

13.8^oC/W

2.05^oC/W

-55°C to 150°C

-40°C to 150°C

Junction Temperature Range

(Voltages referenced to GND unless otherwise specified)

Note 1: Must not exceed 6V.

6

Rev 3.7

Mar 14, 2018

IR38064

ELECTRICAL SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

SYMBOL

DEFINITION

MIN

MAX

UNITS

PVin

Input Bus Voltage

V

1.2

21*

Vin

LDO supply voltage

5.5

4.5

0.5

0

21

5.5

VCC

LDO output/Bias supply voltage

High Side driver gate voltage

Output Voltage

Boot to SW

5.5

V_O

I_O

0.875*PV_in

35

Output Current

A

Fs

T_J

Switching Frequency

Junction Temperature

225

-40

1650

125

kHz

°C

* For input voltages above 16Vin, a resistor is required to be placed in series with the Cboot capacitor that is in

the circuit from the Boot pin (pin 2) to the Sw pin (pin 24). The recommended resistor value is 4.02 ohm. This

Rboot resistor is used to slow the turn-on of the high side MOSFET, which reduces the peak voltage on the switch

node pin by up to 2V. The switch node voltage must be kept below the datasheet maximum of 25Vdc and it is

recommended that it be kept below a peak value of 20 V to 22 V.

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, these specification apply over, 1.5V < PVin < 21V, 4.5V < Vcc < 5.5, 0C < T_J<

125C.

Typical values are specified at T_A= 25C.

PARAMETER

MOSFET R_ds(on)

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

Top Switch

Rds(on)_Top

Rds(on)_Bot

V_Boot– V_SW= 5V, I_D= 35A, Tj

= 25°C

2.4

3.4

4.4

mΩ

Bottom Switch

Vcc =5V, I_D= 35A, Tj = 25°C

0.86

1.32

1.78

Reference Voltage

1.25V<V_FB<2.555V

VOUT_SCALE_LOOP=1;

-1

1

%

Accuracy

0.75V<V_FB<1.25V

VOUT_SCALE_LOOP=1;

-0.75

-0.5

+0.75

0.5

0⁰C<Tj<85⁰C

0.45V<V_FB<0.75V

%

VOUT_SCALE_LOOP=1;

Accuracy

-40⁰C<Tj<125⁰C

1.25V<V_FB<2.555V

VOUT_SCALE_LOOP=1;

-1.6

+1.6

7

Rev 3.7

Mar 14, 2018

IR38064

PARAMETER

SYMBOL

CONDITIONS

0.75V<V_FB<1.25V

MIN

-1.0

-2.0

TYP

MAX

+1.0

+2.0

UNIT

%

VOUT_SCALE_LOOP=1;

0.45V<V_FB<0.75V

VOUT_SCALE_LOOP=1;

Supply Current

PVin range (using

external Vcc=5.1V)

1.2-21

V

Vin range (using

internal LDO)

Fsw=600kHz

Fsw=1.5MHz

5.3-21

5.5-21

Vin range (when

Vin=Vcc)

4.5

5.1

2.7

39

5.5

4

V

V_inSupply Current

(Standby) (internal Vcc)

I_in(Standby)

Enable low, No Switching,

Vin=21V, low power mode

enabled

mA

V_inSupply Current

(Dyn)(internal Vcc)

I_in(Dyn)

Enable high, Fs = 600kHz,

Vin=21V

50

5

VCC Supply Current

(Standby)(external Vcc)

I_cc(Standby)

Enable low, No Switching,

Vcc=5.5V, low power mode

enabled

2.7

39

VCC Supply Current

(Dyn)(external Vcc)

I_cc(Dyn)

Enable high, Fs = 600kHz,

Vcc=5.5V

50

Under Voltage Lockout

VCC – Start –

Threshold

VCC_UVLO_Star VCC Rising Trip Level

t

4.0

3.7

4.2

3.9

4.4

4.1

V

VCC – Stop –

Threshold

VCC_UVLO_Sto

p

VCC Falling Trip Level

PVin-Start-Threshold

PVin-Stop-Threshold

PVin_UVLO_Star PVin Rising Trip Level

t

0.85

0.35

1.14

0.95

0.45

1.2

1.05

0.55

1.36

PVin_UVLO_Sto

p

PVin Falling Trip Level

Enable – Start –

Threshold

Enable_UVLO_S Supply ramping up

tart

V

Enable – Stop –

Threshold

Enable_UVLO_S Supply ramping down

top

0.9

1.0

1.06

1

Enable leakage current

Ien

Enable=5.5V

uA

kHz

Oscillator

Rt current (analog mode

only)

Rt pin voltage < 1.1V

98

100

102

Frequency Range

F_S

Rt=1.54K

Rt=3.83K

Rt=11.8K

360

540

400

600

440

660

1350

1500

1650

8

Rev 3.7

Mar 14, 2018

IR38064

PARAMETER

SYMBOL

Dmin (ctrl)

CONDITIONS

MIN

TYP

MAX

UNIT

Min Pulse Width

Note 2

35

50

ns

Fixed Off Time

Note 2 Fs=1.5MHz

Fs=400kHz

Note 2

100

87.5

150

Max Duty Cycle

Dmax

86.5

225

100

2.1

88.5

1650

%

Sync Frequency Range

Sync Pulse Duration

Sync Level Threshold

kHz

ns

200

High

Low

V

1

Error Amplifier

Vos_Vp

Input Offset Voltage

VFb – Vp, Vp = 0.5V

-1.5

+1.5

%%

Input Bias Current

Sink Current

IFb(E/A)

IVp(E/A)

Isink(E/A)

Isource(E/A)

SR

-0.5

0

+0.5

7

µA

mA

V/µs

V

0.6

8

1.1

13

1.8

25

Source Current

Slew Rate

Note 2

7

12

20

Maximum Voltage

Minimum Voltage

Common Mode Voltage

Vmax(E/A)

Vmin(E/A)

Vcm_Vp

2.8

3.9

4.3

100

2.555

mV

V

0

Remote Sense Differential Amplifier

0.5V<RS+<2.555V, 4kOhm

load

-1.6

-3

0

1.6

3

27⁰C<Tj<85⁰C

Offset Voltage

Offset_RS

mV

0.5V<RS+<2.555V, 4kOhm

load

-40⁰C<Tj<125⁰C

Source Current

Sink Current

Isource_RS

Isink_RS

Slew_RS

Rin_RS+

Rin_RS-

V_RSO=1.5V, V_RSP=4V

11

0.4

2

16

2

mA

1

4

Slew Rate

Note 2, Cload = 100pF

8

V/µs

Kohm

V

RS+ input impedance

RS- input impedance

Maximum Voltage

Minimum Voltage

Bootstrap Diode

Forward Voltage

Switch Node

36

0.5

55

1

74

1.5

20

Note 2

Vmax_RS

Min_RS

V(VCC) – V(RS+)

4

mV

I(Boot) = 40mA

150

300

18

450

1

mV

µA

SW Leakage Current

Lsw

SW = 0V, Enable = 0V

SW=0; Enable= 2V

Isw_En

Internal Regulator (VCC/LDO)

9

Rev 3.7

Mar 14, 2018

IR38064

PARAMETER

SYMBOL

VCC

CONDITIONS

MIN

TYP

MAX

UNIT

Vin(min) = 5.5V, Io=0mA,

Cload = 10uF

Output Voltage

5.15

4.99

4.8

4.5

5.4

5.2

0.7

V

Vin(min) = 5.5V, Io=70mA,

Cload = 10uF

VCC dropout

VCC_drop

Ishort

Io=0-70mA, Cload = 10uF,

Vin=5.1V

V

Short Circuit Current

110

mA

Internal Regulator (P1V8)

Output Voltage

P1V8

Vin(min) = 4.5V, Io = 0‐

10mA, Cload = 2.2uF

1.795

3.8

1.83

1.905

V

Adaptive On time Mode

AOT Threshold

High

Low

En/Fccm

3.9

3.6

4.1

3.8

V

3.1

Zero-crossing

comparator threshold

ZC_Vth

-4

-1

2

mV

s

Zero-crossing

comparator delay

ZC_Tdly

8/Fs

FAULTS

Power Good

Power Good High

threshold

Power_Good_Hi

gh

Vsns rising,

VOUT_SCALE_LOOP=1,

Track_EN floating,

VDAC1=0.5V

%VDAC

1

91

90

86

Vsns rising,

VOUT_SCALE_LOOP=1,

Track_EN low, Vp=0.5V

%Vp

Power Good Low

Threshold

Power_Good_Lo

w

Vsns falling,

VOUT_SCALE_LOOP=1,

Track_EN floating,

VDAC1=0.5V

%VDAC

1

Vsns falling,

VOUT_SCALE_LOOP=1,

Track_EN low, Vp=0.5V

84.5

0

%Vp

Power Good High

TPDLY

Vsns rising, Vsns >

Power_Good_High

ms

us

Threshold Rising Delay

Power Good Low

VPG_low_Dly

Vsns falling, Vsns <

Power_Good_Low

150

175

0.4

200

Threshold Falling delay

Tracker

Upper Threshold

Comparator

VPG(tracker_

upper)

Vp

Rising,

0.38

0.42

VOUT_SCALE_LOOP=1,

Track_EN low, Vsns=Vp

V

Tracker

Lower Threshold

Comparator

VPG(tracker_

lower)

Vp

Falling,

0.28

0.3

0.32

0.5

VOUT_SCALE_LOOP=1,

Track_EN low, Vsns=Vp

PGood Voltage Low

10

PG (voltage)

I_PGood= -5mA

V

Rev 3.7

Mar 14, 2018

IR38064

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

Over Voltage Protection (OVP)

OVP Trip Threshold

OVP (trip)

Vsns rising,

VOUT_SCALE_LOOP=1,

Track_EN floating,

VDAC1=0.5V

%VDAC

1

115

2.5

121

120

4.5

125

5.8

Vsns rising,

VOUT_SCALE_LOOP=1,

Track_EN low, Vp=0.5V

%Vp

OVP comparator

Hysteresis

OVP (hyst)

Vsns falling,

VOUT_SCALE_LOOP=1,

Track_EN floating,

VDAC1=0.5V

%OVP

(trip)

Vsns rising,

VOUT_SCALE_LOOP=1,

Track_EN low, Vp=0.5V

%OVP

(trip)

2.5

4.5

5.8

OVP Fault Prop Delay

OVP (delay)

Vsns rising, Vsns-

OVP(trip)>200 mV

200

ns

Over-Current Protection

OC Trip Current (analog I_TRIP

mode only)

Analog mode: OCSet pulled

high to VCC via resistor.

43.5

34

46

36

28

48.4

37.9

30

A

VCC = 5.05V, T_j=25⁰C

Analog mode: OCSet left

floating.

VCC = 5.05V, T_j=25⁰C

Analog mode: OCSet pulled

low to GND via resistor.

VCC = 5.05V, T_j=25⁰C

26.5

OCset Current

Temperature coefficient

OCSET(temp)

Tblk_Hiccup

-40⁰C to 125⁰C, VCC=5.05V,

Note 2

5900

20

ppm/°C

ms

Hiccup blanking time

Thermal Shutdown

Hysteresis

Note 2

145

25

°C

Input Over-Voltage Protection

PVin overvoltage

threshold

PVin_OV

22

23.7

2.4

25

V

PVin overvoltage

Hysteresis

PVin _{ov hyst}

MONITORING AND REPORTING

Bus Speed¹

100

78

400

kHz

Hz

Iout & Vout filter

Iout & Vout Update rate

31.25

kHz

11

Rev 3.7

Mar 14, 2018

IR38064

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

Vin & Temperature filter

78

Hz

Vin

update rate

&

Temperature

31.25

kHz

Output Voltage Reporting

Resolution

N_Vout

Note 2

1/256

0

V

Lowest reported Vout

Highest reported Vout

Vomon_low

Vomon_high

Vsns=0V

VOUT_SCALE_LOOP=1,

Vsns=3.3V

3.3

6.6

V

VOUT_SCALE_LOOP=0.5,

Vsns=3.3V

VOUT_SCALE_LOOP=0.25,

Vsns=3.3V

13.2

26.4

VOUT_SCALE_LOOP=0.125

, Vsns=3.3V

Vout reporting accuracy

0⁰C to 85⁰C, 4.5V<Vcc<5.5V,

1V<Vsns≤ 1.5V

+/-0.6

+/-1

VOUT_SCALE_LOOP=1

0⁰C to 85⁰C, 4.5V<Vcc<5.5V,

Vsns> 1.5V

VOUT_SCALE_LOOP=1

0⁰C to 125⁰C,

%

4.5V<Vcc<5.5V, Vsns>0.9V

VOUT_SCALE_LOOP=1

+/-1.5

0⁰C to 125⁰C,

4.5V<Vcc<5.5V,

0.5V<Vsns<0.9V

VOUT_SCALE_LOOP=1

+/-3

Iout Reporting

Resolution

N_Iout

Note 2

62.5

mA

A

Iout (digital) monitoring

Range

Iout_dig

0

52.5

1.1

Iout_dig Accuracy

0⁰C to 125⁰C,

4.5V<Vcc<5.5V, 5A < Iout <3

5A

+/-5

%

V

Imon (analog) voltage

Imon

0.3

Imon ( analog) accuracy

0⁰C to 125⁰C,

4.5V<Vcc<5.5V, 5A < Iout <1

5A, -30uA< I_IMON<30uA

+/-1.5

1

A

Temperature Reporting

Resolution

N_Tmon

Note 2

°C

Temperature Monitoring Tmon_dig

(digital) Range

-40

150

12

Rev 3.7

Mar 14, 2018

IR38064

PARAMETER

SYMBOL

CONDITIONS

-40⁰C to 125⁰C,

4.5V<Vcc<5.5V, -30uA<

I_TMON<30uA; Guaranteed

by char

MIN

TYP

MAX

UNIT

Temperature Monitoring

(digital) accuracy

-5

5

°C

Analog monitoring

range

Tmon

-40⁰C to 150⁰C

500

-9

1100

9

mV

°C

Analog Monitoring

Accuracy

-40⁰C to 125⁰C,

4.5V<Vcc<5.5V, -30uA<

I_TMON<30uA, Note 2

Temperature coefficient

2.27

25

mV/°C

°C

Thermal shutdown

hysteresis

Note 2

Input Voltage Reporting

Resolution

N_PVin

1/32

V

Monitoring Range

Monitoring accuracy

PMBVinmon

0

21

0⁰C to 85⁰C, 4.5V<Vcc<5.5V,

PVin>10V

-1.5

1.5

-40⁰C to 125⁰C,

4.5V<Vcc<5.5V, PVin>14V

-40⁰C to 125⁰C,

4.5V<Vcc<5.5V,

6V<PVin<14V

-1.5

-3

1.5

3

%

PMBus Interface Timing Specifications

SMBus Operating

frequency

F_SMB

400

kHz

us

Bus Free time between

Start and Stop condition

T_BUF

1.3

0.6

Hold time after

T_HD:STA

(Repeated) Start

Condition. After this

period, the first clock is

generated.

us

Repeated start

condition setup time

T_SU:STA

T_SU:STO

0.6

us

Stop condition setup

time

Data Rising Threshold

Data Falling Threshold

Clock Rising Threshold

Clock Falling Threshold

Data Hold Time

1.339

1.048

1.339

1.048

300

1.766

1.495

1.766

1.499

900

V

T_HD:DAT

T_SU:DAT

ns

Data Setup Time

100

13

Rev 3.7

Mar 14, 2018

IR38064

PARAMETER

SYMBOL

T_TIMEOUT

CONDITIONS

MIN

TYP

MAX

UNIT

Clock low time out

Clock low period

Clock High Period

25

1.3

0.6

35

ms

us

T_LOW

T_HIGH

50

Notes

2. Guaranteed by design but not tested in production

3. Guaranteed by statistical correlation, but not tested in production

14

Rev 3.7

Mar 14, 2018

IR38064

TYPICAL APPLICATION DIAGRAMS

5.5V <PVin<21V

P1V8

Track_EN

PVin

Vin

Boot

SW

Vo

Vcc/

LDO_out

Vsns

RS+

PGood

Rt/SYNC

RS-

En/FCCM

Vp

RSo

Fb

Comp

LGnd

ADDR

PGnd

Figure 5: Using the internal LDO, digital mode, Vo < 2.555V

5.5V <PVin<21V

P1V8

Track_EN

PVin

Vin

Boot

SW

Vo

Vcc/

LDO_out

Vsns

RS+

PGood

Rt/SYNC

R2

RS-

Recommend R2 =499Ω

En/FCCM

Vp

RSo

Fb

Comp

LGnd

ADDR

PGnd

Figure 6: Using the internal LDO, digital mode, Vo > 2.555V

15

Rev 3.7

Mar 14, 2018

IR38064

TYPICAL APPLICATION DIAGRAMS

5.5V < PVin< 21V

P1V8

PVin

Track_EN

Vin

Boot

SW

Vo

Vcc/

LDO_out

Vsns

RS+

PGood

Rt/SYNC

RS-

En/FCCM

Vp

RSo

Fb

Comp

LGnd

ADDR

PGnd

Figure 7: Using the internal LDO, analog mode, Vo<2.555 V

1.2V <PVin<21V

P1V8

PVin

Track_EN

Vin

Boot

SW

Vcc=5V

Vo

Vcc/

LDO_out

Vsns

RS+

PGood

Rt/SYNC

RS-

En/FCCM

Vp

RSo

Fb

Comp

LGnd

ADDR

PGnd

Figure 8: Using external Vcc, digital mode, Vo<2.555V

16

Rev 3.7

Mar 14, 2018

IR38064

TYPICAL APPLICATION DIAGRAMS

PVin=Vin=Vcc= 5V

P1V8

PVin

Track_EN

Vin

Boot

SW

Vo

Vcc/

LDO_out

Vsns

RS+

PGood

Rt/SYNC

RS-

En/FCCM

Vp

RSo

Fb

Comp

LGnd

ADDR

PGnd

Figure 9: Single 5V application, digital mode, Vo<2.555V

5.5V <PVin<21V

P1V8 Vp

Vcc/

PVin

Vin

Boot

SW

Vo

LDO_out

Vsns

RS+

PGood

Rt/SYNC

RS-

En/FCCM

Track_EN

RSo

Fb

Comp

LGnd

ADDR

PGnd

Figure 10: Using the internal LDO, digital mode, tracking mode

17

Rev 3.7

Mar 14, 2018

IR38064

TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)

18

Rev 3.7

Mar 14, 2018

IR38064

TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)

19

Rev 3.7

Mar 14, 2018

IR38064

TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)

20

Rev 3.7

Mar 14, 2018

IR38064

TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)

21

Rev 3.7

Mar 14, 2018

IR38064

TYPICAL EFFICIENCY AND POWER LOSS CURVES

PVin = Vin = 12V, VCC = Internal LDO, Io=0-35A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the

losses of the inductor, input and output capacitors are also considered in the efficiency and power loss curves.

The table below shows the indicator used for each of the output voltages in the efficiency measurement.

VOUT (V)

LOUT (uH)

0.15

P/N

DCR (mΩ)

0.15

0.8

1

HCB138380D-151 (Delta)

FP1308R3-R32-R (Cooper)

0.15

0.32

0.15

0.32

1.2

1.5

1.8

3.3

5

22

Rev 3.7

Mar 14, 2018

IR38064

TYPICAL EFFICIENCY AND POWER LOSS CURVES

PVin = Vin = VCC = 5V, Io=0-35A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the losses of the

inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table

below shows the indicator used for each of the output voltages in the efficiency measurement.

VOUT (V)

0.8

LOUT (uH)

0.15

P/N

DCR (mΩ)

0.15

HCB138380D-151 (Delta)

FP1308R3-R32-R (Cooper)

1

1.2

1.5

1.8

0.15

3.3

0.32

23

Rev 3.7

Mar 14, 2018

IR38064

THEORY OF OPERATION

the Power-on-reset (POR) low until these voltages

exceed their thresholds and the internal 48 MHz

oscillator is stable. When the device comes out of

reset, it initializes a multiple times programmable

memory (MTP) load cycle, where the contents of the

MTP are loaded into the working registers. Once the

registers are loaded from MTP, the designer can use

PMBus commands to re-configure the various

parameters to suit the specific VR design

requirements if desired, irrespective of the status of

Enable.

DESCRIPTION

The IR38064 is a 35A synchronous buck regulator

with a selectable digital interface and an externally

compensated fast, analog, PWM voltage mode

control scheme to provide good noise immunity as

well as fast dynamic response in a wide variety of

applications. At the same time, enabling the digital

PMBus interface allows complete configurability of

output setting and fault functions, as well as

telemetry.

The switching frequency is programmable up to

1.5MHz and provides the capability of optimizing the

design in terms of size and performance.

In the default configuration, power conversion is

enabled only when the En/FCCM pin voltage

exceeds its undervoltage threshold, the PVin bus

voltage exceeds its undervoltage threshold, the

contents of the MTP have been fully loaded into the

working registers and the device address has been

read. The initialization sequence is shown in Figure

11.

IR38064 provides precisely regulated output voltage

from 0.5V to 0.875*PVin programmed via two

external resistors or digitally through PMBus

commands. The IR38064 operates with an internal

bias supply (LDO), typically 5.2V. This allows

operation with a single supply. The output of this

LDO is brought out at the Vcc pin and must be

bypassed to the system power ground with a 10 uF

decoupling capacitor. The Vcc pin may also be

connected to the Vin pin, and an external Vcc supply

between 4.5V and 5.5V may be used, allowing an

extended operating bus voltage (PVin) range from

1.2V to 21V.

IR38064 provides additional options to enable the

device power conversion through software and

these options may be configured to override the

default by using the I2C interface or PMBus, if used

in digital mode. For further details see the UN0060

IR3806x PMBus command set user note.

PVIN=VIN

VCC

The device utilizes the on-resistance of the low side

MOSFET (synchronous MOSFET) as current sense

element. This method enhances the converter’s

efficiency and reduces cost by eliminating the need

for external current sense resistor.

P1V8

UVOK

clkrdy

POR

Initialization

done

Enable

IR38064 includes two low R_ds(on)MOSFETs using

IR’s HEXFET technology. These are specifically

designed for high efficiency applications.

Vout

Figure 11: IR38064 Initialization sequence

DEVICE POWER-UP AND INITIALIZATION

ANALOG AND DIGITAL MODE OPERATION

During the power-up sequence, when Vin is brought

up, the internal LDO converts it to a regulated 5.2V

at Vcc. There is another LDO which further converts

this down to 1.8V to supply the internal digital

circuitry. An under-voltage lockout circuit monitors

the voltage of VCC pin and the P1V8 pin, and holds

The IR38064 has 2 7-bit registers that are used to

set the base I2C address and base PMBus address

of the device, as shown below in Table 1.

24

Rev 3.7

Mar 14, 2018

IR38064

Table 1: Registers used to set device base

address

6980

7870

+10

+11

+12

+13

+14

+15

Register

Description

8870

I2c_address[6:0]

The chip I2C address. An

address of 0 will disable

communication

9760

10700

11800

Pmbus_address[6:0]

The chip PMBus address.

An address of 0 will disable

communication.

The device will then respond to I2C/PMbus

commands sent to this address. This mode in which

digital communication to and from the device is

allowed following the MTP load sequence is referred

to as the digital mode of operation. However, if the

ADDR pin is left floating, the IR38064 disables

digital communication and will not respond to

commands sent over the bus. In fact, the 3 pins

used for digital communication are dual purpose

pins which get reconfigured for analog applications if

ADDR is left floating. Hence, in the analog mode,

the default configuration parameters loaded in to the

working registers from the MTP during the

initialization sequence cannot be modified on the fly,

and the device can be operated similar to an analog

only SupIRBuck such as IR3847.

In addition, a resistor may be connected between

the ADDR and LGND pins to set an offset from the

default preconfigured I2C address (0x10) and

PMBus address (0x40) in the MTP. Up to 16

different offsets can be set, allowing 16 IR38064

devices with unique addresses in a single system.

This offset, and hence, the device address, is read

by the internal 10 bit ADC during the initialization

sequence. It is recommended that

a

layout

placement be provided for a 10nF capacitor in

parallel with this offset resistor. On systems that

have more noise, this capacitor will help to prevent

the 10 bit ADC from incorrectly reading the offset

and calculating the wrong address offset.

BUS VOLTAGE UVLO

Table below provides the resistor values needed to

set the 16 offsets from the base address.

In the analog mode of operation or with the default

configuration, if the input to the Enable pin is derived

from the bus voltage by a suitably programmed

resistive divider, it can be ensured that the IR38064

does not turn on until the bus voltage reaches the

desired level as shown in Figure 12. Only after the

bus voltage reaches or exceeds this level and

voltage at the Enable pin exceeds its threshold

(typically 1.2V) IR38064 will be enabled. Therefore,

in addition to being a logic input pin to enable the

IR38064, the Enable feature, with its precise

threshold, also allows the user to override the

default 1V Under-Voltage Lockout for the bus

voltage (PVin). This is desirable particularly for high

output voltage applications, where we might want

the IR38064 to be disabled at least until PVin

exceeds the desired output voltage level.

Alternatively, the default 1 V PVin UVLO threshold

may be reconfigured/overridden using the VIN_ON

and VIN_OFF PMBus commands. It should be noted

that while the input voltage is also fed to an ADC

Table 2 : Address offset vs. External

Resistor(R_ADDR

)

ADDR Resistor

(Ohm)

Address Offset

499

+0

+1

+2

+3

+4

+5

+6

+7

+8

+9

1050

1540

2050

2610

3240

3830

4530

5230

6040

25

Rev 3.7

Mar 14, 2018

IR38064

through a 21:1 internal resistive divider, the digitized

input voltage is used only for the purposes of

reporting the input voltage through the READ_VIN

PMBUs command and has no impact on the bus

voltage UVLO, input overvoltage faults and input

undervoltage warnings, all of which are implemented

by using analog comparators to compare the input

PVin=Vin

Vcc

Vp

> 1.2V

voltage

programmed by the PMBus commands VIN_ON,

VIN_OFF, VIN_OV_FAULT_LIMIT and

to

the

corresponding

thresholds

EN

DAC2 (Reference DAC)

VIN_UV_WARN_LIMIT respectively. The bus

voltage reading as reported by READ_VIN has no

effect on the input feedforward function either.

Figure 14: Recommended startup for sequencing

operation (ratiometric or simultaneous)

12V

PVin=Vin

Vcc

10.2V

1 V

PVin

Vp

> 1.2V

Vcc

EN

> 1.2V

EN_UVLO_START

DAC2 (Reference DAC)

1.2V

EN

0V

Track_En

Figure 15: Recommended startup for memory

tracking operation (DDR-VTT)

DAC2 (Reference DAC)

Figure 12: Normal Start up, device turns on when

the bus voltage reaches 10.2V

Figure 13 shows the recommended startup

sequence for the normal (non-tracking, non-

sequencing) operation of IR38064, when Enable is

used as logic input. In this operating mode, a 100

kOhm resistor is connected from ¯T¯r¯a¯c¯k¯_¯E¯n¯ to

P1V8. Figure 14 shows the recommended startup

sequence for sequenced operation of IR38064 with

Enable used as logic input. For this mode

of operation also, a 100 kOhm resistor is connected

from ¯T¯r¯a¯c¯k¯_¯E¯n¯ to P1V8. Figure 15 shows the

recommended startup sequence for tracking

operation of IR38064 with Enable used as logic

input. For this mode of operation, ¯T¯r¯a¯c¯k¯_¯E¯n¯ should

be connected to LGND.

A resistor divider is used at EN pin from PVin to turn

on the device at 10.2V.

PVin=Vin

Vcc

Vp

> 1.2V

EN

DAC2 (Reference DAC)

PRE-BIAS STARTUP

Figure 13: Recommended startup for Normal

operation

IR38064 is able to start up into pre-charged output,

which prevents oscillation and disturbances of the

output voltage.

26

Rev 3.7

Mar 14, 2018

IR38064

The output starts in asynchronous fashion and

keeps the synchronous MOSFET (Sync FET) off

until the first gate signal for control MOSFET (Ctrl

FET) is generated. Figure 16 shows a typical Pre-

Bias condition at start up. The sync FET always

starts with a narrow pulse width (12.5% of a

switching period) and gradually increases its duty

cycle with a step of 12.5%, with 16 cycles at each

step, until it reaches the steady state value. Figure

17 shows the series of 16x8 startup pulses.

programmable delay is 0ms to 127 ms, and the

resolution is 1 ms. Further, the soft start time may be

configured from 1ms (as fast as possible) to 127 ms

with 1 ms resolution.

For more details on the PMBus commands

TON_DELAY and TON_RISE used to program the

startup sequence, please see UN0060 IR3806x

PMBus command set user note.

Note however, that a shorter Ton_Rise can lead to a

slight overshoot on the output voltage during startup.

Infineon recommends using a rise time that would

limit the soft start rate to <0.4mV/us. Also, it is

recommended that the system designer should

verify in the actual design that the selected rise time

keeps the overshoot within limits acceptable to the

system.

[V]

Vo

Pre-Bias

Voltage

[Time]

Figure 16: Pre-Bias startup

Internal Enable

...

HDRv

...

0.5V

...

87.5%

12.5%

16

25%

...

LDRv

...

Reference

DAC

End of

PB

...

16

Figure 17: Pre-Bias startup pulses

Vout

Ton_delay

Ton_rise

t₃

t₁

t₂

Figure 18: DAC2 (VREF) Soft start

SOFT-START (REFERENCE DAC RAMP)

IR38064 has an internal soft starting DAC to control

the output voltage rise and to limit the current surge

at the start-up. In the default configuration and in

analog mode, to ensure correct start-up, the DAC

sequence initiates only after power conversion is

enabled when the En/FCCM pin voltage exceeds its

undervoltage threshold, the PVin bus voltage

exceeds its undervoltage threshold and the contents

of the MTP have been fully loaded into the working

registers. In analog mode and in the default

configuration, the reference DAC signal linearly rises

to 0.5V in 2 ms. Figure 18 shows the waveforms

during soft start In digital mode, the reference DAC

soft-start may be delayed from time power

During the startup sequence the over-current

protection (OCP) and over-voltage protection (OVP)

are active to protect the device for any short circuit

or over voltage condition.

OPERATING FREQUENCY

In the analog mode, the switching frequency can be

programmed between 306kHz

–

1500kHz by

connecting an external resistor from R_tpin to LGnd.

This frequency is set during the initialization

sequence, when the 10 bit ADC reads the voltage at

the RT pin. It should be noted that after the

initialization sequence is complete, the ADC no

conversion is enabled.

The range for this

27 Rev 3.7

Mar 14, 2018

IR38064

longer reads the voltage at the ADC pin, so

changing the resistor on the fly after initialization will

not affect the switching frequency. Table 3 tabulates

the oscillator frequency versus R_t.

EXTERNAL SYNCHRONIZATION

IR38064 incorporates an internal phase lock loop

(PLL) circuit which enables synchronization of the

internal oscillator to an external clock. This function

is important to avoid sub-harmonic oscillations due

to beat frequency for embedded systems when

multiple point-of-load (POL) regulators are used. A

multi-function pin, Rt/Sync, is used to connect the

external clock. In the analog mode, if the external

clock is applied before the initialization sequence is

done, the internal ADC cannot read the value of the

RT resistor and hence, for proper operation, it is

mandatory that the external clock remains applied. If

the synchronization clock is then lost after

initialization, the IR38064 will treat this as a

symptom of a failure in the system and disable

power conversion. Therefore, for such applications,

where the switching frequency is always determined

by an external synchronization clock, the Rt/Sync

pin can be connected to the external clock signal

solely and no other resistor is needed. If the external

clock is applied after the initialization sequence, the

IR38064 treats this as an application where the

converter switching frequency is allowed to run at

the internal free-running frequency if the

synchronization clock is lost. Therefore, in the

analog mode, an external resistor from Rt/Sync pin

to LGnd is required to set the free-running

frequency. In the digital mode, the resistor is not

needed because the free running frequency is set in

an internal register. When an external clock is

applied to Rt/Sync pin after the converter runs in

steady state with its free-running frequency, a

transition from the free-running frequency to the

external clock frequency will happen. This transition

is to gradually make the actual switching frequency

equal to the external clock frequency, no matter

which one is higher. When the external clock signal

is removed from Rt/Sync pin, the switching

frequency is also changed to free-running gradually.

Table 3: Switching Frequency (F_s) vs. External

Resistor(R_t)

R_tResistor (Ohm)

499

F _s(kHz)

306

1050

356

1540

400

2050

444

2610

500

3240

550

3830

600

4530

706

5230

750

6040

800

6980

923

7870

1000

1091

1200

1333

1500

8870

9760

10700

11800

In the digital mode, the default switching frequency

is configured to be 607 kHz, and is programmable

from 250 kHz to 1500 kHz. The user can override

this using the FREQUENCY_SWITCH PMBus

command. In the digital mode of operation no

resistor is used or needed on the R_t/Sync pin. For

best telemetry accuracy, it is recommended that the

following switching frequencies be avoided: 250

kHz, 300 kHz, 400 kHz, 500 kHz, 600 kHz, 750 kHz,

800 kHz, 1 MHz, 1.2 MHz and 1.5 MHz. Instead,

Infineon suggests using the following values 251

kHz, 302 kHz, 403 kHz, 505 kHz, 607 kHz, 762 kHz,

813 kHz, 978 kHz, 1171 kHz and 1454 kHz

respectively.

28

Rev 3.7

Mar 14, 2018

IR38064

Synchronize to the

external clock

Free Running

Frequency

Return to free-

running freq

...

SW

Gradually change

Fs1

SYNC

Fs1

...

Fs2

Figure 20: Synchronizing a low impedance clock

in analog mode

Figure 19: Timing Diagram for Synchronization

to the external clock (Fs1>Fs2 or Fs1<Fs2)

It must be re-iterated that this is not a concern in

digital mode and the clock may be directly applied to

the Rt/Sync pin.

SHUTDOWN

An internal circuit is used to change the PWM ramp

slope according to the clock frequency applied on

Rt/Sync pin. Even though the frequency of the

external synchronization clock can vary in a wide

range, the PLL circuit will make sure that the ramp

amplitude is kept constant, requiring no adjustment

of the loop compensation. PVin variation also affects

the ramp amplitude, which will be discussed

separately in Feed-Forward section.

In the default configuration, IR38064 can be

shutdown by pulling the Enable pin below its 1.0V

threshold. During shutdown the high side and the

low side drivers are turned off. By default, the device

exhibits an immediate shutdown with no delay and

no soft stop.

Alternatively, in digital mode, the part may be

configured

OPERATION PMBus command as well.

to

allow

shutdown

using

the

It must be noted here that in analog mode, since

the voltage at the Rt/Sync pin is read by the ADC at

startup special care must be taken if a low

impedance system clock is used for synchronization

and is applied before the initialization sequence is

done. The circuit shown in Figure 20 below shows

CURRENT SENSING, TELEMETRY AND

OVER CURRENT PROTECTION

Current sensing for both, telemetry as well as

overcurrent protection is done by sensing the

voltage across the sync FET RDson. This method

enhances the converter’s efficiency, reduces cost by

eliminating a current sense resistor and any

minimizes sensitivity to layout related noise issues.

A novel, patented scheme allows reconstruction of

the average inductor current from the voltage

sensed across the Sync FET Rdson. It should be

noted here that it is this reconstructed average

inductor current that is digitized by the ADC and

used for output current reporting as well as for

overcurrent warning, the threshold for which may be

set using the IOUT_OC_WARN_LIMIT command.

how this may done using

a

diode-capacitor

combination. This couples the clock edges to the

Rt/Sync pin while not loading the Rt/SYNC pin with

the impedance of the synchronization clock, and

thus not affecting the Rt voltage read by the ADC at

startup.

29

Rev 3.7

Mar 14, 2018

IR38064

The current is reported in 1/16A resolution using the

READ_IOUT PMBus command.

Current Limit

Hiccup

The Over current (OC) fault protection circuit also

uses the voltage sensed across the R_DS(on)of the

Synchronous MOSFET; however, the protection

mechanism relies on a fast comparator to compare

the sensed signal to the overcurrent threshold and

does not depend on the ADC or reported current. In

the analog mode of operation, the current limit can

be set to one of three possible settings by floating

the OCSelect pin, or pulling it up to Vcc or pulling it

down to PGnd. The current limit scheme in the

IR38064 uses an internal temperature compensated

current source that has the same temperature

coefficient as the R_DS(on)of the Synchronous

MOSFET. As a result, the over-current trip threshold

remains almost constant over temperature.

Tblk_Hiccup

20 ms

IL

0

HDrv

...

0

LDrv

0

PGood

0

Figure 21: Timing Diagram for Current Limit

Hiccup

In the default configuration and in analog mode, if

the overcurrent detection trips the OCP comparator,

the IR38064 goes into a constant current limiting

mode for 8 cycles and then goes into hiccup mode.

The hiccup is performed by de-asserting the internal

Enable signal to the analog and power conversion

circuitry and holding it low for 20 ms.

Over Current Protection circuitry senses the inductor

current flowing through the Synchronous FET closer

to the valley point. The OCP circuit samples this

current for 75 ns typically after the rising edge of the

PWM set pulse which is an internal signal that has a

width of 12.5% of the switching period. The PWM

pulse that turns on the high side FET starts at the

falling edge of the PWM set pulse. This makes valley

current sense more robust as current is sensed

close to the bottom of the inductor downward slope

where transient and switching noise is low. This

helps to prevent false tripping due to noise and

transients.

Following this, the OCP signal resets and the

converter recovers. After every hiccup cycle, the

converter stays in this mode until the overload or

short circuit is removed. This behavior is shown in

Figure 21.

It should be noted that on some units, a false OCP

maybe experienced during IR38064 device start-up

due to noise. The part will ride through this false

OCP due to the pulse by pulse current limiting

feature of the IR38064 and successfully ramp to the

However,

PMBUS Clear_Faults

command after start-up to reset the PMBUS SAlert#

to a high and to clear the PMBUS status register for

faults.

The actual DC output current limit point will be

greater than the valley point by an amount equal to

approximately half of the peak to peak inductor

ripple current. The current limit point will be a

function of the inductor value, input voltage, output

voltage and the frequency of operation. On equation

1, I_LIMITis the value set when configuring the OCP

value. The user should account for the inductor

ripple to obtain the actual DC output current limit.

correct

recommends sending

output

voltage.

Infineon

a

Note that the IR38064 allows the user to override

the default overcurrent threshold using the PMBus

i

2

command

IOUT_OC_FAULT_LIMIT.

It

is

I_OCP I_LIMIT



(1)

recommended that the overcurrent threshold be

programmed to a minimum threshold of 16A and

that the threshold be a multiple of four for good

accuracy. While these devices will still offer

overcurrent protection for thresholds that are not

I_OCP

I_LIMIT

Δi

= DC current limit hiccup point

= Current Limit Valley Point

= Inductor ripple current

30

Rev 3.7

Mar 14, 2018

IR38064

multiples of four or limits below 16A, the thresholds

will not be as accurate.

IOUT_OC_FAULT_LIMIT

IL

Also,

using

the

PMBus

command

0

IOUT_OC_FAULT_RESPONSE, the part may be

configured to respond to an overcurrent fault in one

of two ways

HDrv

0

LDrv

0

CLK

Fs

1) Pulse by pulse current limiting for a programmed

number of switching cycles (8 to 64 cycles, in 8 cycle

resolution) followed by a latched shutdown.

0

OCP High

1

2

3

4

5

6

7

8

9

10

11

...

Internal

Enable

2) Pulse by pulse current limiting for a programmed

number (8 to 64 cycles, in 8 cycle resolution) of

switching cycles followed by hiccup.

Figure 23: Constant current limiting.

Figure 23 depicts a case where the overcurrent

condition happens when the converter is operating

at D>0.5 and the overcurrent response has been set

to Constant current operation through pulse by pulse

current limiting. In such a case, after 3 consecutive

overcurrent cycles are recognized, the pulse width is

dropped such that D=0.5 and then after 3 more

consecutive OCP cycles, to 0.25 and then finally to

0.125 at which it keeps running until the total OCP

count reaches the programmed maximum following

which the part enters hiccup mode. Conversely,

when the overcurrent condition disappears, the

pulse width is restored to its nominal value

gradually, by a similar mechanism in reverse; every

sequence of 4 consecutive cycles in which the

current is below the overcurrent threshold doubles

the duty cycle, so that D goes from 0.125 to 0.25,

then to 0.5 and finally to its nominal value.

The pulse-by-pulse or constant current limiting

mechanism is briefly explained below.

IOUT_OC_FAULT_LIMIT

IL

20 ms

0

HDrv

0

LDrv

0

CLK

Fs

0

OCP High

1

2

3

4

5

6

7

8

Internal

Enable

Figure 22: Pulse by pulse current limiting for 8

cycles, followed by hiccup.

In Figure 22 above, with the overcurrent response

set to pulse-by-pulse current limiting for 8 cycles

followed by hiccup, the converter is operating at

D<0.125 when the overcurrent condition occurs. In

such a case, no duty cycle limiting is applied.

DIE TEMPERATURE SENSING, TELEMETRY

AND THERMAL SHUTDOWN

IR38064 uses on die temperature sensing for

accurate

temperature

reporting

and

over

temperature detection. The READ_TEMEPRATURE

PMBus command reports this temperature in 1⁰C

resolution. The trip threshold is set by default to

145^oC. The default over temperature response of the

IR38064 (also the response in analog mode) is to

inhibit power conversion while the fault is present,

followed by automatic restart after the fault condition

is cleared. Hence, in the default configuration, when

trip threshold is exceeded, the internal Enable signal

31

Rev 3.7

Mar 14, 2018

IR38064

to the power conversion circuitry is de-asserted,

turning off both MOSFETs.

loop transfer function and requires a change in the

compensation network to optimally stabilize the loop.

Automatic restart is initiated when the sensed

temperature drops within the operating range. There

is a 25^oC hysteresis in the thermal shutdown

threshold.

FEED-FORWARD

Feed-Forward (F.F.) is an important feature,

because it can keep the converter stable and

preserve its load transient performance when PVin

varies over a wide range.

The PWM ramp

The default overtemperature threshold as well as

overtemperature response may be re-configured or

overridden using the OT_FAULT_LIMIT and

amplitude (Vramp) is proportionally changed with

PVin to maintain PVin/Vramp almost constant

throughout PVin variation range (as shown in Figure

24). Thus, the control loop bandwidth and phase

margin can be maintained constant. Feed-forward

function can also minimize impact on output voltage

from fast PVin change. The feedforward is disabled

OT_FAULT_RESPONSE

PMBus

commands

respectively. The devices support three types of

responses to an over-temperature fault:

1) Ignore

for PVin<4.7V. Hence, for PVin<4.7V,

a

re-

calculation of control loop parameters is needed for

re-compensation.

2) Inhibit when over temperature condition exists

and auto-restart when over temperature condition

disappears

16V

12V

5V

3) Latched shutdown.

PVin

0

REMOTE VOLTAGE SENSING

PWM Ramp

True differential remote sensing in the feedback loop

is critical to high current applications where the

output voltage across the load may differ from the

output voltage measured locally across an output

capacitor at the output inductor, and to applications

that require die voltage sensing.

Ramp Offset

0

Figure 24: Timing Diagram for Feed-Forward

(F.F.) Function

The RS+ and RS- pins of the IR38064 form the

inputs to a remote sense differential amplifier with

high speed, low input offset and low input bias

current which ensure accurate voltage sensing and

fast transient response in such applications.

LIGHT LOAD EFFICIENCY ENHANCEMENT

(AOT)

The IR38064 implements an Adaptive On Time

control or AOT scheme to improve light load

efficiency. It is based on a COT (Constant On Time)

control scheme with some novel advancements that

make the on-time during diode emulation adaptive

and dependent upon the pulse width in constant

frequency operation. This allows the scheme to be

combined with a PWM scheme, while providing

relatively smooth transition between the two modes

of operation. In other words, the switching regulator

can operate in AOT mode at light loads and

automatically switch to PWM at medium and heavy

loads and vice versa. Therefore, the regulator will

The input range for the differential amplifier is limited

to 1.5V below the VCC rail.

Therefore, for

applications in which the output voltage is more than

3V, it is recommended to use local sensing, or if

remote sensing is a must, then the output voltage

between the RS+ and RS-pins must be divided

down to less than 3V using a resistive voltage

divider. Practically, since designs for output voltage

greater than 2.555V require the use of a resistive

divider anyway, it is recommended that this divider

be placed at the input of the remote sense amplifier.

Please note, however, that this modifies the open

32

Rev 3.7

Mar 14, 2018

IR38064

benefit from the high efficiency of the AOT mode at

light loads, and from the constant frequency and fast

transient response of the PWM at medium to heavy

loads.

...

Vout

0

8/Fs delay

Diode

IL

Emulation

...

In order to enable this light load efficiency

enhancement mode in analog operation, the voltage

at the En/FCCM pin needs to be kept above 4V. In

digital mode, a MFR_SPECIFIC PMBus command

(MFR_FCCM) can be used to enable AOT operation

at light load.

0

Ton

...

SW

...

0

HDrv

0

LDrv

...

0

Shortly after the reference voltage has finished

ramping up, an internal circuit which is called the

“calibration circuit” starts operation. It samples the

Comp voltage (output of the error amplifier), digitizes

it and stores it in a register. There is a DAC which

converts the value of this register to an analog

voltage which is equal to the sampled Comp voltage.

At this time, the regulator is ready to enter AOT

mode if the load condition is appropriate. If the load

is so low that the inductor current becomes negative

before the next SW pulse, the operation can be

switched to AOT mode. The condition to enter AOT

is the occurrence of 8 consecutive inductor current

zero crossings in eight consecutive switching cycles.

If this happens, operation is switched to AOT mode

as shown in Figure 25. The inductor current is

sensed using the RDS_ON of the Sync-FET and no

direct inductor current measuring is required. In AOT

mode, just like COT operation, pulses with constant

width are generated and diode emulation is utilized.

This means that a pulse is generated and LDrv is

held on until the inductor current becomes zero.

Then both HDrv and LDrv remain off until the

voltage of the sense pin comes down and reaches

the reference voltage. At this moment the next pulse

is generated. The sense pin is connected to the

output voltage by a resistor divider which has the

same ratio as the voltage divider which is connected

to the feedback pin (Fb).

Reduced Switching

Frequency

1/Fs

Figure 25: Timing Diagram for Reduced

Switching Frequency and Diode Emulation in

Light Load Condition (AOT mode)

When the load increases beyond a certain value, the

control is switched back to PWM through either of

the following two mechanisms:

- If due to the increase in load, the output voltage

drops to 95% of the reference voltage.

-If Vsense remains below the reference voltage for

3 consecutive inductor current zero-cross events

It is worth mentioning that in AOT mode, when

Vsense comes down to reference voltage level, a

new pulse in generated only if the inductor current is

already zero. If at this time the inductor current

(sensed on the Sync-FET) is still positive, the new

pulse generation is postponed till the current decays

to zero. The second condition mentioned above

usually happens when the load is gradually

increased.

It should be noted that in tracking mode, AOT

operation is disabled and the IR38064 can only

operate in continuous conduction mode even at light

loads.

In digital mode, if the output voltage and hence the

reference voltage is commanded to a different

voltage, AOT is disabled during the transition. It is

enabled only after reference voltage finishes its

ramp (up or down) and the calibration circuit has

sampled and held the new Comp voltage.

33

Rev 3.7

Mar 14, 2018

IR38064

In general, AOT operation is more jittery and noisier

than FCCM operation, where the switching

frequency may vary from cycle to cycle, giving

increased Vout ripple. Therefore, it is recommended

to use FCCM mode of operation as far as possible.

5.5V <Vin<21V

Vo1

(master)

En/FCCM

PVin

Vin

Vp

Boot

SW

Vcc

SCL/OCSet

Vsns

RS+

PGood

OUTPUT VOLTAGE TRACKING AND

SEQUENCING

IR38064

master

PGood

RS-

ADDR

R_A

Rt/SYNC

RSo

Fb

SDA/IMON

IR38064 can accommodate user programmable

tracking and/or sequencing options using Vp,

¯T¯r¯a¯c¯k¯_¯E¯n¯ , Enable, and Power Good pins. The

error-amplifier (E/A) has two non-inverting inputs.

Ideally, the input with the lowest voltage is used for

regulating the output voltage and the other input is

ignored. In practice the voltage of the other input

should be about 200mV greater than the

low-voltage input so that its effects can completely

be ignored. Vp and ¯T¯r¯a¯c¯k¯_¯E¯n¯ are internally biased

to 5V via a high impedance path. For normal

operation, Vp is left floating and a 100 kOhm resistor

is connected from ¯T¯r¯a¯c¯k¯_¯E¯n¯ to P1V8. Therefore, in

normal operating condition, after Enable goes high,

DAC2 ramps up the output voltage until Vfb (voltage

of feedback/Fb pin) reaches about 0.5V.

SALERT/TMON

P1V8

Comp

LGnd

PGnd

Track_En

R_B

5.5V <Vin<21V

Vo1(master)

R_E

Vo2

(slave)

En/FCCM

PVin

Vin

Vp

Boot

R_F

Vcc

SW

SCL/OCSet

Vsns

RS+

PGood

IR38064

slave

PGood

RS-

ADDR

R_C

Rt/SYNC

SDA/IMON

RSo

Fb

SALERT/TMON

Comp

LGnd

PGnd

Track_En

P1V8

R_D

Tracking-mode operation is achieved by connecting

¯T¯r¯a¯c¯k¯_¯E¯n¯ to LGND. In tracking mode, Vfb always

follows Vp which means Vout is always proportional

to Vp voltage (typical for DDR/Vtt rail applications).

The effective Vp variation range is 0V~2.555V.

Figure 26: Application Circuit for Simultaneous

and Ratiometric Sequencing of two Manhattan

devices

Tracking and sequencing operations can be

implemented to be simultaneous or ratiometric (refer

to Figure 27 and Figure 28). Figure 26 shows typical

circuit configuration for sequencing operation. With

this power-up configuration, the voltage at the Vp pin

of the slave reaches 0.5V before the Fb pin of the

master. If R_E/R_F=R_C/R_D, simultaneous startup is

achieved. That is, the output voltage of the slave

follows that of the master until the voltage at the Vp

pin of the slave reaches 0.5 V. After the voltage at

the Vp pin of the slave exceeds 0.5V, the internal

0.5V reference of the slave dictates its output

voltage. In reality the regulation gradually shifts from

Vp to internal DAC2. The circuit shown in Figure 26

can also be used for simultaneous or ratiometric

tracking operation if the ¯T¯r¯a¯c¯k¯_¯E¯n¯ pin of the slave

is connected to LGND.

In sequencing mode of operation (simultaneous or

ratiometric), a 100 kOhm resistor is connected from

¯T¯r¯a¯c¯k¯_¯E¯n¯ to P1V8 and Vp is kept to ground level

until DAC2 signal reaches the final value. Then Vp is

ramped up and Vfb follows Vp. When Vp>DAC2

(0.5V in analog mode or default configuration) the

error-amplifier switches to DAC2 and the output

voltage is regulated with DAC2. The final Vp voltage

after sequencing startup should between 0.7V ~ 5V.

34

Rev 3.7

Mar 14, 2018

IR38064

Table 4: Required Conditions for Simultaneous /

Ratiometric Tracking and Sequencing (Figure 26)

Table 4 summarizes the required conditions to

achieve simultaneous / ratiometric tracking or

sequencing operations.

Track_

Enable

(Slave)

Vp

Required

Condition

Operating

Mode

Vcc

Normal

(Non-

sequencing,

Non-tracking)

Simultaneous

Sequencing

100

kOhm to

P1V8

Reference DAC=0.5V

Enable (slave)

Floating

―

1.2V

Soft Start (slave)

100

kOhm to

P1V8

Ramp

up from

0V

R_A/R_B>R_E/

R_F=R_C/R_D

Vo1 (master)

Ratiometric

Sequencing

100

kOhm to

P1V8

Ramp

up from

0V

R_A/R_B>R_E/

R_F>R_C/R_D

(a)

(b)

Vo2 (slave)

Vo1 (master)

Simultaneous

Tracking

Ramp

up from

0V

R_E/R_F

=R_C/R_D

0V

Vo2 (slave)

Ratiometric

Tracking

Ramp

up from

0V

R_E/R_F

>R_C/R_D

Figure 27: Typical waveforms for sequencing

mode of operation: (a) simultaneous, (b)

ratiometric

¯T¯R¯A¯¯C¯K¯_¯E¯¯N¯

Vcc

This pin is used to choose between tracking or non-

tracking mode of operation. To enable operation in

tracking mode, this pin must be tied to LGnd. For

non-tracking or sequencing mode, a 100 kOhm

resistor is connected from this pin to P1V8.

Track_En=0V (slave)

Enable (slave)

1.2V

Soft Start (slave)

Vo1 (master)

Vo2 (slave)

OUTPUT VOLTAGE SENSING, TELEMETRY

AND FAULTS

(a)

In the IR38064, the voltage sense and regulation

circuits are decoupled, enabling ease of testing as

well as redundancy. In order to do this, IR38064

uses the sense voltage at the dedicated Vsns pin for

output voltage reporting (in 1/256 V resolution, using

the READ_VOUT PMBus command) as well as for

Vo1 (master)

Vo2 (slave)

(b)

Figure 28: Typical waveforms in tracking mode

of operation: (a) simultaneous, (b) ratiometric

35

Rev 3.7

Mar 14, 2018

IR38064

power good detection and output overvoltage

protection.

Fault DAC

V

0.5

0

Power good detection and output overvoltage

detection rely on fast analog comparator circuits,

whereas overvoltage warnings as well as

undervoltage faults and warnings rely on comparing

the digitized Vsns to the corresponding thresholds

Reference DAC

V

0.5

0

Vsns

0.45V

0.42V

0

programmed

using

PMBus

commands

VOUT_OV_WARN_LIMIT,VOUT_UV_FAULT_LIMIT

and VOUT_UV_WARN_LIMIT respectively.

PGD

Power Good Output

0

The Vsns voltage is an input to the window

comparator with default upper and lower thresholds

of 0.45V and 0.42V respectively. PGood signal is

high whenever Vsns voltage is within the PGood

comparator window thresholds. The PGood pin is

open drain and it needs to be externally pulled high.

High state indicates that output is in regulation. It

should be noted, that in digital mode, the Power

Good thresholds may be changed through the

POWER_GOOD_ON and POWER_GOOD_OFF

commands, which set the rising and falling PGood

thresholds respectively. However, when no resistive

divider is used, such as for output voltages lower

than 2.555V, the Power Good thresholds must be

programmed to within 630 mV of the output voltage,

failing which the effective power good threshold

changes from an absolute threshold to one that

tracks the output voltage with a 630 mV offset.

160us

Figure 29: Non-sequenced, Non-tracking Startup

0.4V

0.3V

Vp

0

1.2*Vp

Vsns

0.9*Vp

0

PGD

0

Figure 30: Vp Tracking (¯T¯r¯a¯c¯k¯_¯E¯n¯ = 0V)

The threshold is set differently in different operating

modes and the result of the comparison sets the

PGood signal. Figure 29, Figure 30 and Figure 31

show the timing diagram of the PGood signal in

different operating modes. The Vsns signal is also

used by OVP comparator to detect an output over

voltage condition. By default, the PGood signal will

assert as soon as the Vsns signal enters the

regulation window. In digital mode, this delay is

programmable from 0 to 10ms with a 1 ms

resolution, using the MFR_TPGDLY command.

36

Rev 3.7

Mar 14, 2018

IR38064

until a reset is performed by cycling either Vcc or

Enable, or in the digital mode, using the

OPERATION command. IR38064 allows the user to

reconfigure this response by the use of the

VOUT_OV_FAULT_RESPONSE PMBus command.

In addition to the default response described above,

this command can be used to configure the device

such that Vout overvoltage faults are ignored and

the converter remains enabled. (however, they will

still be flagged in the STATUS_REGISTERS and by

¯S¯A¯le¯r¯t ). For further details on the corresponding

PMBus commands related to OVP, please refer to

UN0060 IR3806x PMBus command set user note.

Reference DAC

0.5V

0

(1V<Vp<5V)

0.5V

Vp

0

0.605V

Vsns

0.45V

0

PGD

0

Vsns voltage is set by an external resistive voltage

divider connected to the output.

Figure 31: Vp Sequencing (100 kOhm from

¯T¯r¯a¯c¯k¯_¯E¯n¯ to P1V8)

DAC1+OV_OFFSET_DAC

Vout

DAC1

hysteresis

0

Over-Voltage Protection (OVP)

HDrv

0

Over-voltage protection in IR38064 is achieved by

comparing sense pin voltage Vsns to a configurable

overvoltage threshold.

LDrv

0

For non-tracking operation, in analog mode, or in

digital mode using the default configuration, the OVP

threshold is set to 0.605V; for tracking operation, it is

set at 1.2*Vp.

Comp

0

PGood

0

200 ns

For non-tracking operation, in digital mode, the OVP

threshold may be reprogrammed to within 655 mV of

the output voltage (for output voltages lower than

2.555V, without any resistive divider on the Fb pin),

Figure 32: Timing Diagram for OVP in non-

tracking mode

using

the

VOUT_OV_FAULT_LIMIT

PMBus

MINIMUM ON TIME CONSIDERATIONS

command. For an OVP threshold programmed to be

more than 655 mV greater than the output voltage,

the effective OV threshold ceases to be an absolute

value and instead tracks the output voltage with a

655 mV offset.

The minimum ON time is the shortest amount of time

for the Control FET to be reliably turned on. This is a

very critical parameter for low duty cycle, high

frequency applications. In the conventional

approach, when the error amplifier output is near the

bottom of the ramp waveform with which it is

compared to generate the PWM output, propagation

delays can be high enough to cause pulse skipping,

and hence limit the minimum pulse width that can be

realized. Moreover, in the conventional approach,

the bottom of the ramp often presents a high gain

region to the error amplifier output, making the

When Vsns exceeds the over voltage threshold, an

over voltage trip signal asserts after 200ns (typ.)

delay. The default response is that the high side

drive signal HDrv is latched off immediately and

PGood flags are set low. The low side drive signal is

kept on until the Vsns voltage drops 5% below the

overvoltage threshold. HDrv remains latched off

37

Rev 3.7

Mar 14, 2018

IR38064

modulator more susceptible to noise and requiring

the use of lower control loop bandwidth to prevent

noise, jitter and pulse skipping.

Therefore, at the maximum recommended input

voltage 21V and minimum output voltage, the

converter should be designed at a switching

frequency that does not exceed 476 kHz.

Conversely, for operation at the maximum

recommended operating frequency (1.5 MHz) and

minimum output voltage (0.5V), the input voltage

(PVin) should not exceed 6.7V, otherwise pulse

skipping may happen.

Infineon has developed a proprietary scheme to

improve and enhance the minimum pulse width

which minimizes these delays and hence, allows

stable operation with pulse-widths as small as 35ns.

At the same time, this scheme also has greater

noise immunity, thus allowing stable, jitter free

operation down to very low pulse widths even with a

high control loop bandwidth, thus reducing the

required output capacitance.

VOLTAGE REFERNCE

The default reference voltage of the error amplifier is

0.5V for both digital and analog mode. The default

voltage scale loop setting is 1.

Any design or application using IR38064 must

ensure operation with a pulse width that is higher

than the minimum on-time and at least 50 ns of on-

time is recommended in the application. This is

necessary for the circuit to operate without jitter and

pulse-skipping, which can cause high inductor

current ripple and high output voltage ripple.

MAXIMUM DUTY RATIO

A certain off-time is specified for IR38064. This

provides an upper limit on the operating duty ratio at

any given switching frequency. The off-time remains

at a relatively fixed ratio to switching period in the

low and mid frequency range, while at higher

frequencies, the maximum duty ratio at which

D

V_out

(2)

t_on



F_sPVin  F_s

IR38064 can operate shows

a corresponding

In any application that uses IR38064, the following

condition must be satisfied:

decrease. Figure 33 shows a plot of the maximum

duty ratio vs. the switching frequency with built in

input voltage feed forward mechanism.

(3)

(4)

t_on(min) t_on

V_out

PV_in F_s

V_out

t_on(min)



PV_in F_s

(5)

t_on(min)

The minimum output voltage is limited by the

reference voltage and hence V_out(min)= 0.5V.

Therefore, for V_out(min)= 0.5V,

V_out

PV_in F_s

(6)

t_on(min)

Figure 33: Maximum duty cycle vs. switching

frequency

0.5V

PV_in F_s

10 V/μs

50ns

38

Rev 3.7

Mar 14, 2018

IR38064

Programming the frequency

DESIGN EXAMPLE

The device is programmed with a default switching

frequency=607 kHz. This value may be read using the

FREQUENCY_SWITCH PMBus command.

The following example is a typical application for the

IR38064.

PV_in= Vin=12V

F_s= 607 kHz

V_o= 1.2V

If operating in analog mode, the timing resistor Rt

should be chosen to be 3.83K

I_o= 35A

Output Voltage Programming

Ripple Voltage = ± 1% * V_o

ΔV_o= ± 5% * Vo (for 40% load transient)

Digital mode operation

The IR38064 offers flexibility for programming the

output voltage. Two distinct methods of programming

the Output voltage are available and the appropriate

one should be chosen depending upon if the mode of

operation is analog or digital.

Enabling the IR38064

As explained earlier, in analog mode, the precise

threshold of the Enable lends itself well to

implementation of a UVLO for the Bus Voltage as

shown in Figure 34.

In the analog mode of operation, the output voltage is

programmed by the reference voltage and an external

resistive divider. The FB pin is the inverting input of

the error amplifier, which is internally referenced to

VREF.

Vin

The divider ratio is set such that the voltage at the

VREF pin equals that at the FB pin when the output is

at its desired value. When an external resistor divider

is connected to the output as shown in Figure 35, the

output voltage is defined by using the following

equation:

IR38064

R1

Enable

R2

Figure 34: Using Enable pin for UVLO

implementation





R



⁵

V_oV_ref 1

(9)







R₆



For a typical Enable threshold of V_EN= 1.2 V









V_ref





(10)

R₆ R₅

R₂

V_oV_ref

PV_in(min)

R₂ R

V_EN1.2

(7)

(8)

R  R₂

1

Vo

V_EN

IR38064

FB

R5

R6

¹PV_in(min)V_EN

For PV_{in (min)}=9.2V, R₁=49.9K and R₂=7.5K ohm is a

good choice.

Alternatively, if used in digital mode, the PVin UVLO

thresholds may be programmed to suitable values

such as 9V and 8V, through the VIN_ON and

VIN_OFF PMBus commands or through the

appropriate configuration registers respectively.

Figure 35: Typical application of the IR38064 for

programming the output voltage

However, in the digital mode of operation, the Vout

related PMBus commands and the Vout related

registers allow the user to program the output voltage

directly, by changing the reference voltage (up to a

maximum of 2.555V) in response to the commanded

39

Rev 3.7

Mar 14, 2018

IR38064

voltage. Therefore, no resistive divider is necessary

for this design since Vo=1.2V.

The ripple currents generated during the on time of

the control FETs should be provided by the input

capacitor. The RMS value of this ripple for each

channel is expressed by:

Bootstrap Capacitor Selection

To drive the Control FET, it is necessary to supply a

gate voltage at least 4V greater than the voltage at the

SW pin, which is connected to the source of the

Control FET. This is achieved by using a bootstrap

configuration, which comprises the internal bootstrap

diode and an external bootstrap capacitor (C1). The

operation of the circuit is as follows: When the sync

FET is turned on, the capacitor node connected to SW

is pulled down to ground. The capacitor charges

towards V_ccthrough the internal bootstrap diode

(Figure 36), which has a forward voltage drop V_D. The

voltage V_cacross the bootstrap capacitor C1 is

approximately given as:

I_RMS I_o D



1 D



(13)

(14)

V_o

D 

PV

in

Where:

D is the Duty Cycle

I_RMSis the RMS value of the input capacitor

current.

Io is the output current.

I_o=35A and D = 0.1, the I_RMS= 10.5A.

Ceramic capacitors are recommended due to their

peak current capabilities. They also feature low ESR

and ESL at higher frequency which enables better

efficiency. For this application, it is advisable to have

V_cV_ccV_D

(11)

When the control FET turns on in the next cycle, the

capacitor node connected to SW rises to the bus

voltage PV_in. However, if the value of C1 is

appropriately chosen, the voltage V_cacross C1

remains approximately unchanged and the voltage at

the Boot pin becomes:

4x22uF,

25V

ceramic

capacitors,

C3216X5R1E226M160AB from TDK. In addition to

these, although not mandatory, a 1x330uF, 25V SMD

capacitor EEV-FK1E331P from Panasonic may also

be used as a bulk capacitor and is recommended if

the input power supply is not located close to the

converter.

V_Boot PV V_ccV_D

(12)

in

Cvin

PVIN

Inductor Selection

+ V_D

-

Boot

Inductors are selected based on output power,

operating frequency and efficiency requirements. A

low inductor value causes large ripple current,

resulting in the smaller size, faster response to a load

transient but poor efficiency and high output noise.

Generally, the selection of the inductor value can be

reduced to the desired maximum ripple current in the

inductor (Δi). The optimum point is usually found

between 20% and 50% ripple of the output current.

For the buck converter, the inductor value for the

desired operating ripple current can be determined

using the following relation:

V

cc

+

Vc

-

C1

SW

L

IR38064

PGnd

Figure 36: Bootstrap circuit to generate Vc voltage

A bootstrap capacitor of value 0.1uF is suitable for

most applications.

i

t

1

PV V_o L ;t  D

in

F

s

V_o

Input Capacitor Selection

L  PV V 

_o

(15)



in

PV i F

in

s

40

Rev 3.7

Mar 14, 2018

IR38064

The goal for this design is to meet the voltage ripple

requirement in the smallest possible capacitor size.

Therefore it is advisable to select ceramic capacitors

due to their low ESR and ESL and small size. Ten of

Where:

PV_in= Maximum input voltage

V₀= Output Voltage

TDK

C2012X5R0J476M

(47uF/0805/X5R/6.3V)

Δi = Inductor Ripple Current

F_s= Switching Frequency

Δ_t= On time for Control FET

capacitors is a good choice.

It is also recommended to use a 0.1µF ceramic

capacitor at the output for high frequency filtering.

D

= Duty Cycle

If Δi ≈ 34%*I_o, then the inductor is calculated to be

0.15μH. Select L=0.15μH, HCB138380D-151, from

Delta which provides a compact, low DCR inductor

suitable for this application. The selected inductor

Feedback Compensation

The IR38064, while allowing flexibility and

configurability through the digital wrapper of the

PMBus interface, still employs a high performance

voltage mode control engine. The control loop

is a single voltage feedback path including error

amplifier and a PWM comparator. To achieve fast

transient response and accurate output regulation, a

compensation circuit is necessary. The goal of the

compensation network is to provide a closed-loop

value gives

current=11.9A.

a

peak-to-peak inductor ripple

Output Capacitor Selection

The voltage ripple and transient requirements

determine the output capacitors type and values. The

criterion is normally based on the value of the

Effective Series Resistance (ESR). However the

actual capacitance value and the Equivalent Series

Inductance (ESL) are other contributing components.

These components can be described as:

transfer

function

with

the

highest

0 dB crossing frequency and adequate phase margin

(greater than 45^o).

The output LC filter introduces a double pole, -

40dB/decade gain slope above its corner resonant

frequency, and a total phase lag of 180^o. The resonant

frequency of the LC filter is expressed as follows:

V_o V_o_{ } V_o_{ } V_o(C)

ESR

ESL

V_0(ESR) I_L ESR

1

F_LC

(17)

2  L_oC_o

Figure 37 shows gain and phase of the LC filter. Since

we already have 180^ophase shift from the output filter

alone,

PV V

_o





in

V_0(ESL)



 ESL





L



I_L

8C_o F_s

V_0(C)



(16)

the system runs the risk of being unstable.

Phase

Gain

Where:

ΔV₀= Output Voltage Ripple

ΔI_L= Inductor Ripple Current

0⁰

0dB

-40dB/Decade

Since the output capacitor has a major role in the

overall performance of the converter and determines

the transient response, selection of the capacitor is

critical. The IR38064 can perform well with all types of

capacitors.

-90⁰

-180⁰

Frequency

F_LC

Figure 37: Gain and Phase of LC filter

As a rule, the capacitor must have low enough ESR to

meet output ripple and load transient requirements.

41

Rev 3.7

Mar 14, 2018

IR38064

The IR38064 uses a voltage-type error amplifier with

high-gain (90dB) and high-bandwidth (30MHz). The

output of the amplifier is available for DC gain control

and AC phase compensation.

The (s) indicates that the transfer function varies as a

function of frequency. This configuration introduces a

gain and zero, expressed by:

R₃

(20)

H(s) 

The error amplifier can be compensated either in type

II or type III compensation.

R₅

1

(21)

F_z

Local feedback with Type II compensation is shown in

Figure 38.

2  R₃C₃

First select the desired zero-crossover frequency (F_o):

This method requires that the output capacitor have

enough ESR to satisfy stability requirements. If the

output capacitor’s ESR generates a zero at 5kHz to

50kHz, the zero generates acceptable phase margin

and the Type II compensator can be used.

F  F_ESRand F  (1/5 ~1/10) F

(22)

o

s

Use the following equation to calculate R3:

V_osc F  F_ESR R₅

o

(23)

R₃

PV  F_L²_C

in

The ESR zero of the output capacitor is expressed as

follows:

Where:

PV_in= Maximum Input Voltage

V_osc=Effective amplitude of the oscillator ramp

F_o= Crossover Frequency

F_ESR= Zero Frequency of the Output Capacitor

F_LC= Resonant Frequency of the Output Filter

R₅= Feedback Resistor

1

(18)

F_ESR



2  ESRC_o

V^OUT

Z_IN

C_POLE

C3

R3

R5

Zf

To cancel one of the LC filter poles, place the zero

before the LC filter resonant frequency pole:

Fb

E/A

Ve

F_Z 75% F_LC

R6

Comp

1

VREF

F_Z 0.75

(24)

Gain(dB)

2 L_oC_o

H(s) dB

Use equation (22), (23) and (24) to calculate C3.

One more capacitor is sometimes added in parallel

with C3 and R3. This introduces one more pole which

is mainly used to suppress the switching noise.

Frequency

F_POLE

F_Z

Figure 38: Type II compensation network and its

asymptotic gain plot

The additional pole is given by:

1

(25)

F_p

C₃C_POLE

The transfer function (V_e/V_out) is given by:

2  R₃

C₃ C_POLE

Z _f

V_e

1 sR₃C₃

sR₅C₃

The pole is set to one half of the switching frequency

 H(s)  

 

(19)

which results in the capacitor C_POLE

:

V_out

Z_IN

42

Rev 3.7

Mar 14, 2018

IR38064

The compensation network has three poles and two

zeros and they are expressed as follows:

1

(26)

C_POLE





1

  R₃ F_S

  R₃ F_S

C₃

F_P1 0

F_P2

(28)

(29)

For a general unconditional stable solution for any

type of output capacitors with a wide range of ESR

values, we use a local feedback with a type III

1

2  R₄C₄

compensation

network.

The

typically

used

1

(30)

F_P3



compensation network for voltage-mode controller is

shown in Figure 39.





2  R₃C₂

C₂C₃

C₂ C₃





2  R₃





V

OUT

Z_IN

C2

C3

1

C4

R4

R3

(31)

(32)

F_Z1

F_{Z 2}

R5

R6

2  R₃C₃

Z_f

1



2 C₄



R₃ R₅



2 C₄ R₅

Fb

Ve

E A

/

Comp

Cross over frequency is expressed as:

V

REF

PV

1

(33)

Gain (dB)

F  R₃C₄ ⁱⁿ

o

V_osc2  L_oC_o

Based on the frequency of the zero generated by the

output capacitor and its ESR, relative to the crossover

frequency, the compensation type can be different.

Table 5 shows the compensation types for relative

locations of the crossover frequency.

|H(s)| dB

Frequency

F

P₃

P₂

Z₁

Z₂

Figure 39: Type III Compensation network and its

asymptotic gain plot

Table 5: Different types of compensators

Compensator

Type

Typical Output

Capacitor

F_ESRvs F_O

Again, the transfer function is given by:

F_LC< F_ESR< F_O<

F_S/2

Type II

Type III

Electrolytic

Z _f

V_e

SP Cap,

Ceramic

 H(s)  

F_LC< F_O< F_ESR

V_out

Z_IN

The higher the crossover frequency is, the potentially

faster the load transient response will be. However,

the crossover frequency should be low enough to

allow attenuation of switching noise. Typically, the

control loop bandwidth or crossover frequency (F_o) is

selected such that:

By replacing Z_inand Z_f, according to Figure 39, the

transfer function can be expressed as:



1 sR₃C₃





1 sC₄



R₄ R₅



H(s)  













C₂C₃





sR₅



C₂ C₃



1 sR



1 sR C₄



3

4

C₂ C₃







F 



1/5 ~1/10 *F



o

s

(27)

43

Rev 3.7

Mar 14, 2018

IR38064

The DC gain should be large enough to provide high

DC-regulation accuracy. The phase margin should be

greater than 45^ofor overall stability.

1 sin 

1sin 

F_P2 F



425.35 kHz

o

Select:

In this design, we target F_o= 75 kHz.

The specifications

F_Z1 0.5 F_{Z 2} ^{6.61 kHz and}

PV_in= 12V

V_o= 1.2V

F_P3 0.5 F  300 kHz

s

V_osc= 1.357 (This is a function of PVin, duty cycle

and

switching

frequency.

Infineon’s

Select C₄= 2.2nF.

SupIRBuck online design tool can help the

user in accounting for this operating point

dependency of the effective oscillator ramp

amplitude)

Calculate R₃, C₃and C₂:

2  F  L_oC_oV_osc

o

V_ref= 1.2V

L_o= 0.15 µH

C_o= 10 x 47µF, ESR≈3mΩ each

; R₃= 1.18 kΩ,

R₃

C₄ PV

in

Select: R₃= 1.21 kΩ

It must be noted here that the value of the

capacitance used in the compensator design must be

the small signal value. For instance, the small signal

capacitance of the 47µF capacitor used in this design

is 34µF at 1.2 V DC bias and 600 kHz frequency. It is

this value that must be used for all computations

related to the compensation. The small signal value

may be obtained from the manufacturer’s datasheets,

design tools or SPICE models. Alternatively, they may

also be inferred from measuring the power stage

transfer function of the converter and measuring the

double pole frequency F_LCand using equation

1

; C₃= 20.12 nF, Select: C₃= 22

; C₂= 449.6 pF, Select: C₂=

C₃

2  F_Z1 R₃

nF

1

C₂

2  F_P3 R₃

390 pF

Calculate R₄, R₅and R₆:

(22) to compute the small signal C_o.

1

R₄

; R₄= 170 Ω, Select R₄= 182

These result to:

2 C₄ F_P2

F_LC= 22.29 kHz

F_ESR= 1220.7 kHz

Ω

F_s/2 = 300 kHz

Select crossover frequency F₀=75 kHz

1

R₅

; R₅= 5.3kΩ, Select R₅= 5.62

2 C₄ F_{Z 2}

Since F_LC<F₀<Fs/2<F_ESR, Type III is selected to place

kΩ

the pole and zeros.

In digital mode, R6 is not necessary.

Detailed calculation of compensation Type III:

Setting the Power Good Threshold

Desired Phase Margin Θ = 70°

In

digital

mode,

the

PMBus

commands

POWER_GOOD_ON and POWER_GOOD_OFF, or

the corresponding registers may be used to adjust the

power good thresholds to within 630 mV of the output

1 sin

1 sin

F_{Z 2} F



13.22 kHz

o

44

Rev 3.7

Mar 14, 2018

IR38064

voltage (for output voltages <2.555V). In this design,

the power good thresholds have been set such that

the Power Good is asserted when the output voltage

rises above 1.074V, and is de-asserted when the

output voltage falls below 1V, giving 74mV of

hysteresis.

LGnd. In this design, R_ADDRwas chosen to be 499Ω,

to have no offset from the base i2c/PMBus address.

Further, Infineon’s PowIRCenter USB-to-I2C dongles

have their SCL and SDA lines internally pulled up to

3.3V. Therefore, although this design provides

placeholders for the bus pullups, they may be left

unpopulated if the PowIRCenter dongle is used. The

¯S¯A¯le¯r¯t line is pulled up to Vcc with a 4.99K resistor.

In this design, a power good assertion delay of 0 ms

was programmed. Therefore, the PGood signal

asserts as soon as the output voltage rises above the

power good assertion threshold, and remains

asserted until the output voltage drops below the

power good de-assertion threshold. There is a fixed

160us delay for power good de-assertion. It should be

noted, however, that an overvoltage condition or any

fault condition that causes a shutdown will lead to

PGood de-assertion without any delay.

Selecting Power Good Pull-Up Resistor

The PGood is an open drain output and require pull

up resistors to VCC. The value of the pull-up resistors

should limit the current flowing into the PGood pin to

less than 5mA. A typical value used is 4.99kΩ.

Setting the Overvoltage Threshold

In digital mode, the overvoltage protection threshold

may be programmed using the PMBus command

VOUT_OV_FAULT_LIMIT, or the corresponding

configuration registers, to within 655 mV of the output

voltage (for output voltages <2.555V). In this design,

the threshold has been set to 1.5V. The fault response

has been set to shutdown, so that an overvoltage

condition will cause the part to shutdown with the sync

FET remaining on until the voltage drops 5% below

the overvoltage threshold. In analog

Setting the Overcurrent Threshold

For this 35A design, the overcurrent protection

threshold has been programmed such that the part

goes into a hiccup current limiting mode when the

inductor valley current exceeds 46A, or when the load

current exceeds ~52A.

Communicating on the I2C/PMBus

In order to enable digital mode, as explained earlier, a

resistor needs to be connected from the ADDR pin to

45

Rev 3.7

Mar 14, 2018

IR38064

Vin=12V

R₁

49.9 K

C_PVIN=1X330uF/25V +

4X22uF/1206/X5R/16V

R₂

7.5 K

En/

FCCM

C_boot=0.1uF/0603/

X7R/50V

Vp

PVin

Vin

Boot

Vo

Vcc/

LDO_out

SW

Lo

0.15uH

C_VCC=1X10uF/

0805/X5R/10V

Vsns

R_PG

4.99 K

PGood

RS+

RS-

C_o=10X47uF/

0805/X5R/6.3V

PGood

Rt/SYNC

P1V8

R5

5.62 K

RSo

RTRACK

100 K

R4

182

C4

2.2nF

C_P1V8=1X10uF/

0603/X5R/10V

Fb

C3

22 nF

Track_EN

ADDR

R3

1.21 K

Comp

PGnd

LGnd

CADDR

(optional)

10 nF

RADDR

499

C2

390 pF

Figure 40: Application circuit for a single supply, 12V to 1.2V, 35A Point of Load Converter

46

Rev 3.7

Mar 14, 2018

IR38064

TYPICAL OPERATING WAVEFORMS

Vin = PVin = 12V, Vout = 1.2V, Iout = 0-35A, Room Temperature, No Air Flow

Figure 41: PV_inStart up at 35A Load

Figure 42:PV_inStart up at 35A Load

Ch₁:P_Vin, Ch₂:V_out, Ch₃:P_Good,Ch₄:V_cc

Ch₁:P_Vin, Ch₂:V_out, Ch₃:P_Good, Ch₄:Enable

Figure 43:Operation 80,Turn ON without margining, 35A

load

Figure 44: Operation 00, Immediate OFF, 35A

load

Ch₁:P_Vin, Ch₂:V_out, Ch₃:P_Good, Ch₄:Enable

Figure 45: Inductor node at 35A load

Figure 46: Output voltage ripple at 35A load

Ch₃:SW node

Ch₂:V_out

47

Rev 3.7

Mar 14, 2018

IR38064

TYPICAL OPERATING WAVEFORMS

Vin = PVin = 12V, Vout = 1.2V, Iout = 0-35A, Room Temperature, No Air Flow

Figure 47: 0.35V Prebias voltage startup at 0A

Figure 48: Short-circuit recovery (Hiccup) at 35A

load

Ch₂:V_out, Ch₃:P_Good

Ch2:V_out, Ch3:P_Good

48

Rev 3.7

Mar 14, 2018

IR38064

TYPICAL OPERATING WAVEFORMS

Vin = PVin = 12V, Vout = 1.2V, Iout = 0-35A, Room Temperature, No Air Flow

Figure 49: Transient Response, 3.5A to 14A step (2.5A/us)

Ch₁:V_out, Ch₄:I_out

Figure 50: Transient Response, 24.5A to 35A step (2.5A/us)

Ch₁:V_out, Ch₄:I_out

49

Rev 3.7

Mar 14, 2018

IR38064

TYPICAL OPERATING WAVEFORMS

Vin = PVin = 12V, Vout = 1.2V, Iout = 0-35A, Room Temperature, No Air Flow

Figure 51: Bode Plot at 0A load

Bandwidth = 81.33kHz, Phase Margin = 55.9^o, Gain Margin = 13.9dB

Figure 52: Bode Plot at 35A load

Bandwidth = 73.3kHz, Phase Margin = 55.8^o, Gain Margin = 15.4dB

50

Rev 3.7

Mar 14, 2018

IR38064

TYPICAL OPERATING WAVEFORMS

Vin = PVin = 12V, Vout = 1.2V, Iout = 0-35A, Room Temperature, No Air Flow

Figure 53: Efficiency versus load current

Figure 54: Power loss versus load current

51

Rev 3.7

Mar 14, 2018

IR38064

TYPICAL OPERATING WAVEFORMS

Vin = PVin = 12V, Vout = 1.2V, Iout = 0-35A, Room Temperature, No Air Flow

Figure 55: Thermal Image of the board at 35A load

IR38064: 120.2^oC, inductor: 89.89^oC, Ambient:29.8^oC

52

Rev 3.7

Mar 14, 2018

IR38064

Figure 56: PMBus Command Summary for the 1.2V design

53

Rev 3.7

Mar 14, 2018

IR38064

I2C PROTOCOLS

All registers may be accessed using either I2C or PMBus protocols. I2C allows the use of a simple format

whereas PMBus provides error checking capability. Figure 57 shows the I2C format employed by Manhattan

S: Start Condition

1

S

7

1

8

1

8

1

P

A: Acknowledge (0')

N: Not Acknowledge (1')

Sr: Repeated Start Condition

P: Stop Condition

Slave

Register

Address

WRITE

READ

A

W

Data Byte

Address

1

S

7

1

8

R: Read (1')

Slave

Register

Address

W: Write (0')

A

P

W

Address

…

PEC: Packet Error Checking

*: Present if PEC is enabled

: Master to Slave

7

1

P

1

S

1

R

8

Slave

Address

Data Byte

N

: Slave to Master

Figure 57: I2C Format

To access IR’s configuration and monitoring registers, 4 different protocols are required:

SMBUS/PMBUS PROTOCOLS

the SMBus Read/Write Byte/Word protocol with/without PEC (for status and monitoring)

the SMBus Send Byte protocol with/without PEC (for CLEAR_FAULTS only)

the SMBus Block Read protocol for accessing Model and Revision information

the SMBus Process call (for accessing Configuration Registers)

In addition, Manhattan supports:

Alert Response Address (ARA)

Bus timeout (10ms)

Group Command for writing to many VRs within one command

54

Rev 3.7

Mar 14, 2018

IR38064

S: Start Condition

8

1

S

7

1

8

1

8

1

P

A: Acknowledge (0')

N: Not Acknowledge (1')

Sr: Repeated Start Condition

P: Stop Condition

Slave

Command

Code

A*

BYTE

A

Data Byte

A

PEC*

W

Address

1

S

1

R: Read (1')

7

1

8

1

Slave

Command

Code

Data Byte

Low

W: Write (0')

WORD

A

W

Address

…

PEC: Packet Error Checking

*: Present if PEC is enabled

: Master to Slave

1

8

1

P

8

Data Byte

High

A*

PEC*

A

: Slave to Master

Figure 58: SMBus Write Byte/Word

1

P

1

8

1

7

1

R

1

8

1

7

8

Slave

Command

Code

Slave

Data Byte

A*

A

PEC*

N

BYTE

S

W

Sr

Address

1

S

7

1

8

1

7

1

R

1

8

1

Slave

Command

Code

Data Byte

A

Sr

A

WORD

W

Address

Low

Address

…

1

8

1

8

Data Byte

A*

PEC*

N

P

High

Figure 59: SMBus Read Byte/Word

1

S

7

1

8

1

8

1

P

Slave

Command

Code

PEC*

A

A*

A

W

Address

Figure 60: SMBus Send Byte

1

7

1

8

1

Slave

Command

Code

S

W

A

Address

…

1

7

1

R

1

8

1

Slave

Byte Count =1

Data Byte

A*

A

PEC*

N

P

Sr

Address

Figure 61: SMBus Block Read with Byte Count=1

55

Rev 3.7

Mar 14, 2018

IR38064

PMBus

Address

Command

D1h

Register

Address

Data Byte

PEC*

S

W

A

P

Figure 62: MFR specific command to Write an internal Register

Figure 63: SMBus Custom Process Call to Read an internal Register

1

S

7

1

8

1

8

1

8

1

8

1

Slave

Low

High

Command

A*

A

W

A

PEC1*

Address 1

Data Byte

Code 1

…

1 or more bytes

7

1

8

1

A

8

1

8

1

8

1

Low

Slave

High

Command

Code 2

A*

A

Sr

W

PEC2*

Data Byte

Address 2

Data Byte

…

1 or more bytes

1

7

1

8

1

8

1

8

1

8

1

Low

Slave

Command

Code n

High

A

P

Sr

W

A

PECn*

Data Byte

Address n

Data Byte

…

1 or more bytes

Figure 64: Group Command

56

Rev 3.7

Mar 14, 2018

IR38064

LAYOUT RECOMMENDATIONS

The layout is very important when designing high

frequency switching converters. Layout will affect

noise pickup and can cause a good design to

perform with less than expected results.

communication lines be at least 10 mils wide with a

spacing between the SCL and SDA traces that is at

least 2-3 times the trace width. Also, it is important

that these traces be routed away from any noise

sources (such as Sw node)

Make the connections for the power components in

the top layer with wide, copper filled areas or

polygons. In general, it is desirable to make proper

use of power planes and polygons for power

distribution and heat dissipation.

The input capacitors, inductor, output capacitors and

the IR38064 should be as close to each other as

possible. This helps to reduce the EMI radiated by

the power traces due to the high switching currents

through them. Place the input capacitor directly at

the PVin pin of IR38064.

The feedback part of the system should be kept

away from the inductor and other noise sources.

The critical bypass components such as capacitors

for Vin, VCC and 1.8V should be close to their

respective pins. It is important to place the feedback

components including feedback resistors and

compensation components close to Fb and Comp

pins.

In a multilayer PCB use one layer as a power

ground plane and have a control circuit ground

(analog ground), to which all signals are referenced.

The goal is to localize the high current path to a

separate loop that does not interfere with the more

sensitive analog control function. These two grounds

must be connected together on the PC board layout

at a single point. It is recommended to place all

the compensation parts over the analog ground

plane in top layer.

The Power QFN is a thermally enhanced package.

Based on thermal performance it is recommended to

use at least a 6-layers PCB. To effectively remove

heat from the device the exposed pad should be

connected to the ground plane using vias.

IR38064 has 3 pins, SCL, SDA and S¯¯A¯L¯E¯R¯T¯ that

are used for I2C/PMBus communication. It is

recommended that the traces used for these

57

Rev 3.7

Mar 14, 2018

IR38064

SUPPORTED PMBUS COMMANDS

Command

Code

SMBus

No. of

Default

Value

Command Name

Range

Resolution

Description

transaction bytes

01h

02h

03h

OPERATION

ON_OFF_CONFIG

CLEAR_FAULTS

R/W Byte

Send Byte

1

0

Enables or disables the device and controls margining

Configures the combination of Enable pin input and

serial bus commands needed to turn the unit on and of

Clear contents of Fault registers

Used to control writing to the PMBus device. The inten

of this command is to provide protection against

accidental changes.

10h

WRITE_PROTECT

R/W Byte

1

15h

16h

STORE_USER_ALL

Send Byte

0

Burns the User section registers into OTP memory

Copies the OTP registers into User memory

RESTORE_USER_ALL

Returns 1011xxxx to indicate Packet Error Checking is

supported, maximum bus speed is 400kHz and

SMBAlert# is supported.

19h

1Bh

CAPABILITY

Read Byte

1

2

Write

word/Block

read

May be used to prevent a warning or fault condition

from asserting the SMBALERT# signal.

SMBALERT_MASK

Process call

Causes the device to set its output voltage to the

0.5V commanded value.

V_S= VOUT_SCALE_LOOP

0-

21h

22h

24h

VOUT_COMMAND¹⁶

VOUT_TRIM¹⁶

R/W Word

2

5mV/V_S

2.555V/V_S

-128-

+128V

0V

Available to the device user to trim the output voltage

Sets an upper limit on the output voltage the unit can

command regardless of any other commands or

combinations.

VOUT_MAX¹⁶

6V

Sets the MARGIN high voltage when commanded by

0-

25h

VOUT_MARGIN_HIGH¹⁶

VOUT_MARGIN_LOW¹⁶

R/W Word

2

5mV/V_S

0.55V OPERATION

V_S= VOUT_SCALE_LOOP

Sets the MARGIN low voltage when commanded by

0.45V OPERATION

V_L= VOUT_SCALE_LOOP

0.125mV Sets the rate in mV/μs at which the output should

2.555V/V_S

0-

26h

27h

29h

33h

35h

2

2.555V/V_S

0-

VOUT_TRANSITION_RATE¹¹R/W Word

127ms/us

/us

change voltage. Exponent 0 to -4 allowed.

Compensates for external resistor divider in feedback

path and in the sense path. Values 1, 0.5, 0.25, 0.125

allowed. Exponent -3 allowed.

Sets the switching frequency, in kHz. Exponent 0 to 1

allowed.

Sets the value of the input voltage, in volts, at which th

unit should start power conversion. Exponent -1

allowed.

VOUT_SCALE_LOOP¹¹

FREQUENCY_SWITCH¹¹

VIN_ON¹¹

R/W Word

0.125-1

1

166-

1500kHz

607kHz

1V

0-16.5V

0-16V

0.5V

Sets the value of the input voltage, in volts, at which th

36h

39h

40h

VIN_OFF¹¹

R/W Word

2

0.5V

0.5A

0.5V unit, once operation has started, should stop power

conversion. Exponent -1 allowed.

-128A-

+127.5A

(25-

Used to null out any offsets in the output current

sensing circuit. Exponent -1 allowed.

Sets the value of the output voltage measured at the

0.605V sense pin that causes an output overvoltage fault.

V_S= VOUT_SCALE_LOOP

IOUT_CAL_OFFSET¹¹

VOUT_OV_FAULT_LIMIT¹⁶

0A

655mV)/V 10mV/V_S

S

VOUT_OV_FAULT_RESPONS

E

VOUT_OV_WARN_LIMIT¹⁶

Ignore/Sh

utdown

Shutdow Instructs the device on what action to take in response

41h

42h

R/W Byte

R/W Word

1

2

n

to an output overvoltage fault.

Sets the value of the output voltage at the

sense pin that causes an output voltage high warning.

3.9mV

0.56V

58

Rev 3.7

Mar 14, 2018

IR38064

Sets the value of the output voltage at the

Sense pin that causes an output voltage low warning.

Sets the value of the output voltage at the

sense pin that causes an output undervoltage fault.

Instructs the device on what action to

43h

44h

45h

VOUT_UV_WARN_LIMIT¹⁶

VOUT_UV_FAULT_LIMIT¹⁶

R/W Word

R/W Byte

2

1

3.9mV

0.44V

3.9mV 0.395V

Ignore

VOUT_UV_FAULT_RESPONS

E

Ignore/Shut

down

take in response to an output undervoltage fault.

Sets the value of the output current, in

46A amperes, that causes the overcurrent detector to

indicate an overcurrent fault. Exponent -1 allowed.

46h

IOUT_OC_FAULT_LIMIT¹¹

R/W Word

2

3-52.5A

0.5A

Pulse by

pulse for

8 cycles, Instructs the device on what action to

then take in response to an output overcurrent fault.

hiccup or

47h IOUT_OC_FAULT_RESPONSE R/W Byte

1

latch off

Sets the value of the output current, in

amperes, that causes the overcurrent detector to

indicate an overcurrent warning. Exponent -1

4Ah

IOUT_OC_WARN_LIMIT¹¹

R/W Word

2

0-63.5A

0.5A

39A

allowed.

Set the temperature, in degrees Celsius, of the unit at

which it should indicate an Overtemperature Fault.

Exponent 0 allowed.

4Fh

50h

OT_FAULT_LIMIT¹¹

R/W Word

R/W Byte

2

1

0-150°C

1°C

145°C

Ignore/Shut

down/Inhibi

it

Instructs the device on what action to take in

Inhibit

OT_FAULT_RESPONSE

response to an overtemperature fault.

Set the temperature, in degrees Celsius, of the unit at

which it should indicate an Overtemperature Warning

alarm. Exponent 0 allowed.

Sets the value of the input voltage that causes an

input overvoltage fault. Exponent -2 allowed.

Instructs the device on what action to take

in response to an input overvoltage fault.

51h

55h

56h

OT_WARN_LIMIT¹¹

R/W Word

2

1

0-150°C

1°C

125°C

VIN_OV_FAULT_LIMIT¹¹

6.25V-24V 0.25V

24V

Ignore/Shut

down

Shutdow

VIN_OV_FAULT_RESPONSE R/W Byte

n

Sets the value of the input voltage PVin, in volts,

that causes an input overvoltage fault. Exponent -1

allowed.

58h

5Eh

5Fh

VIN_UV_WARN_LIMIT¹¹

POWER_GOOD_ON¹⁶

POWER_GOOD_OFF¹⁶

R/W Word

2

0-16V

0.5V

Sets the output voltage at which an optional

(0-

0.63V)/V_S

10mV/V_S0.45V POWER_GOOD signal should be asserted.

V_S=VOUT_SCALE_LOOP

Sets the output voltage at which an optional

10mV/V_S0.42V POWER_GOOD signal should be negated.

V_S=VOUT_SCALE_LOOP

(0-

0.63V)/V_S

Sets the time, in milliseconds, from when a start

condition is received (as programmed by the

ON_OFF_CONFIG command) until the output

voltage starts to rise. Exponent 0 allowed.

60h

61h

TON_DELAY¹¹

TON_RISE¹¹

R/W Word

2

0-127ms

1ms

0ms

Sets the time, in milliseconds, from when the output

2ms starts to rise until the voltage has entered the

regulation band. Exponent 0 allowed.

Sets an upper limit, in milliseconds, on how long the

0 (No unit can attempt to power up the output without

limit) reaching the output undervoltage fault limit.

Exponent 0 allowed.

62h

63h

TON_MAX_FAULT_LIMIT¹¹

R/W Word

R/W Byte

2

1

Instructs the device on what action to

TON_MAX_FAULT_RESPONS

E

Ignore/Shut

down

Ignore

take in response to a TON_MAX fault.

Sets the time, in milliseconds, from a stop condition

is received (as programmed by the

64h

65h

TOFF_DELAY (not supported) R/W Word

2

0-127ms

1ms

0ms ON_OFF_CONFIG command) until the unit stops

transferring energy to the output. Exponent 0

allowed.

TOFF_FALL (not supported)

R/W Word

1ms Device will acknowledge this command but ignore it.

59

Rev 3.7

Mar 14, 2018

IR38064

Returns 1 byte where the bit meanings are:

Bit <7> device busy fault

Bit <6> output off (due to fault or enable)

Bit <5> Output over-voltage fault

Bit <4> Output over-current fault

Bit <3> Input Under-voltage fault

Bit <2> Temperature fault

78h

STATUS BYTE

Read Byte

1

Bit <1> Communication/Memory/Logic fault

Bit <0>: None of the above

Returns 2 bytes where the Low byte is the same as

the STATUS_BYTE data. The High byte has bit

meanings are:

Bit <7> Output high or low fault

Bit <6> Output over-current fault

Bit <5> Input under-voltage fault

Bit <4> Reserved; hardcoded to 0

Bit <3> Output power not good

Bit <2:0> Hardcoded to 0

79h

STATUS WORD

Read Word

2

7Ah

7Bh

7Ch

STATUS_VOUT

STATUS_IOUT

STATUS_INPUT

Read Byte

1

Reports types of VOUT related faults.

Reports types of IOUT related faults.

Reports types of INPUT related faults.

Returns Over Temperature warning and Over

Temperature fault (OTP level). Does not report under

temperature warning/fault. The bit meanings are:

Bit <7> Over Temperature Fault

Bit <6> Over Temperature Warning

Bit <5> Under Temperature Warning

Bit <4> Under Temperature Fault

Bit <3:0> Reserved

7Dh

STATUS_TEMPERATURE

Read Byte

1

Returns 1 byte where the bit meanings are:

Bit <7> Command not Supported

Bit <6> Invalid data

Bit <5> PEC fault

7Eh

STATUS_CML

Read Byte

1

Bit <4> OTP fault

Bit <3:2> Reserved

Bit<1> Other communication fault

Bit<0> Other memory or logic fault; hardcoded to 0

88h

8Bh

8Ch

8Dh

96h

READ_VIN¹¹

READ_VOUT¹⁶

READ_IOUT¹¹

Read Word

2

Returns the input voltage in Volts

Returns the output voltage in Volts

Returns the output current in Amperes

Returns the device temperature in degrees Celsius

Returns the output power in Watts

READ_TEMPERATURE¹¹

READ_POUT¹¹

Reports PMBus Part I rev 1.1 & PMBus

Part II rev 1.2(draft)

98h

99h

PMBUS_REVISION

MFR_ID

Read Byte

1

3

Block

Read/Write

Returns 2 bytes used to read the manufacturer’s ID.

User can overwrite with any value.

IR

If set to 00h, returns a 1 byte code corresponding to

Set 00 IC_DEVICE_ID.

Block

Read/Write

9Ah

MFR_MODEL

2

Alternatively, user can set to any non-zero value

60

Rev 3.7

Mar 14, 2018

IR38064

If set to 00h, returns a 1 byte code corresponding to

Set 00 IC_DEVICE_REV.

Block

Read/Write

9Bh

ADh

MFR_REVISION

IC_DEVICE_ID

2

Alternatively, user can set to any non-zero value

Used to read the type or part number of an IC.

IR38060: 30h

IR38061:31h

IR38060: 32h

Block Read

IR38060: 33h

IR38064:34h

IR38065:35h

AEh

D0h

IC_DEVICE_REV

MFR_READ_REG

Block Read

Custom

2

Used to read the revision of the IC

Manufacturer Specific: Read from configuration

registers

Manufacturer Specific: Write to configuration & status

registers

D1h

D8h

MFR_WRITE_REG

MFR_TPGDLY

Custom

2

Sets the delay in ms, between the output voltage

0ms entering the regulation window and the assertion of

the PGood signal. Exponent 0 allowed.

R/W Word

0-10ms

1ms

Allows the user to choose between forced continuous

1 (CCM) conduction mode and adaptive on-time operation at

light load.

D9h

MFR_FCCM

R/W Byte

1

0-1

D6h

DBh

MFR_I2C_address

R/W Word

Read Word

1

2

0-7Fh

10h

Sets and returns the device I2C base address

Continuously records and reports the highest value of

Read Vout.

MFR_VOUT_PEAK¹⁶

Continuously records and reports the highest value of

Read Iout.

Continuously records and reports the highest value of

Read_Temperature

DCh

MFR_IOUT_PEAK¹¹

Read Word

2

DDh MFR_TEMPERATURE_PEAK¹¹Read Word

61

Rev 3.7

Mar 14, 2018

IR38064

PCB PADS AND COMPONENT

62

Rev 3.7

Mar 14, 2018

IR38064

PCB COPPER AND SOLDER RESIST (PAD SIZES)

63

Rev 3.7

Mar 14, 2018

IR38064

PCB COPPER AND SOLDER RESIST (PAD SPACING)

64

Rev 3.7

Mar 14, 2018

IR38064

SOLDER PASTE STENCIL (PAD SIZES)

65

Rev 3.7

Mar 14, 2018

IR38064

SOLDER PASTE STENCIL (PAD SPACING)

66

Rev 3.7

Mar 14, 2018

IR38064

MARKING INFORMATION

TAPE AND REEL INFORMATION

Refer to Application Note AN-1132 for more information.

IRXXXX

67

Rev 3.7

Mar 14, 2018

IR38064

PACKAGE INFORMATION

SIDE VIEW (Back)

A

B

34

33

32

31

1

30

29

28

27

26

1

2

3

25

4

5

6

7

8

9

24

23

22

21

20

19

10 11 12 13 14 15 16 17 18

SIDE VIEW (Left)

SIDE VIEW (Right)

TOP VIEW

C

SIDE VIEW (Front)

68

Rev 3.7

Mar 14, 2018

IR38064

69

Rev 3.7

Mar 14, 2018

IR38064

ENVIRONMENTAL QUALIFICATIONS

Industrial

Qualification Level

Moisture Sensitivity Level

5mm x 7mm PQFN

MSL 2 260C

JEDEC Class B

JEDEC Class 2 (2KV)

JEDEC Class 3

Machine Model

(JESD22-A115A)

Human Body Model

ESD

(JESD22-A114F)

Charged Device Model

(JESD22-C101F)

RoHS Compliant

Yes (with Exemption 7a)

70

Rev 3.7

Mar 14, 2018

IR38064

REVSION HISTORY

Rev.

Date

Description

2.0

6/16/2015

Initial release

Added AC specification for Boot to SW, explicitly stated that no Rt resistor needed in

digital mode, added ESD specifications, corrected a typo in Vin operating range to

PVin operating range

2.1

2.2

2/8/2016

3/4/2016

Corrected

IOUT_OC_FAULT_LIMIT,

IOUT_OC_FAULT_RESPONSE

and

IOUT_OC_WARN_LIMIT range and defaults in PMBus command set table

converted to IFX (intermediate) format.

added a Marking diagram

added T&R info

2.3

3/11/2016

updated the POD

2.4

2.5

2.6

5/18/2016

6/10/2016

6/28/2016

Corrected current rating in header

Changed PVin rating to 16V. Updated with temp char data and plots, updated min on

time section and max duty plots, updated Vcc range from 4.5V to 4.5V, expressed

Iout reporting res in mA rather than A

Corrected references to user note UN0060

Changed OC response types; also changed PMBus default. Changed pad, stencil and

solder drawings, added info about decoupling caps, added placement for 10nF cap on

addr resistor in typical apps diagrams, removed gain and bandwidth specs of RSA and

EA. Added note about preferring to use FCCM because AOT is noisier. Re-arranged

order of the legend for efficiency and power loss curves, Changed ADDR resistor for 0

offset to 499 ohm

2.7

8/15/2016

Corrected some typos, added recommendation to clear faults on startup, min.

RT resistor also changed from 0 ohm to 499 ohm

2.8

8/17/2016

Corrected 3 references to PVin =21V and changed them to 16V in the spec

tables.

2.9

3.0

3.1

8/18/2016

9/22/2016

10/3/2016

Updated qual info

Updated leadframe drawing with dimensions, updated PVin rating to 21V with

Rboot note

3.2

3.3

12/2/2016

1/11/2017

Updates related to 750 k on track_en pin, changed LDO test condition in spec table

Updates related to 100k from track_en to P1V8

Update Vp bias current, note on the 750 K option from track_en# to LGnd

Added IBM part numbers into Ordering info

3.4

3.5

3/1/2017

5/17/2017

Update Ordering Information

Update to PMBus commands. TOFF_DELAY and TOFF_FALL not supported

in Manhattan.Update to Analog and Digital Mode Operation, added default

I2C/PMBus addresses.Added note, Rt pin can be connected to GND through a

series 15kohm resistor instead of floating.

3.6

12/15/2017

Specified how to set OCP in analog mode.

71

Rev 3.7

Mar 14, 2018

IR38064

Rev.

Date

Description

Added recommendation to use 10uF bypass capacitor at P1V8 pin.

Updated the schematic diagrams and OCP timing diagram.

3.7

03/14/2018

Added OCP recommendations.

72

Rev 3.7

Mar 14, 2018

IR38064

Published by

Infineon Technologies AG

81726 München, Germany

IMPORTANT NOTICE

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics (“Beschaffenheitsgarantie”). With respect to any examples, hints or any typical values stated

herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims

any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of

intellectual property rights of any third party.

In addition, any information given in this document is subject to customer’s compliance with its obligations stated

in this document and any applicable legal requirements, norms and standards concerning customer’s products

and any use of the product of Infineon Technologies in customer’s applications.

The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of

customer’s technical departments to evaluate the suitability of the product for the intended application and the

completeness of the product information given in this document with respect to such application.

For further information on the product, technology, delivery terms and conditions and prices please contact your

nearest Infineon Technologies office (www.infineon.com).

WARNINGS

Due to technical requirements products may contain dangerous substances. For information on the types in

question please contact your nearest Infineon Technologies office.

Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized

representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications

where a failure of the product or any consequences of the use thereof can reasonably be expected to result in

personal injury.

73

Rev 3.7

Mar 14, 2018


型号：	IR38064MTRPBF
厂家：	Infineon
描述：	带 PMBus 接口的高度集成 35A 单输入电压同步降压调节器。调节器
文件：	总73页 (文件大小：3349K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IR38064MTRPBF [INFINEON]

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