IR3811MPBF_08 [INFINEON]
HIGHLY INTEGRATED 7A WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR; 高度集成的7A宽电压输入，同步降压稳压器
| 型号： | IR3811MPBF_08 |
| 厂家： | 
Infineon |
| 描述： | HIGHLY INTEGRATED 7A WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR |
| 文件： | 总21页 (文件大小：669K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD-60334
IR3811MPbF
TM
SupIRBuck
HIGHLY INTEGRATED 7A
WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR
Features
Description
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Wide Input Voltage Range 2.5V to 21V
Wide Output Voltage Range 0.6V to 12V
Continuous 7A Load Capability
600kHz High Frequency Operation
Programmable Over-Current-Protection
Hiccup Current Limit
The IR3811 SupIRBuckTM is an easy-to-use, fully
integrated and highly efficient DC/DC regulator.
The onboard switching controller and MOSFETs
make the IR3811 a space-efficient solution,
providing accurate power delivery for low output
voltage applications.
Tracking capability for Memory Application
Precision Reference Voltage (0.6V)
Programmable Soft-Start
The IR3811 operates from a single 4.5V to 14V
input supply and generates an output voltage
adjustable from 0.6V to 0.75*Vin at loads up to 7A.
Pre-Bias Start-up
Thermal Protection
IR3811 can be configured for tracking
applications to generate termination voltage (VTT)
for memory applications.
Thermally Enhanced Package
Small Size 5mmx6mm QFN
Pb-Free (RoHS Compliant)
A versatile regulator offering programmability of
start up time and current limit, the IR3811’s fixed
600kHz switching frequency allows the use of
small external components.
Applications
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Distributed Point-of-Loads
Server and Workstations
Embedded Systems
IR3811 also features important protection
functions, such as Pre-Bias startup, hiccup
current limit and thermal shutdown to provide the
required system level security in the event of fault
conditions.
Storage Systems
DDR Applications
Graphics Cards
Game Consoles
Computing Peripheral Voltage Regulators
Fig. 1. Typical application diagram
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PD-60334
IR3811MPbF
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND)
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VIN Supply Voltage
Vcc Supply Voltage
Vc Supply Voltage
SW
-0.3V to 24V
-0.3V to 16V
-0.3V to 30V
-0.3V to 30V
-0.3V to 16V
-0.3V to 3.5V
10mA
PGood
Fb,COMP,SS,Vsns
OCSet
AGnd to PGnd
-0.3V to +0.3V
Storage Temperature Range
Operating Junction Temperature Range
ESD Classification
Moisture Sensitivity Level
-65°C To 150°C
-40°C To 150°C
JEDEC, JESD22-A114
JEDEC Level 3 @ 260oC
Caution: Stresses beyond those listed under “Absolute Maximum Rating” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of the specifications is not implied. Exposure to “Absolute Maximum
Rating” conditions for extended periods may affect device reliability.
PACKAGE INFORMATION
5mm x 6mm POWER QFN
10
11
SW
12
VIN
PGnd
θJA = 35oC / W
θJ-PCB = 2oC / W
15
AGnd
Vref
VCC
9
8
13
HG
Vc
14
1
4
7
2
3
5
6
Vp FB COMP AGnd AGnd SS OCSet
Fig. 2: Package outline (Top view)
ORDERING INFORMATION
PKG
PACKAGE
PIN
PARTS
PARTS
DESIG
COUNT
PER TUBE
PER REEL
DESCRIPTION
M
IR3811MTRPBF
15
---------------
4000
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PD-60334
IR3811MPbF
Block Diagram
Fig. 3. Simplified block diagram of the IR3811.
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PD-60334
IR3811MPbF
Pin Description
Pin Name
Description
1
2
Vp
Fb
Non-inverting input of error amplifier. This pin can be used for tracking application.
Inverting input to the error amplifier. This pin is connected directly to the output of
the regulator via resistor divider to set the output voltage and provide feedback to
the error amplifier.
3
4
5
6
Comp
AGnd
AGnd
SS/SD
Output of error amplifier. An external resistor and capacitor network is typically
connected from this pin to ground to provide loop compensation.
Signal ground for internal reference and control circuitry.
Signal ground for internal reference and control circuitry.
Soft start / shutdown. This pin provides user programmable soft-start function.
Connect an external capacitor from this pin to ground to set the start up time of the
output voltage. The converter can be shutdown by pulling this pin below 0.3V.
Current limit set point. A resistor from this pin to SW pin will set the current limit
threshold.
7
8
OCSet
VCC
This pin powers the internal IC as well as low side driver. A minimum of 0.1uF high
frequency capacitor must be connected from this pin to the power ground.
9
Vref
PGnd
SW
External reference voltage. Drive capability for this pin is 2μA.
10
11
12
Power Ground. This pin serves as a separated ground for the MOSFET drivers and
should be connected to the system’s power ground plane.
Switch node. This pin is connected to the output inductor
VIN
Input voltage connection pin
13
14
HG
VC
This pin is connected to the high side gate driver. Connect a small capacitor from
this pin to switch node (SW).
This pin powers the high side driver and must be connected to a voltage higher than
input voltage. A minimum of 0.1uF high frequency capacitor must be connected
from this pin to the power ground for the charge-pump high side drive scheme.
Signal ground for internal reference and control circuitry.
15
AGnd
Pins 4, 5 and 15 need to be connected together on system board.
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PD-60334
IR3811MPbF
Recommended Operating Conditions
Symbol
Definition
Min
Max
Units
Vin
Vcc
Vc
Vo
Io Note1
Tj
Input Voltage
2.5
4.5
Vin + 5V
0.6
21
14
28
12
7
Supply Voltage
Supply Voltage
Output Voltage
Output Current
V
0
-40
A
Junction Temperature
125
oC
Electrical Specifications
Unless otherwise specified, these specification apply over Vin=Vcc=Vc=12V, 0oC<Tj(Ic)< 105oC.
Typical values are specified at Ta = 25oC.
Parameter
Power Loss
Symbol
Test Condition
Min
TYP
MAX
Units
Power Loss
Ploss
Vcc=Vin=12V, Vc=24V, Vo=1.8V,
2.1
W
Io=7A, L=1uH, Note3
MOSFET Rds(on)
ID=9A, Tj(MOSFET)=25oC
ID=9A, Tj(MOSFET)=25oC
Top Switch
Rds(on)_Top
Rds(on)_Bot
10.5
10.5
13.4
13.4
mΩ
Bottom Switch
Reference Voltage
Feedback Voltage
VFB
0.6
V
%
%
Accuracy
0oC<Tj<105oC
-1.35
-1.5
+1.35
+1.5
-40oC<Tj<105oC, Note2
Supply Current
VCC Supply Current (Static)
ICC(Static)
IC(Static)
ICC(Dynamic)
IC(Dynamic)
SS=0V, No Switching
SS=0V, No Switching
10
4.5
18
18
13
7
VC Supply Current
(Static)
VCC Supply Current
(Dynamic)
VC Supply Current
(Dynamic)
mA
SS=3V, Vc=24V, Vcc=Vin=12V.
Vo=1.8V, Io=0A
SS=3V, Vc=24V, Vcc=Vin=12V.
Vo=1.8V, Io=0A
25
25
Under Voltage Lockout
VCC-Start-Threshold
VCC_UVLO(R)
VCC_UVLO(F)
Supply ramping up
4.0
3.7
4.4
4.1
VCC-Stop-Threshold
VCC-Hysteresis
Supply ramping down
Supply ramping up and down
Supply ramping up
0.15
3.1
0.25
0.2
0.3
V
VC-Start-Threshold
VC-Stop-Threshold
VC-Hysteresis
VC_UVLO(R)
VC_UVLO(F)
3.5
Supply ramping down
Supply ramping up and down
2.85
0.15
3.25
0.25
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PD-60334
IR3811MPbF
Parameter
SYM
Test Condition
Min
TYP
MAX
Units
Oscillator
Frequency
FS
540
600
1.25
80
660
kHz
V
Note3
Note3
Fb=0V
Ramp Amplitude
Min Pulse Width
Max Duty Cycle
Vramp
Dmin(ctrl)
Dmax
ns
%
75
Error Amplifier
Input Bias Current
IFB1
SS=3V
SS=3V
SS=0V
-0.1
-0.1
50
-0.5
-0.5
70
Input Bias Current
Input Bias Current
IVp
IFB2
μA
30
50
Source/Sink Current
Transconductance
I(source/Sink)
gm
70
90
1000
-4.5
0.2
1300
0
1600
+4.5
1.0
μmho
mV
V
Input Offset Voltage
Vp( (Common Mode Range)
Vos
Fb to Vp
Soft Start/SD
Soft Start Current
ISS
SS=0V
15
15
20
28
μA
Shutdown Output Threshold
SD
0.25
V
Over Current Protection
OCSET Current
Hiccup Current
IOCSET
IHiccup
20
3
26
μA
Note3
Hiccup Duty Cycle
Hiccup(duty)
15
%
IHiccup / ISS , Note3
Thermal Shutdown
Thermal Shutdown Threshold
140
20
Note3
Note3
oC
Thermal Shutdown Hysteresis
Note1: Continuous output current determined by input and output voltage setting and the thermal environment.
Note2: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.
Note3: Guaranteed by Design but not tested in production.
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PD-60334
IR3811MPbF
TYPICAL OPERATING CHARACTERISTICS (-40oC - 125oC)
Icc(static)
Ic(static)
13.0
12.0
11.0
10.0
9.0
7.0
6.0
5.0
4.0
3.0
2.0
8.0
7.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temp[oC]
Temp[oC]
Icc(dynamic)
Ic(dynamic)
21.0
19.0
17.0
15.0
13.0
21.0
19.0
17.0
15.0
13.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temp[oC]
Temp[oC]
Vfb
ISS
27.0
25.0
23.0
21.0
19.0
17.0
15.0
605.0
600.0
595.0
590.0
585.0
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temp[oC]
Temp[oC]
IOCSET
Transconductance
26.0
25.0
24.0
23.0
22.0
21.0
20.0
19.0
18.0
17.0
16.0
15.0
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temp[oC]
Temp[oC]
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PD-60334
IR3811MPbF
Circuit Description
THEORY OF OPERATION
The IR3811 is
a
voltage mode PWM
Pre-Bias Startup
synchronous regulator and operates with a fixed
600kHz switching frequency, allowing the use of
small external components.
The IR3811 is able to start up into pre-charged
output, which prevents oscillation and
disturbances of the output voltage.
The output voltage is set by feedback pin (Fb)
and the internal reference voltage (0.6V). These
are two inputs to error amplifier. The error signal
between these two inputs is amplified and it is
compared to a fixed frequency linear sawtooth
ramp.
The output starts in asynchronous fashion and
keeps the synchronous MOSFET off until the first
gate signal for control MOSFET is generated.
Figure 4 shows a typical Pre-Bias condition at
start up.
Depending on system configuration, a specific
number of output capacitors may be required to
prevent discharging the output voltage.
A trailing edge modulation is used for generating
fixed frequency pulses (PWM) which drives the
internal N-channel MOSFETs.
The internal oscillator circuit uses on-chip
circuitry, eliminating the need for external
components.
Vo
V
The IR3811 operates with single input voltage
from 4.5V to 14V allowing an extended operating
input voltage range.
Pre-Bias Voltage
The over-current protection is performed by
sensing current through the RDS(on) of low side
MOSFET. This method enhances the converter’s
efficiency and reduces cost by eliminating a
current sense resistor. The current limit is
programmable by using an external resistor.
Time
Fig. 4: Pre-Bias start up
Under-Voltage Lockout
The under-voltage lockout circuit monitors the
two input supplies (Vcc and Vc) and assures that
the MOSFET driver outputs remain in the off
state whenever the supply voltage drops below
set thresholds. Lockout occurs if Vcc or Vc fall
below 4.3V and 3.3V respectively. Normal
operation resumes once Vcc and Vc rise above
the set values.
Shutdown
The output can be shutdown by pulling the soft-
start pin below 0.3V. This can easily be done by
using an external small signal transistor. During
shutdown both MOSFET drivers will be turned
off. Normal operation will resume by cycling soft
start pin.
External Reference and Tracking
Thermal Shutdown
IR3811 is able to operate as a stand alone
regulator by connecting the Vref to Vp. In this
case the reference voltage is 0.6V. For tracking
application Vref pin can be left floating and the
Vp pin will be connected to master voltage which
IR3811 will track. In this case the Vp voltage is
the IC’s reference voltage.
Temperature sensing is provided inside the
IR3811. The trip threshold is typically set to
140oC. When trip threshold is exceeded, thermal
shutdown turns off both MOSFETs. Thermal
shutdown is not latched and automatic restart is
initiated when the sensed temperature drops
within the operating range. There is a 20oC
hysteresis in the thermal shutdown threshold.
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PD-60334
IR3811MPbF
Soft-Start
The IR3811 has programmable soft-start to
control the output voltage rise and limit the inrush
current during start-up.
3V
20uA
SS/SD
Comp
To ensure correct start-up, the soft-start
sequence initiates when Vcc and Vc rise above
their threshold and generate the Power On
Ready (POR) signal. The soft-start function
operates by sourcing current to charge an
external capacitor to about 3V.
40uA
POR
Error Amp
24K
24K
0.6V
Initially, the soft-start function clamps the output
of error amplifier by injecting a current (40uA)
into the Fb pin and generates a voltage about
0.96V (40ux24K) across the negative input of
error amplifier (see figure 5).
Fb
The magnitude of the injected current is inversely
proportional to the voltage at the soft-start pin. As
the soft-start voltage ramps up, the injected
current decreases linearly and so does the
voltage at negative input of error amplifier.
Fig. 5: Soft-Start circuit for IR3811
When the soft-start capacitor is around 1V, the
voltage at the positive input of the error amplifier
is approximately 0.6V.
Output of UVLO
POR
3V
The output of error amplifier will start increasing
and generating the first PWM signal. As the soft-
start capacitor voltage continues to rise up, the
current flowing into the Fb pin will keep
decreasing.
≅2V
≅1V
Soft-Start
Voltage
0V
The feedback voltage increases linearly as the
soft start voltage ramps up. When soft-start
voltage is around 2V, the output voltage reaches
the steady state and the injected current is zero.
40uA
Current flowing
into Fb pin
0uA
0.96V
Voltage at negative input ≅
of Error Amp
Figure
6
shows the theoretical operating
waveforms during soft-start.
0.6V
0.6V
The output voltage start-up time is the time
period when soft-start capacitor voltage
increases from 1V to 2V.
0V
Voltage at Fb pin
The start-up time will be dependent on the size of
the external soft-start capacitor and can be
estimated by:
Fig. 6: Theoretical operation waveforms
during soft-start
T
start
20μA∗
= 2V −1V
Css
For a given start-up time, the soft-start capacitor
can be estimated as:
CSS ≅ 20μA*T (ms)
--(1)
start
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PD-60334
IR3811MPbF
Over-Current Protection
The over current protection is performed by
sensing current through the RDS(on) of the low-
side MOSFET. This method enhances the
converter’s efficiency and reduces cost by
eliminating a current sense resistor. As shown in
figure 7, an external resistor (RSET) is connected
between OCSet pin and the inductor point which
sets the current limit set point.
The internal current source develops a voltage
across RSET. When the low side MOSFET is
turned on, the inductor current flows through the
Q2 and results a voltage which is given by:
Fig. 8: 3uA current source for discharging
soft-start capacitor during hiccup
The OCP circuit starts sampling current when the
low gate drive is about 3V. The OCSet pin is
internally clamped about 1.5V during on time of
high side gate to prevent false trigging, figure 9
shows the OCSet pin during one switching cycle.
As shown, there is about 150ns delay to mask
the dead time. Since this node contains switching
noises, this delay also functions as a filter.
VOCSet = (IOCSet ∗ ROCSet ) − (RDS(on) ∗IL )
--( 2)
Deadtime
Blanking time
IOCSet*ROCSet
Clamp voltage
Fig. 7: Connection of over current sensing resistor
The critical inductor current can be calculated by
setting:
V
OCSet = (IOCSet ∗ROCSet)−(RDS(on) ∗IL ) = 0
Fig. 9: OCset pin during normal condition
Ch1: Inductor point, Ch3:OCSet
ROCSet ∗ IOCSet
ISET = IL(critical )
=
--( 3 )
RDS (on )
The value of RSET should be checked in an actual
circuit to ensure that the over current protection
circuit activates as expected. The IR3811 current
limit is designed primarily as disaster preventing,
and doesn't operate as a precision current
regulator.
An over current is detected if the OCSet pin goes
below ground. This trips the OCP comparator
and cycles the soft start function in hiccup mode.
The hiccup is performed by charging and
discharging the soft-start capacitor in a certain
slope rate. As shown in figure 8 a 3uA current
source is used to discharge the soft-start
capacitor.
The OCP comparator resets after every soft start
cycle. The converter stays in this mode until the
overload or short circuit is removed. The
converter will automatically recover.
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PD-60334
IR3811MPbF
Soft-Start Programming
Application Information
Design Example:
The following example is a typical application for
the IR3811. The application circuit is shown in
page 17.
The soft-start timing can be programmed by
selecting the soft-start capacitance value. The
start-up time of the converter can be calculated
by using:
CSS ≅ 20μA*T
--(1)
start
Where Tstart is the desired start-up time (ms)
For a start-up time of 11ms, the soft-start
capacitor will be 0.22uF.
Vin =12V,(13.2V,max )
Vo = 0.75V
Vc supply for single input voltage
Io = 7 A
To drive the high side switch, it is necessary to
supply a gate voltage at least 4V greater than the
bus voltage. This is achieved by using a charge
pump configuration as shown in figure 11. This
method is simple and inexpensive. The operation
of the circuit is as follows: when the lower
MOSFET is turned on, the capacitor (C1) is
pulled down to ground and charges, up to VBUS
value, through the diode (D1). The bus voltage
will be added to this voltage when upper
MOSFET turns on in next cycle, and providing
supply voltage (Vc) through diode (D2). Vc is
approximately:
ΔVo ≤ 30mV
Fs = 600 kHz
Output Voltage Programming
Output voltage is programmed by reference
voltage and external voltage divider. The Fb pin
is the inverting input of the error amplifier, which
is internally referenced to 0.6V. The divider is
ratioed to provide 0.6V at the Fb pin when the
output is at its desired value. The output voltage
is defined by using the following equation:
⎛
⎞
R8
R9
V ≅ 2∗V
−
VD1 +VD2
--(6)
⎜
⎟
⎟
Vo =Vref ∗ 1 +
--(4)
C
bus
⎜
⎝
⎠
Capacitors in the range of 0.1uF are generally
adequate for most applications. The diodes must
be a fast recovery device to minimize the amount
of charge fed back from the charge pump
capacitor into VBUS. The diodes need to be able
to block the full power rail voltage, which is seen
when the high side MOSFET is switched on. For
low voltage application, schottky diodes can be
used to minimize forward drop across the diodes
at start up.
When an external resistor divider is connected to
the output as shown in figure 10.
VOUT
IR3811
R8
Fb
R9
Fig. 10: Typical application of the IR3811 for
programming the output voltage
Equation (4) can be rewritten as:
⎛
⎞
Vref
⎜
⎜
⎟
⎟
R9 = R8 ∗
--(5)
VO−Vref
⎝
⎠
Fig. 11: Charge pump circuit to generate
Vc voltage
For the calculated values of R8 and R9 see
feedback compensation section.
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PD-60334
IR3811MPbF
Input Capacitor Selection
IfΔi ≈ 30%(Io ,)then the output inductor will be:
L = 0.6uH
The input filter capacitor should be selected
based on how much ripple the supply can
tolerate on the DC input line. The ripple current
generated during the on time of upper MOSFET
should be provided by the input capacitor. The
RMS value of this ripple is expressed by:
Delta MLP-104 series provides a range of
inductors in different values, and small size
suitable for this application.
Output Capacitor Selection
IRMS = Io ∗ D∗(1−D) --(7)
The voltage ripple and transient requirements
determine the output capacitors’ type and values.
The criteria is normally based on the value of the
Effective Series Resistance (ESR). However the
actual capacitance value and the Equivalent
Series Inductance (ESL) are other contributing
components. These components can be
described as:
Vo
D =
Where:
V
in
D is the Duty Cycle
IRMS is the RMS value of the input capacitor
current.
Io is the output current.
For Io=7A and D=0.0625, the IRMS=1.69A.
ΔV = ΔVo(ESR) + ΔVo(ESL) + ΔV
o
o(C)
Ceramic capacitors are recommended due to
their peak current capabilities. They also feature
low ESR and ESL at higher frequency which
results in better efficiency,
ΔV
= ΔIL *ESR - -(9)
o(ESR)
Use 3x10uF, 16V ceramic capacitors from
Panasonic.
V
⎛
⎜
⎞
⎟
in
ΔV
=
*ESL
o(ESL)
L
⎝
⎠
Inductor Selection
ΔIL
8 *Co *F
ΔV
=
o(C)
The inductor is selected based on output power,
operating frequency and efficiency requirements.
A low inductor value causes a large ripple
current, resulting in the smaller size, faster
response to a load transient but poor efficiency
and high output noise. Generally, the selection of
the inductor value can be reduced to the desired
maximum ripple current in the inductor (Δi) . The
optimum point is usually found between 20% and
50% ripple of the output current.
s
ΔV =Output voltage ripple
o
ΔIL = Inductor ripple current
Since the output capacitor has a major role in the
overall performance of converter and determine
the result of transient response, selection of the
capacitor is critical. The IR3811 can perform well
with all types of capacitors.
For the buck converter, the inductor value for the
desired operating ripple current can be
determined using the following:
As a rule the capacitor must have low enough
ESR to meet output ripple and load transient
requirements, yet have high enough ESR to
satisfy stability requirements.
Δi
Δt
1
V −V = L∗ ; Δt = D∗
in
o
F
s
The goal for this design is to meet the voltage
ripple requirement in the smallest possible
capacitor size. Therefore, a ceramic capacitor is
selected due to its low ESR and small size. Six of
the Panasonic ECJ2FB0J226M (22uF, 6.3V, X5R
and EIA 0805 case size) are a good choice.
V
o
L =
(
V −V
)
∗
--(8)
in
o
V ∗Δi *F
in
s
Where:
V = Maximum input voltage
in
Vo = Output Voltage
Δi = Inductor ripple current
Fs= Switching frequency
Δt = Turn on time
In the case of tantalum or low ESR electrolytic
capacitors, the ESR dominates the output
voltage ripple, equation (9) can be used to
calculate the required ESR for the specific
voltage ripple.
D = Duty cycle
01/08/08
12
PD-60334
IR3811MPbF
Feedback Compensation
The ESR zero of the output capacitor expressed
as follows:
The IR3811 is a voltage mode controller; the
control loop is a single voltage feedback path
including error amplifier and error comparator. To
achieve fast transient response and accurate
output regulation, a compensation circuit is
necessary. The goal of the compensation
network is to provide a closed loop transfer
function with the highest 0dB crossing frequency
and adequate phase margin (greater than 45o).
1
F
=
- - -(12)
ESR
2∗π *ESR*Co
VOUT
R8
Fb
Comp
Ve
E/A
R9
C
4
CPOLE
VREF
R3
The output LC filter introduces a double pole, –
40dB/decade gain slope above its corner
resonant frequency, and a total phase lag of 180o
(see figure 13). The resonant frequency of the LC
filter expressed as follows:
Gain(dB)
H(s) dB
1
Frequency
F =
- - -(11)
FZ
LC
2 π L Co
o
Fig. 14: TypeII compensation network
and its asymptotic gain plot
Figure 13 shows gain and phase of the LC filter.
Since we already have 180o phase shift from the
output filter along, the system risks being
unstable.
The transfer function (Ve/Vo) is given by:
Gain
Phase
R9
1+sRC4
3
H(s)= gm *
*
- - -(13)
R9 +R8
sC
4
0ꢀ
0dB
-40dB/decade
The (s) indicates that the transfer function varies
as a function of frequency. This configuration
introduces a gain and zero expressed by:
-180
ꢀ
Frequency
FLC
F
LC Frequency
⎛
⎞
R9
⎜
⎟
⎟
[
H
(
s
)
]
= gm *
* R3 - - -(14)
⎜
⎝
R9 +R8
⎠
Fig. 13: Gain and Phase of LC filter
1
F =
- - -(15)
z
2π *R3 *C4
The IR3811’s error amplifier is a differential-input
transconductance amplifier. The output is
available for DC gain control or AC phase
compensation.
The gain is determined by the voltage divider and
error amplifier’s transconductance gain.
First select the desired zero-crossover frequency
(Fo):
The error amplifier can be compensated either in
type II or typeIII compensation. When it is used in
type II compensation the transconductance
properties of the error amplifier become evident
and can be used to cancel one of the output filter
poles. This will be accomplished with a series RC
circuit from Comp pin to ground as shown in
figure 14.
F > FESR andF ≤
1/5~1/10 *F
o
o
s
Use the following equation to calculate R3:
V * F * FESR * (R8 +R9 )
osc
o
R3 =
- - -(16)
V * F2 * R9 * gm
in
LC
Where:
Vin = Maximum Input Voltage
osc = Oscillator Ramp Voltage
Fo = Crossover Frequency
ESR = Zero Frequency of the Output Capacitor
LC = Resonant Frequency of the Output Filter
V
This method requires that the output capacitor
should have enough ESR to satisfy stability
requirements. In general the output capacitor’s
ESR generates a zero typically at 5kHz to 50kHz
which is essential for an acceptable phase
margin.
F
F
R8 and R9 = Feedback Resistor Dividers
gm = Error Amplifier Transconductance
01/08/08
13
PD-60334
IR3811MPbF
To cancel one of the LC filter poles, place the
zero before the LC filter resonant frequency pole:
VOUT
ZIN
C3
F =75%F
z
LC
C
7
R3
C4
1
F = 0.75*
- - -(17)
R10
R8
z
Zf
2π L *Co
o
Use equations (15) and (16) to calculate C4.
One more capacitor is sometimes added in
parallel with C4 and R3. This introduces one
more pole which is mainly used to suppress the
switching noise.
Fb
Ve
E/A
R9
Comp
VREF
Gain(dB)
The additional pole is given by:
H(s) dB
1
F =
P
C4 *CPOLE
2π *R3 *
C4 +CPOLE
Frequency
F
Z
1
F
Z
2
F
P
2
FP3
The pole sets to one half of switching frequency
which results in the capacitor CPOLE
:
Fig.15: Compensation network with local
feedback and its asymptotic gain plot
1
1
CPOLE
=
≅
1
π * R3 * F
s
π * R3 * F −
s
As known, the transconductance amplifier has
high impedance (current source) output,
therefore, consideration should be taken when
loading the error amplifier output. It may exceed
its source/sink output current capability, so that
the amplifier will not be able to swing its output
voltage over the necessary range.
C4
F
s
For FP <<
2
For a general solution for unconditional stability
for any type of output capacitors, in a wide range
of ESR values we should implement local
feedback with a compensation network (type III).
The typically used compensation network for
voltage-mode controller is shown in figure 15.
The compensation network has three poles and
two zeros and they are expressed as follows:
In such a configuration, the transfer function is
FP1 = 0
given by:
1
Ve 1 − gmZf
Vo 1 + gmZIN
FP2
FP3
=
=
=
2π * R10 *C7
1
1
≅
⎛
⎞
2π * R3 *C3
C4 *C3
C4 + C3
The error amplifier gain is independent of the
transconductance under the following condition:
⎜
⎜
⎟
⎟
2π * R3
⎝
⎠
1
Fz1 =
gm * Zf >>1 and gm * Zin >>1 - - - (18)
2π * R3 *C4
1
1
By replacing Zin and Zf according to figure 15, the
transformer function can be expressed as:
Fz2
=
≅
2π *C7 * (R8 + R10 ) 2π *C7 * R8
1
(1 + sR3C4 ) *
[
1 + sC7
R8 + R10
]
Cross over frequency is expressed as:
H(s) =
*
sR8 (C4 + C3 )
⎡
⎤
⎥
⎦
⎛
⎞
C4 *C3
C4 + C3
⎜
⎜
⎟
⎟
1 + sR
* (1 + sR C )
⎢
3
10
7
V
1
in
F = R3 *C *
*
⎝
⎠
⎣
o
7
V
2π *L *Co
osc
o
01/08/08
14
PD-60334
IR3811MPbF
The DC gain will be large enough to provide high
DC-regulation accuracy (typically -5dB to -12dB).
The phase margin should be greater than 45o for
overall stability.
Based on the frequency of the zero generated by
the output capacitor and its ESR versus
crossover frequency, the compensation type can
be different. The table below shows the
compensation types and location of crossover
frequency.
Θmax =70o
Desired Phase Boost:
Compensator
type
Output
capacitor
FESR vs. Fo
1-SinΘ
F =F *
Z2
o
1+SinΘ
Type II(PI)
Electrolytic
, Tantalum
FLC<FESR<Fo<Fs/2
FLC<Fo<FESR<Fs/2
F =14.11kHz
Z2
Type III(PID)
Tantalum,
ceramic
Method A
1+SinΘ
F =F *
P2
o
1-SinΘ
Type III(PID)
Ceramic
FLC<Fo<Fs/2<FESR
Method B
F =453.70kHz
P2
Table1- The compensation type and location
of FESR versus Fo
Select: F =0.5* F and F =0.5* F
Z1
Z2
P3
s
Select:C =180pF
The details of these compensation types are
discussed in application note AN-1043 which can
be downloaded from IR’s website at www.irf.com.
7
2π * F * L * Co *V
2
o
o
R3 =
OSC , R3=12.57KΩ, checkR3 ≥
C *V
gm
7
in
For this design we have:
Vin=12V
Vo=0.75V
Select: R3 =12.70KΩ
CalculateC4 andC3 :
1
Vosc=1.25V
Vref=0.6V
gm=1000umoh
Lo=0.60uH
Co=6x22uF, ESR=0.5mOhm
Fs=600kHz
C4 =
;C4 =1.78nF, Select: C4 =1.8nF
2π * F * R
Z1
3
1
These result to:
C3 =
;C3 =41.77pF, Select:C3 =39pF
2π * F * R3
P3
FLC=24.210kHz
F
F
ESR=4.4MHz
s/2=600kHz
CalculateR ,R8 andR9 :
10
Select crossover frequency:
1
1
R =
; R =1.95KΩ, checkR ≥
P2
10
10
10
F < FESR andF ≤
1/5~1/10 *F
2π * C * F
gm
o
o
s
7
Fo=80kHz
Select: R =1.96KΩ
10
Since: FLC<Fo<Fs/2<FESR, typeIII method B is
1
selected to place the poles and zeros.
R8 =
R9 =
R ; R8 =60.72KΩ, Select: R8 =60.4KΩ
10
2π * C * F
7
Z2
The following design rules will give a crossover
frequency approximately one-tenth of the
switching frequency. The higher the band width,
the potentially faster the load transient response.
V
ref
* R8 ; R9 =241.6KΩ, Select: R9 =243KΩ
V
V
o
ref
01/08/08
15
PD-60334
IR3811MPbF
Layout Consideration
Programming the Current-Limit
The layout is very important when designing high
frequency switching converters. Layout will affect
noise pickup and can cause a good design to
perform with less than expected results.
The Current-Limit threshold can be set by
connecting a resistor (RSET) from drain of the
low-side MOSFET to the OCSet pin. The
resistor can be calculated by using equation (3).
Start to place the power components, making all
the connection in the top layer with wide, copper
filled areas.
The RDS(on) has
a
positive temperature
coefficient and it should be considered for the
worse case operation. This resistor must be
placed close to the IC, place a small ceramic
capacitor from this pin to power ground (PGnd)
for noise rejection purposes.
The inductor, output capacitor and the IR3811
should be as close to each other as possible.
This helps to reduce the EMI radiated by the
power traces due to the high switching currents
through them. Place the input capacitor directly to
the Vin pin of IR3811. To reduce the ESR replace
the single input capacitor with two parallel units.
The feedback part of the system should be kept
away from the inductor and other noise sources.
The critical bypass components such as
capacitors for Vcc and Vc should be close to their
respective pins. It is important to place the
feedback components including feedback
resistors and compensation components close to
Fb and Comp pins.
ROCSet ∗IOCSet
ISET =IL(critica)l
=
- -(3)
RDS(on)
RDS(on) =10.5mΩ ∗υ =10.5mΩ ∗1.5 =15.75mΩ
where:
υ :Temperature Dependency
Note :Use14.5 mΩ for low - side MOSFET
if 5V is used for V
cc
Δi
ISET = (Io ∗1.5) +
2
where:
In a multilayer PCB use one layer as a power
ground plane and have a control circuit ground
(analog ground), to which all signals are
referenced. The goal is to localize the high
current path to a separate loop that does not
interfere with the more sensitive analog control
function. These two grounds must be connected
together on the PC board layout at a single point.
The Power QFN is a thermally enhanced
package. Based on thermal performance it is
recommended to use at least a 4-layers PCB. To
effectively remove heat from the device the
exposed pad should be connected to the ground
plane using vias.
Io : MaxOutputCurrent
Δi : Inductor ripplecurrent
Vo
Δi = (V -Vo )∗
in
V ∗L∗F
in
s
ISET = (7A∗1.5)+ 0.97A=11.47A
ROCSet = R7 = 9.09KΩ
01/08/08
16
PD-60334
IR3811MPbF
Typical Application for IR3811
12V to 0.75V @ 7A
Fig.16: Typical Application circuit for 12V to 0.75V at 7A using ceramic output capacitors
01/08/08
17
PD-60334
IR3811MPbF
PCB Metal and Components Placement
The lead lands (the 11 IC pins) width should be equal to the nominal part lead width. The
minimum lead to lead spacing should be ≥ 0.2mm to minimize shorting.
Lead land length should be equal to the maximum part lead length + 0.3 mm outboard
extension. The outboard extension ensures a large and inspectable toe fillet.
The pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal
to maximum part pad length and width. However, the minimum metal-to-metal spacing
should be no less than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper
and no less than 0.23mm for 3 oz. Copper.
01/08/08
18
PD-60334
IR3811MPbF
Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder
resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure
NSMD pads.
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder
resist onto the copper of 0.05mm to accommodate solder resist mis-alignment.
Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to
the high aspect ratio of the solder resist strip separating the lead lands from the pad land.
01/08/08
19
PD-60334
IR3811MPbF
Stencil Design
•
The Stencil apertures for the lead lands should be approximately 80% of the area of
the lead lads. Reducing the amount of solder deposited will minimize the
occurrences of lead shorts. If too much solder is deposited on the center pad the part
will float and the lead lands will be open.
•
The maximum length and width of the land pad stencil aperture should be equal to
the solder resist opening minus an annular 0.2mm pull back to decrease the
incidence of shorting the center land to the lead lands when the part is pushed into
the solder paste.
01/08/08
20
PD-60334
IR3811MPbF
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been designed and qualified for the Consumer market.
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 10/07
01/08/08
21
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