IR3823AMTRPBF [INFINEON]

3 A 单输出同步降压调节器;


型号：	IR3823AMTRPBF
厂家：	Infineon
描述：	3 A 单输出同步降压调节器调节器
文件：	总41页 (文件大小：1153K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IR3823A

IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Features

•

Single 4.3 V to 17 V application

Precision Reference Voltage (0.6 V +/-0.5%)

Enhanced Fast COT engine stable with Ceramic Output Capacitors and No External Compensation

Optional Forced Continuous Conduction Mode or Diode Emulation for Enhanced Light Load Efficiency

Programmable Switching Frequency from 600 kHz to 2 MHz

Enable input with Voltage Monitoring Capability & Power Good Output

Monotonic Start-Up with Two Selectable Soft Start time & Enhanced Pre-Bias Start up

Thermally compensated Internal Over Current Protection

Thermal Shut Down

Operating Junction Temp: -40 °C < T_j< 125 °C

Small Size: 3.5 mm x 3.5 mm PQFN

Halogen-free and RoHS Compliant

Potential applications

•

Server Applications

Storage Applications

Telecom & Datacom Applications

Distributed Point of Load Power Architectures

Product validation

Qualified for industrial applications according to the relevant tests of JEDEC47/20/22

Description

The IR3823A is an easy-to-use, fully integrated dc - dc Buck regulator. The onboard PWM controller and MOSFETs

with integrated bootstrap diode make IR3823A a small footprint solution, providing high-efficiency power

delivery. Furthermore, it uses a fast Constant On-Time (COT) control scheme, which simplifies design efforts and

provides fast control response.

The IR3823A has an internal low dropout voltage regulator, allowing operation with a single supply. The IR3823A

is a versatile regulator, offering programmable switching frequency from 600 kHz to 2 MHz, two selectable soft

start times, Forced Continuous Conduction Mode (FCCM) and Diode Emulation Mode (DEM) operation.

It also features important protection functions, such as pre-bias start-up, thermally compensated current limit,

over voltage and under voltage protection, and thermal shutdown to give required system level security in the

event of fault conditions.

Final Datasheet

www.infineon.com

Please read the Important Notice and Warnings at the end of this document

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Table of contents

Features ........................................................................................................................................ 1

Potential applications..................................................................................................................... 1

Product validation.......................................................................................................................... 1

Description .................................................................................................................................... 1

Table of contents............................................................................................................................ 2

Ordering information ............................................................................................................. 4

Functional block diagram........................................................................................................ 5

Typical application diagram .................................................................................................... 6

Pin descriptions ..................................................................................................................... 7

Absolute maximum ratings ..................................................................................................... 8

6.1

Thermal characteristics .......................................................................................................... 9

Thermal Characteristics..........................................................................................................................9

7.1

7.2

Electrical specifications .........................................................................................................10

Recommended operating conditions...................................................................................................10

Electrical characteristics.......................................................................................................................11

Typical efficiency and power loss curves..................................................................................14

PV_in= V_in= 12 V, F_sw= 600 kHz ................................................................................................................14

PV_in= V_in= 12 V, F_sw= 800 kHz ................................................................................................................15

PV_in= V_in= 12 V, F_sw= 1000 kHz...............................................................................................................16

8.1

8.2

8.3

Thermal de-rating cuves ........................................................................................................17

R_DS(ON)of MOSFET over temperature .........................................................................................18

Typical operating characteristics (-40 °C ≤ T_j≤ +ꢀꢁꢂ °C)..............................................................19

Theory of operation...............................................................................................................21

Fast Constant On-Time Control ............................................................................................................21

Enable ....................................................................................................................................................21

FCCM and DEM Operation.....................................................................................................................22

Pseudo-Constant Switching Frequency ...............................................................................................22

Soft-start................................................................................................................................................23

Pre-bias Start-up ...................................................................................................................................23

Internal Low - Dropout (LDO) Regulator...............................................................................................24

Over Current Protection (OCP) .............................................................................................................24

Under Voltage Protection (UVP) ...........................................................................................................25

Over Voltage Protection (OVP)..............................................................................................................25

Over Temperature Protection (OTP) ....................................................................................................26

Power Good (PGood) Output ................................................................................................................26

Minimum ON - Time and Minimum OFF - Time ....................................................................................26

Selection of Feedforward Capacitor and Feedback Resistors.............................................................27

Resistors for Configuration Pins ...........................................................................................................28

12.1

12.2

12.3

12.4

12.5

12.6

12.7

12.8

12.9

12.10

12.11

12.12

12.13

12.14

12.15

Design example.....................................................................................................................29

Enabling the IR3823A ............................................................................................................................29

Programming the Switching Frequency and Operation Mode............................................................29

Selecting Input Capacitors....................................................................................................................29

Inductor Selection.................................................................................................................................30

Output Capacitor Selection ..................................................................................................................30

13.1

13.2

13.3

13.4

13.5

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Table of contents

13.6

13.7

13.8

13.9

Output Voltage Programming...............................................................................................................31

Feedforward Capacitor .........................................................................................................................31

Bootstrap Capacitor..............................................................................................................................31

Vin and VCC/LDO bypass Capacitor......................................................................................................31

14.1

14.2

Application information.........................................................................................................32

Application Diagram..............................................................................................................................32

Typical Operating Waveforms...............................................................................................................32

15.1

15.2

Layout recommendations ......................................................................................................35

Solder mask...........................................................................................................................................35

Stencil design ........................................................................................................................................36

16.1

16.2

Package ...............................................................................................................................38

Marking Information .............................................................................................................................38

Dimensions............................................................................................................................................38

Environmental qualifications .................................................................................................40

Revision history.............................................................................................................................41

Final Datasheet

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Ordering information

Ordering Information

Base Part Number

IR3823AMTRPBF

Package Type

Standard Pack Form and Qty Orderable Part Number

PQFN 3.5 mm x 3.5 mm Tape and Reel

4000

IR3823AMTRPBFXUMA1

IR3823AMTRPBF

Designator

Packing type

Tape & Reel

Dry

Moisture

protection packing

Packing size

330 mm

Halogen Free

RoHS compliant

Total lead free

Yes

PVin

PGND

AGND 13

AGND

VCC/ LDO

Vin

AGND

Boot

Figure 1 Package Top View

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Functional block diagram

VCC/LDO

AGND

PGood

Vin

POR

UVP

Threshold

UVP OTP

OVP

VCC/LDO

LDO

Fault

AGND

BOOT

PVin

OVP

Threshold

Turn-on Delay

PGood

Prebias

Fault

HDrVin

HDrv

PGood

Hysteresis

Threshold

POR

Hiccup

OVP

POR

VCC

4.0 V

GATE

DRIVE

LOGIC

VCC/LDO

OTP

Fault

1.2 V

LDrVin

LDrv

PWM

COMP

SOFT

START

ADAPTIVE

ON-TIME

GENERATOR

SET

PGND

Zero Cross

DETECTION

PGND

RAMP

GENERATOR

OCP

Floor

GENERATOR

Hiccup

UVP

VREF

AGND

OCP Limit

TON/MODE

20 ms

Delay

Figure 2 Block diagram

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Typical application diagram

PVin

Enable

PVin

Vin

BOOT

VCC/LDO

PGood

IR3823A

Cff

RFB1

RFB2

Float or GND

TON/MODE

PGND

AGND

Figure 3 IR3823A basic application circuit

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Pin descriptions

Note:

I = Input, O = Output

Pin#

Pin Name

I/O

Type

Pin Description

Output voltage feedback pin. Connect this pin to the

output of the regulator via a resistor divider to set the

output voltage.

Analog

Connect this pin to VCC/Float or GND to select Soft-Start

time from 2 options (see Table 5 Configuration for SS Pin).

This pin must be left floating.

Analog

No connect

Note: Pin 3 is internally connected.

Signal ground for the internal reference voltage and

control circuitry. AGND and PGND are not internally

connected. AGND and PGND must be connected on the

PCB with a single ground connection.

4, 9, 13, 16

AGND

Ground

Multi-function pin. This pin sets the switching frequency to

1 of 8 settings and sets the mode of operation to FCCM or

DEM by connecting a resistor to ground.

Power Good status output pin is open drain. Connect a pull

up resistor from this pin to VCC/LDO or to an external bias

voltage, e.g. 3.3 V.

TON/MODE

PGood

Analog

Vin is the input voltage for the Internal LDO and it should

always be connected to PVin; also forms input to

feedforward block. A 4.7 µF capacitor should be connected

between this pin and PGND.

Output of the internal LDO. A ceramic capacitor valued

between 2.2 µF and 10 µF is recommended for use between

VCC/LDO and the Power ground (PGND).

Power ground. This pin should be connected to the

systemꢀs power ground plane. Bypass capacitors between

PVin and PGND should be connected very close to PVin pin

and this pin.

Vin

Power

Ground

VCC/LDO

PGND

Power

Switch node. This pin is connected to the output inductor.

Input voltage for power stage. Bypass capacitors between

PVin and PGND should be connected very close to this pin

and PGND.

PVin

Supply voltage for the high side driver. Connect this pin to

the SW pin through a bootstrap capacitor.

BOOT

Analog

Enable pin to turn the IC on and off.

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Absolute maximum ratings

Description

Min

Max

Unit

Conditions

PVin, Vin, En to PGND

-0.3

Note 1

-0.3 V(dc),

below -5 V for 5 ns

PVin to SW

VCC/LDO to PGND

BOOT to PGND

-0.3

Note 1

-0.3 V(dc),

below -0.3 V for 5 ns

-0.3 (dc),

SW to PGND

BOOT to SW

FB, PGood, TON/MODE and SS

to AGND

Note 1

below -5 V for 5 ns

-0.3

Note 1

PGND to AGND

-0.3

-55

-40

0.3

150

Storage Temperature Range

Junction Temperature Range

°C

Note:

1. PGND and AGND pin are connected together

Attention:

Stresses beyond these listed under ꢀAbsolute Maximum Ratingsꢁ may cause permanent

damage to the device. These are stress ratings only and functional operation of the device at

these or any other conditions beyond those indicated in the operational sections of the

specifications are not implied.

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Thermal characteristics

6.1

Thermal Characteristics

Description

Symbol

Values

37.4 °C/W

10.1 °C/W

120 °C/W

Test Conditions

Junction to Ambient Thermal Resistance

Junction to PCB Thermal Resistance

Junction to Case Top Thermal Resistance

θ_JA

θ_JC-PCB

θ_JC

Note 2

Note:

2. θ_JAis tested in still air on IR3823A evaluation board. The board uses a 4-layer ꢀ.ꢁ” x ꢀ.ꢀ” FRꢂ PCB.

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Electrical specifications

7.1

Recommended operating conditions

Description

Min

Max

Unit

Note

Note 3, Note 4 & 7

Note 5, Note 6

Note 6

PV_inVoltage Range

4.5

0.6

Typical Output Voltage Range

Continuous Output Current Range

Typical Switching Frequency

Operating Junction Temperature

600

-40

2000

125

kHz

°C

Note 7

Note:

3. A common practice is to have 20% margin on the maximum SW node voltage in the design. A 2Ω resistor in series

with the BOOT pin is recommended for PVin ꢃ ꢄꢅ.ꢀ V to ensure the maximum SW node spike voltage does not

exceed 20 V. Alternatively, an RC snubber can be used at the SW node to reduce the SW node spike.

4. For single-rail applications with PV_in= V_in= 4.3 V-5.4 V, the internal LDO may enter dropout mode. OCP limits can

be reduced due to the lower VCC voltage.

5. The maximum output voltage is limited by the minimum off-time. Please refer to Section 12.13 for details. Also

note that OCP limit may be degraded when off-time is close to the minimum off-time.

6. Maximum output current capability can be reduced at elevated ambient temperatures. Lower VCC voltage can

result in higher R_{DS (ON)}and therefore require more thermal derating.

7. The maximum LDO output current must be limited to 50 mA or less for operations requiring the full operating

temperature range of -40 °C ꢀ T_Jꢀ 125 °C. Thermal derating may be needed for operation at elevated ambient

temperatures to ensure the junction temperature remains within the recommended operating range.

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Electrical specifications

7.2

Electrical characteristics

Note:

Unless otherwise specified, the specifications apply over ꢂ.ꢆ V ꢇ Vin = PVin ꢇ ꢄꢈ V, ꢉ °C < T_J< 125 °C.

Typical values are specified at Ta = 25 °C.

Parameter

Symbol

Conditions

Min Typ Max Unit

Power Stage

R_{DS (on)_Top}

R_{DS (on)_Bot}

V_BOOT– V_SW= 5.0 V, T_j= 25 C

VCC = 5.0 V, T_j= 25 C

I(Boot) = 25 mA

Top Switch

mΩ

29.5

Bottom Switch

370 600

Bootstrap Forward Voltage

En = 0 V

300

V_SW

SW float voltage

Dead Band Time

En = high, No Switching

SW node rising edge, Note 8

SW node falling edge, Note 8

300

T_db

Supply Current

I_{in (Standby)}

I_{in (Static)}

En = Low, No Switching

En = 2 V, No Switching

µA

Vin Supply Current (standby)

Vin Supply Current (static)

Soft Start

2.3

0.7

2.8

1.5

SS = GND

Soft Start time

SS time

V_FB

SS = VCC/Floating

Feedback Voltage

0.6

Feedback Voltage

-0.5

-1

+0.5

0°C < T_j< 85 °C, Note 9

-40 °C < T_j< 125 °C, Note 9

V_FB= 0.6 V, T_j= 25 C

Accuracy

-0.15

+0.15 A

V_FBInput Current

IV_FB

On-Time Timer Control

Vin = 12 V, Vo = 1 V,

152

114

91.5

TON/MODE = ꢁ kΩ, ꢂꢁ.ꢃ kΩ, Note 10

Vin = 12 V, Vo = 1 V,

TON/MODE = ꢂ.ꢃ kΩ, ꢂꢄ.ꢂ kΩ, Note 10

Vin = 12 V, Vo = 1 V,

TON/MODE = ꢄ.ꢅꢆ kΩ, ꢂꢅ kΩ, Note 10

Vin = 12 V, Vo = 1 V,

TON/MODE = ꢇ.ꢅꢈ kΩ, ꢂꢉ.ꢄ kΩ, Note 10

Vin = 12 V, Vo = 1 V,

On Time

T_on

66.5

58.5

TON/MODE = ꢅ.ꢃꢇ kΩ, ꢂꢈ.ꢊ kΩ, Note 10

Vin = 12 V, Vo = 1 V,

TON/MODE = ꢃ.ꢊꢉ kΩ, ꢄꢂ.ꢃ kΩ, Note 10

Vin = 12 V, Vo = 1 V,

TON/MODE = ꢊ.ꢇꢄ kΩ, ꢄꢅ.ꢆ kΩ, Note 10

Vin = 12 V, Vo = 1 V,

TON/MODE = ꢈ.ꢈꢊ kΩ, ꢄꢈ.ꢊ kΩ, Note 10

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Electrical specifications

Parameter

Symbol

Conditions

Min Typ Max Unit

Vin = 12 V, Vo = 1 V,

114

TON/MODE = Floating, Note 10

Vin = 12 V, Vo = 0 V

Minimum On-Time

Minimum Off-Time

VCC LDO Output

T_{on (Min)}

T_{off (Min)}

270 360

T_j= 25 C, V_FB= 0 V

5.5 V ꢋ Vin ꢋ 17 V, when Icc = 50 mA,

Cload = 2.2 µF

VCC

4.7 5.0

5.3

Output Voltage

VCC_drop Vin = 4.3 V, Icc = 50 mA, Cload = 2.2 µF

I_short

300

VCC Dropout

Short Circuit Current

Under Voltage Lockout

VCC-Start Threshold

VCC-Stop Threshold

Enable-Start-Threshold

Enable-Stop-Threshold

Input Impedance

5.5 V ꢋ Vin ꢋ 17 V

Vcc_UVLO_Start VCC Rising Trip Level

Vcc_UVLO_Stop VCC Falling Trip Level

En_UVLO_Start ramping up

En_UVLO_Stop ramping down

R_EN

3.8 4.0

3.6 3.8

4.2

4.0

1.14 1.2 1.36

0.9 1.06

500 915 1500

k

Over Current Limit

Current Limit Threshold

(Valley Current)

Ioc

T_j= 25 °C, VCC = 5.0 V

3.3 4.5

5.4

Over Voltage Protection

FB Rising

115 121 125

110 115 120

4.0

OVP_Vth

% Vref

µs

OVP Trip Threshold

FB Falling, OVP hysteresis

OVP_Tdly

OVP Protection Delay

Under Voltage Protection

UVP Trip Threshold

UVP_Vth

FB Falling

75 % Vref

µs

UVP_Tdly

UVP Protection Delay

Hiccup Blanking Time

Tblk_Hiccup

Power Good

VPG (upper)

VPG (lower)

I_PG

FB Rising

95 % Vref

90 % Vref

Pgood Turn on Threshold

Pgood Turn off Threshold

Pgood Sink Current

Pgood Voltage Low

FB Falling

PGood = 0.5 V, En = 2 V

Vin = VCC = 0 V, Rpull-up = ꢃꢁ kΩ to 3.3 V

FB Rising, see VPG (upper)

FB < VPG (lower) or FB > VPG (upper)

2.5

V_{PG (low)}

0.3

2.5

0.5

V_{PG (on)_Dly}

V_{PG (comp)_Dly}

µs

Pgood Turn on Delay

Pgood Comparator Delay

3.5

Pgood Open Drain Leakage

Current

PGood = 3.3 V

µA

Thermal Shutdown

Hysteresis

140

Note 8

°C

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Electrical specifications

Note:

8. Guaranteed by construction and not tested in production.

9. Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in

production.

10. Ton is trimmed so that the target switching frequency is achieved at around 1.5 A load current.

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Typical efficiency and power loss curves

8.1

PV_in= V_in= ꢀꢁ V, F_sw= ꢃꢄꢄ kHz

PV_in= V_in= 12 V, VCC = Internal LDO, I_o= 0 A - 3 A, F_sw= 600 kHz, Room Temperature, No Air Flow. Note that the

efficiency and power loss curves include losses of the IR3823A, inductor losses, losses of the input and output

capacitors, and PCB trace losses. The table below shows the inductors used for each of the output voltages in

the efficiency measurement.

Table 1

Vout (V)

Inductors for PV_in= V_in= 12 V, F_s= 600 kHz

Lout (nH)

1000

P/N

Size (mm)

4.0 x 4.0 x 2.1

DCR (m)

10.8

XFL4020-102ME

XFL4020-152ME

XFL4020-222ME

1.0

1.2

1.8

3.3

5.0

1500

14.4

1500

14.4

2200

21.35

2200

PVin = Vin = 12V, Fsw = 600kHz - Internal LDO, Natural Convention, Ta = 25°C

100

1.0V - DEM

1.0V - FCCM

1.2V - DEM

1.2V - FCCM

1.8V - DEM

1.8V - FCCM

3.3V - DEM

3.3V - FCCM

5.0V - DEM

5.0V - FCCM

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Io (A)

PVin = Vin = 12V, Fsw = 600kHz - Internal LDO, Natural Convention, Ta = 25°C

1.0V - DEM

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

1.0V - FCCM

1.2V - DEM

1.2V - FCCM

1.8V - DEM

1.8V - FCCM

3.3V - DEM

3.3V - FCCM

5.0V - DEM

5.0V - FCCM

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Io (A)

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Typical efficiency and power loss curves

8.2

PV_in= V_in= ꢀꢁ V, F_sw= 8ꢄꢄ kHz

PV_in= V_in= 12 V, VCC = Internal LDO, Io = 0 A - 3 A, F_sw= 800 kHz, Room Temperature, No Air Flow. Note that the

efficiency and power loss curves include losses of the IR3823A, inductor losses, losses of the input and output

capacitors, and PCB trace losses. The table below shows the inductors used for each of the output voltages in

the efficiency measurement.

Table 2

Inductors for PVin = Vin = 12 V, Fsw = 800 kHz

Vout (V)

Lout (nH)

1000

P/N

Size (mm)

4.0 x 4.0 x 2.1

DCR (m)

10.8

XFL4020-102ME

XFL4020-152ME

XFL4020-222ME

1.0

1.2

1.8

3.3

5.0

1500

14.4

1500

14.4

2200

21.35

2200

PVin = Vin = 12V, Fsw = 800kHz - Internal LDO, Natural Convention, Ta = 25°C

100

1.0V - DEM

1.0V - FCCM

1.2V - DEM

1.2V - FCCM

1.8V - DEM

1.8V - FCCM

3.3V - DEM

3.3V - FCCM

5.0V - DEM

5.0V - FCCM

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Io (A)

PVin = Vin = 12V, Fsw = 800kHz - Internal LDO, Natural Convention, Ta = 25°C

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

1.0V - DEM

1.0V - FCCM

1.2V - DEM

1.2V - FCCM

1.8V - DEM

1.8V - FCCM

3.3V - DEM

3.3V - FCCM

5.0V - DEM

5.0V - FCCM

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Io (A)

Final Datasheet

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Typical efficiency and power loss curves

8.3

PV_in= V_in= ꢀꢁ V, F_sw= ꢀꢄꢄꢄ kHz

PV_in= V_in= 12 V, VCC = Internal LDO, Io = 0 A - 3 A, F_sw= 1000 kHz, Room Temperature, No Air Flow. Note that the

efficiency and power loss curves include losses of the IR3823A, inductor losses, losses of the input and output

capacitors, and PCB trace losses. The table below shows the inductors used for each of the output voltages in

the efficiency measurement.

Table 3

Inductors for PVin = Vin = 12 V, Fsw = 1000 kHz

Vout (V)

Lout (nH)

1000

P/N

Size (mm)

4.0 x 4.0 x 2.1

DCR (m)

10.8

XFL4020-102ME

XFL4020-152ME

XFL4020-222ME

1.0

1.2

1.8

3.3

5.0

1500

14.4

1500

14.4

2200

21.35

2200

PVin=Vin=12V, Fsw = 1000kHz - Internal LDO, Natural Convention, Ta = 25°C

100

1.0V - DEM

1.0V - FCCM

1.2V - DEM

1.2V - FCCM

1.8V - DEM

1.8V - FCCM

3.3V - DEM

3.3V - FCCM

5.0V - DEM

5.0V - FCCM

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Io (A)

PVin=Vin=12V, Fsw = 1000kHz - Internal LDO, Natural Convention, Ta = 25°C

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

1.0V - DEM

1.0V - FCCM

1.2V - DEM

1.2V - FCCM

1.8V - DEM

1.8V - FCCM

3.3V - DEM

3.3V - FCCM

5.0V - DEM

5.0V - FCCM

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Io (A)

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Thermal de-rating cuves

Measurement is done on IR3823A evaluation board at 200 LFM. The PCB is a 4-layer board with 1.8 oz. copper for

top and bottom layers and 2 oz. copper for the inner layers, FR4 material, size 2.2” x 2.6”.

PVin = Vin = 12V, Vout = 1.2V, Fsw = 800 kHz

3.5

2.5

1.5

0.5

Ambient Temperature (^oC)

PVin = Vin = 12V, Vout = 3.3V, Fsw = 800 kHz

3.5

2.5

1.5

0.5

Ambient Temperature (^oC)

PVin = Vin = 12V, Vout = 5.0V, Fsw = 800 kHz

3.5

2.5

1.5

0.5

Ambient Temperature (^oC)

Figure 4 Thermal derating curves, PVin = 12 V, Vout = 1.2 V/3.3 V/5 V, fsw = 800 kHz, VCC = Internal LDO

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

RDS(ON) of MOSFET over temperature

R_DSꢅONꢆof MOSFET over temperature

Rds(on) of Control MOSFET

Vcc = 5V

120

-40

-20

100

140

Temperature (°C)

Rds(on) of Synchronous MOSFET

Vcc = 5V

120

-40

-20

100

140

Temperature (°C)

Figure 5 Rds(on) of MOSFETs over Junction Temperature

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Typical operating characteristics (-ꢇꢄ C ≤ Tj ≤ +ꢀꢁꢂ Cꢆ

Typical operating characteristics ꢅ-ꢇꢄ °C ≤ T_j≤ +ꢀꢁꢂ °Cꢆ

Vin Standby Supply Current

Vin Static Supply Current

3.5

2.5

1.5

0.5

-40 -20

20 40 60 80 100 120 140

Temperature (°C)

-40 -20

20 40 60 80 100 120 140

Temperature (°C)

LDO Voltage at Vin = 5.5 V & 17 V, Icc = 50 mA

LDO Voltage Drop at Vin = 4.3 V, Icc = 50 mA

5.1

300

250

200

150

100

5.05

4.95

Vin = 5.5 V

4.9

Vin = 17 V

4.85

-40 -20

20 40 60 80 100 120 140

Temperature (°C)

-40 -20

20 40 60 80 100 120 140

Temperature (°C)

Enable_Start and Stop Thresholds

Vcc_UVLO Start and Stop Thresholds

1.3

1.25

1.2

4.2

4.1

1.15

1.1

3.9

3.8

3.7

3.6

1.05

En_Start

Vcc_UVLO_Start

Vcc_UVLO_Stop

0.95

0.9

En_Stop

0.85

-40 -20

20 40 60 80 100 120 140

Temperature (°C)

-40 -20

20 40 60 80 100 120 140

Temperature (°C)

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Typical operating characteristics (-ꢇꢄ C ≤ Tj ≤ +ꢀꢁꢂ Cꢆ

VFB

OVP Rise and Fall Thresholds

603

125

120

115

110

105

602

601

600

599

598

597

OVP_Rise

OVP_Fall

-40 -20

20 40 60 80 100 120 140

Temperature (°C)

-40 -20

20 40 60 80 100 120 140

Temperature (°C)

UVP_Threshold

PGood Rise and Fall Thresholds

PGood_Rise

PGood_Fall

-40 -20

20 40 60 80 100 120 140

Temperature (°C)

-40 -20

20 40 60 80 100 120 140

Temperature (°C)

OCP Limit (4.5 A) - 5 V Vcc

5.5

4.5

3.5

OCP - Typ

-40 -20

20 40 60 80 100 120 140

Temperature (°C)

Figure 6 Typical operating characteristics

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Theory of operation

12.1

Fast Constant On-Time Control

The IR3823A features a proprietary fast Constant On-Time (COT) Control, which can provide fast load transient

response, good output regulation and minimize design effort. Fast COT control compares the output voltage, V_o,

to a floor voltage combined with an internal ramp signal. When V_odrops below that signal, a PWM signal is

initiated to turn on the high-side FET for a fixed on-time. The floor voltage is generated from an internally-

compensated error amplifier, which compares Vout with a reference voltage. Compared to the traditional COT

control, fast COT control significantly improves Vout regulation.

12.2

Enable

En pin controls the on/off state of the IR3823A. An internal Under Voltage Lock-Out (UVLO) circuit monitors the

En voltage. When the En voltage is above an internal threshold, the internal LDO starts to ramp up. When the

VCC/LDO voltage rises above the VCC_UVLO_Start threshold, the soft-start sequence starts. The En pin can be

configured in three ways, as shown in Figure 7. With configuration 2, the Enable signal is derived from the PVin

voltage by a resistor divider, R_EN1and R_EN2. By selecting different divider ratios, users can program a UVLO

threshold for the bus voltage. This is a very desirable feature because it prevents the IR3823A from operating until

PVin is higher than a desired voltage level. For some space-constrained designs, the En pin can be directly

connected to PVin without using the external resistor divider, as shown in Configuration 3. The EN pin should not

be left floating. A pull-down resistor in the range of tens of kilohms is recommended. Figure 8 illustrates the

corresponding start-up sequences with three EN configurations.

PVin

Vin

PVin

Vin

R_EN1

Vcc

IR3823A

R_EN2

ꢁ

ꢂꢃꢄ

En = _ꢁ

× ꢆꢇ

ꢈꢉ

En = an external logic signal

Configuration 1

PVin = Vin = En

Configuration 3

+ꢁ

ꢂꢃꢅ

ꢂꢃꢄ

Configuration 2

Figure 7 Enable Configurations

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Theory of operation

Pvin= Vin=12V

PVin=Vin=En=12V

Pvin = Vin = 12V

Vcc_ UVLO

Vcc

Vcc_UVLO

En Threshold

Vcc_ UVLO

En = REN2/(REN1+REN2)*PVin

En>1.2V

En Threshold

Pgood Turn-on

threshold

2.5ms

Pgood Turn-on

threshold

2.5ms

Pgood Turn-on

threshold

2.5ms

PGood

Pgood stays at logic low

ꢁ

ꢂꢃꢄ

En = an external logic signal

Configuration 1

En = _ꢁ

× ꢆꢇ

ꢂꢃꢄ

Pvin = Vin = En

Configuration 3

ꢈꢉ

+ꢁ

ꢂꢃꢅ

Configuration 2

Figure 8 Start-up sequence

12.3

FCCM and DEM Operation

The IR3823A offers two operation modes: Forced Continuous Conduction Mode (FCCM) and Diode Emulation

Mode (DEM). With FCCM, the IR3823A always operates as a synchronous buck converter with a pseudo-constant

switching frequency leading to small output voltage ripple. In DEM, the synchronous FET is turned off when the

inductor current is close to zero, reducing the switching frequency and improving efficiency at light load. At heavy

load, both FCCM and DEM operate in the same way. The operation mode can be selected with the TON/MODE

pin, as shown in Table 4. It should be noted that the selection of the operation mode cannot be changed on the

fly. To load a new TON/MODE configuration, En or VCC voltage must be cycled.

12.4

Pseudo-Constant Switching Frequency

The IR3823A offers eight programmable switching frequencies, f_sw, from 600 kHz to 2 MHz, by connecting an

external resistor from the TON/MODE pin to ground. Based on the selected f_sw, the IR3823A generates the

corresponding on-time of the Control FET for a given PV_inand V_o, as shown by the formula below.

ꢇ_ꢌ

ꢍ

ꢊ

ꢋꢉ

ꢆꢇ

ꢎ

ꢏꢐ

ꢈꢉ

Where f_swis the desired switching frequency. During operation, the IR3823A monitors PV_inand V_o, and can

automatically adjust the on-time to maintain the pre-selected f_sw. As load current increases, the switching

frequency can increase to compensate for power losses.

Table 4 lists resistor values for the TON/MODE pin. In this table, E96 resistors with ±1% tolerance are used. To

load a new TON/MODE configuration, En or VCC voltage must be cycled.

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Theory of operation

Table 4 Configuration Resistors for TON/MODE Pin

TON/MODE Resistor ꢅkΩꢆ

Freq (kHz)

Mode

±1% Tolerance

600

800

1.5

2.49

1000

1200

1400

1600

1800

2000

600

3.48

FCCM

4.53

5.76

7.32

8.87

10.5

12.1

800

1000

1200

1400

1600

1800

2000

800

16.2

DEM

18.7

21.5

24.9

28.7

TON/MODE = Floating

FCCM

12.5

Soft-start

The IR3823A has an internal digital soft-start to control the output voltage rise and to limit the current surge at

start-up. To ensure a correct start-up, the soft-start sequence initiates when the En and VCC voltages rise above

their respective thresholds. The internal soft-start signal linearly rises from 0 V to 0.6 V in a defined time duration.

The soft-start time does not change with the output voltage. During soft-start, the IR3823A operates in DEM until

1 ms after the output voltage ramps above the PGood turn-on threshold. The IR3823A has two soft-start time

options selected by floating or connecting to VCC the SS pin and shorting it to ground. Table 5 lists the

corresponding soft-start times. To load a new SS selection, En or VCC voltage must be cycled.

Table 5 Configuration for SS Pin

Soft-Start Time (ms)

SS = GND

SS = VCC/Floating

12.6

Pre-bias Start-up

The IR3823A is able to start up into a pre-charged output without causing oscillations and disturbances of the

output voltage. When the IR3823A starts up with a pre-biased output voltage, both control FET and Sync FET are

kept off until the internal soft-start signal exceeds the FB voltage.

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Theory of operation

12.7

Internal Low - Dropout ꢅLDOꢆ Regulator

The IR3823A has an integrated low-dropout LDO regulator providing the bias voltage for the internal circuitry. To

minimize standby current, the internal LDO is disabled when the En voltage is pulled low. The Vin pin is the input

of the LDO. IR3823A supports the internal LDO with single rail operation, i.e., the Vin pin should always be

connected to the PVin pin. Figure 9 illustrates the configuration of VCC/LDO, and the Vin pin.

PVin

4.7 uF

Vin

PVin

VCC/LDO

IR3823A

2.2 uF ~10 uF

PGND

Single rail operation with the internal LDO

Figure 9 Configuration of using the internal LDO.

Section 7.1 specified the recommended operating voltage range of PVin. The following design guidelines are

recommended when configuring the VCC/LDO.

•

Place a bypass capacitor to minimize disturbances on the VCC pin. For single rail operation using the internal

LDO, a 4.7 µF low ESR ceramic capacitor must be used between the Vin pin and PGND and a low ESR ceramic

capacitor with value between 2.2 µF and 10 µF is required to be placed close to the VCC/LDO pin with reference

to PGND. A 10 µF MLCC is recommended for the VCC bypass capacitor when VIN is below 5.5 V.

•

For applications using the internal LDO with ꢅ.ꢇ V ꢋ VIN ꢋ ꢃ.ꢅ V, the LDO can be in the dropout mode. It is

important to ensure that the LDO voltage does not fall below the VCC UVLO threshold voltage. At Vin = 4.3 V,

I_CCmust not exceed 50 mA under all operating conditions such as during a step-up load transient, in which the

control loop may require the increase of f_sw. OCP limits can also be reduced due to the lower VCC voltage.

12.8

Over Current Protection ꢅOCPꢆ

The IR3823A offers cycle-by-cycle OCP response with a fixed OCP limit of 4.5 A. Cycle-by-cycle OCP response

allows the IR3823A to fulfill a brief high current demand, such as a high inrush current during start-up. Detailed

operation is explained as follows:

OCP is activated when En voltage is above its threshold. The OCP circuitry monitors the current of the

Synchronous MOSFET through its R_{DS (ON)}. When a new PWM pulse is requested by the control loop, if the current

of the Synchronous MOSFET exceeds the OCP limit, the IR3823A skips the PWM pulse and extends the on-time of

the Synchronous MOSFET until the current drops below the OCP limit. OCP operation is also illustrated in Figure

10. During OCP events, the valley of the inductor current is regulated around the OCP limit. However, during the

first switching cycle when the OCP is tripped, the valley of the inductor current can drop slightly below the OCP

limit. It should be noted that OCP events do not pull the PGood signal low unless V_odrops below the PGood turn-

off threshold. If the OCP event persists, the output voltage can eventually drop below the Under Voltage

Protection (UVP) threshold and trigger UVP. Then the IR3823A enters hiccup mode.

The OCP limit is thermally compensated. The OCP limit specified in Section 7.2 refers to the valley of the inductor

current when OCP is tripped. Therefore, the corresponding output dc current can be calculated as follows:

∆ꢛ_ꢗ

ꢑ_{ꢋꢒꢓ_ꢔꢕꢖ}= ꢑ_ꢗꢘꢙ

ꢚ

ꢜ

Where: I_{out_OCP}= Output dc current when OCP is tripped. I_LIM= OCP limit specified in the Section 7.2, which is the

valley of inductor current. ΔiL = Peak-peak inductor ripple current.

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Theory of operation

To avoid inductor saturation during OCP events, the following criterion is recommended for the inductor

saturation current rating.

ꢑ_ꢏꢝꢓꢞ ꢑ_{ꢗꢘꢙ_ꢟꢝꢠ}ꢚ ∆ꢛ_ꢗ

Where: I_satis the inductor saturation current and I_{LIM_max}is the maximum spec of the OCP limit.

OCP Tripped

Current

Limit

UVP Hiccup

Blanking

time

Inductor

Current

Pulse

skipped

HDrv

LDrv

PGood

UVP

Threshold

PGood Turn-off

Threshold

Figure 10 Cycle-by-cycle OCP response

12.9

Under Voltage Protection ꢅUVPꢆ

Under Voltage Protection (UVP) provides additional protection during OCP fault or other faults. UVP protection

is enabled when the soft-start voltage rises above 100 mV. UVP circuitry monitors FB voltage. When FB is below

the UVP threshold for 5 µs (typical), an under voltage trip signal asserts and both Control MOSFET and

Synchronous MOSFET are turned off. The IR3823A enters hiccup mode with a blanking time of 20 ms, during

which the Control MOSFET and the Synchronous MOSFET remain off. After the completion of blanking time, the

IR3823A attempts to recover to the nominal output voltage with a soft-start, as shown in Figure 10. The IR3823A

will repeat hiccup mode and attempt to recover until the UVP condition is removed.

12.10

Over Voltage Protection ꢅOVPꢆ

Over Voltage Protection (OVP) is achieved by comparing the FB voltage to an OVP threshold voltage. When the

FB voltage exceeds the OVP threshold, an over voltage trip signal asserts after 4 µs (typical) delay. The Control

MOSFET is latched off immediately and PGood flags low. The Synchronous MOSFET remains on to discharge the

output capacitor. When FB voltage drops below around 115% of the reference voltage, Synchronous MOSFET

turns off to prevent complete depletion of the output capacitors. Figure 11 illustrates the OVP operation. The

OVP comparator becomes active when the EN signal is above the start threshold.

IR3823A has a Latched OVP response, i.e., when OVP is triggered, the Control FET remains latched off until either

VCC voltage or the En signal is cycled.

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3 A single-voltage synchronous Buck regulator

Theory of operation

HDrv

LDrv

120%V_ref

115%V_ref

V_ref

91%V_ref

OVP

91%V_ref

84%V_ref

VFB

PGood

Pgood turn-on

delay =2.5 ms

Pgood turn-on

delay =2.5 ms

OVP delay = 4 us

Figure 11 Over voltage protection response and PGood behavior.

12.11

Over Temperature Protection ꢅOTPꢆ

Temperature of the controller is monitored internally. When the temperature exceeds the over temperature

threshold, OTP circuitry turns off both Control and Synchronous MOSFETs and resets the internal soft start.

Automatic restart is initiated when the sensed temperature drops back into the operating range. The thermal

shutdown threshold has a hysteresis of 20 °C.

12.12

Power Good ꢅPGoodꢆ Output

The PGood pin is the open drain of an internal NFET, and must be externally pulled high through a pull-up

resistor. The PGood signal is high when three criteria are satisfied:

1. En signal and VCC voltage are above their respective thresholds.

2. No over voltage or over temperature faults occur.

3. Vo is within regulation.

In order to detect if V_ois in regulation, the PGood comparator continuously monitors FB voltage. When FB voltage

ramps up above the upper threshold, the PGood signal is pulled high after 2.5 ms. When FB voltage drops below

the lower threshold, the PGood signal is pulled low immediately. Figure 11 illustrates the PGood response.

During start-up with a pre-biased output voltage, the PGood signal is held low before the first PWM is generated

and is then pulled high with 2.5 ms delay after FB voltage rises above the PGood threshold. IR3823A also

integrates an additional PFET in parallel to the PGood NFET, as shown in Figure 2. This PFET allows the PGood

signal to stay at logic low when the VCC voltage is not present and the PGood pin is pulled up by an external bias

voltage. Please refer to Figure 8. Since the PGood PFET has relatively higher on resistance, a ꢃꢁ kΩ pull-up

resistor is needed for a Pgood bias voltage of 3.3V to maintain the PGood signal at logic low when the PGood

PFET is on.

12.13

Minimum ON - Time and Minimum OFF - Time

The minimum on-time refers to the shortest time for the Control MOSFET to be reliably turned on. The minimum

off-time refers to the minimum time duration in which the Synchronous FET stays on before a new PWM pulse is

generated. The minimum off-time is needed for IR3823A to charge the bootstrap capacitor, and to sense the

current of the Synchronous MOSFET for OCP.

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Theory of operation

For applications requiring a small duty cycle, it is important that the selected switching frequency results in an

on-time larger than the maximum spec of the minimum on-time in Section 7.2. Otherwise, the resulting switching

frequency may be lower than the desired target. The following formula should be used to check for the minimum

on-time requirement.

ꢇ_ꢌ

> max ꢢꢣꢤꢥ ꢦꢎ ꢊ_{ꢋꢉ ꢨiꢩ}

ꢧ

ꢪ

ꢡꢎ × ꢇ

ꢏꢐ

ꢈꢉ

Where f_swis the desired switching frequency. k is the variation of the switching frequency. As a rule of thumb,

select k = 1.25 to ensure design margin.

For applications requiring a high duty cycle, it is important to make sure a proper switching frequency is selected

so that the resulting off-time is longer than the maximum spec of the minimum off-time in Section 7.2, which can

be calculated as shown below.

ꢇ − ꢇ_ꢌ

ꢈꢉ

> max ꢢꢣꢤꢥ ꢦꢎ ꢊ_{ꢋꢫꢫ ꢨiꢩ}

ꢧ

ꢪ

ꢡꢎ × ꢇ

ꢏꢐ

ꢈꢉ

Where f_swis the desired switching frequency. k is the variation of the switching frequency. As a rule of thumb,

select k = 1.25 to ensure design margin.

The resulting maximum duty cycle is therefore determined by the selected on-time and minimum off-time.

ꢊ

ꢋꢉ

ꢬ_ꢟꢝꢠ

ꢊ

ꢋꢉ

ꢚ ꢊ_{ꢋꢫꢫꢧꢨiꢩꢪ}

12.14

Selection of Feedforward Capacitor and Feedback Resistors

Output voltage can be programmed with an external voltage divider. The FB voltage is compared to an internal

reference voltage of 0.6 V. The divider ratio is set to provide 0.6 V at the FB pin when the output is at its desired

value. The calculation of the feedback resistor divider is shown below.

ꢯ_ꢰꢱꢲ

ꢇ_ꢔ= ꢇ × (ꢍ ꢚ

)

ꢭꢮꢫ

ꢯ_ꢰꢱꢳ

Where R_FB1and R_FB2are the top and bottom feedback resistors.

A small MLCC capacitor, C_ff, is preferred in parallel with the top feedback resistor, R_FB1, to provide extra phase

boost and improve the transient load response, as shown in Figure 12. The following formula can be used to

help select C_ffand R_FB1. The value of C_ffis recommended to be 100 pF or higher to minimize the impact of circuit

parasitic capacitance, where L_Oand C_Oare the output LC filter of the buck regulator. Table 6 lists the suggested

ꢌmꢀ for some common outputs. C_ffand R_FB1may be further optimized based on the transient load tests.

ꢵ ꢴ

√

ꢌ

ꢯ_ꢰꢱꢲꢴ_ꢫꢫ

ꢶ × 4.ꢷ

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Theory of operation

RFB 1

RFB 2

Cff

Figure 12 Configuration of feedforward capacitor, Cff.

Table 6 Selection of m

0.3

0.5

0.7

ꢇ.ꢁ V ꢋ Vo ꢋ 6.0 V

1.2 V < Vo < 3.0 V

Vo ꢋ ꢂ.ꢄ V

12.15

Resistors for Configuration Pins

To properly configure the TON/ MODE pin, E96 resistors with ±1% tolerance must be used per Table 4 and Section

7.2. If E12 resistor values are preferred, the E96 resistors can be replaced with two or three E12 resistors in series,

as shown in Table 7. Note that the tolerance of E12 resistors must be ±0.1%.

Table 7 Replacement of E96 configuration resistors with E12 resistors in series

E96 ±1%

R ꢍkΩꢎ

4.53

1.50

5.76

2.49

7.32

3.45

8.87

10.5

12.1

21.5

E12 ±0.1% (R = R_S1+ R_S2or R_S1+ R_S2+ R_S3)

R_S1ꢍkΩꢎ

R_S2ꢍkΩꢎ

1.8

R_S3ꢍkΩꢎ

2.7

1.5

5.6

1.8

6.8

3.3

8.2

N/A

0.18

0.15

0.68

0.56

0.15

0.68

0.47

0.1

3.3

3.9

24.9

16.2

28.7

21.5

24.9

2.7

1.2

1.8

3.3

2.7

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Design example

13 Design example

In this section, an example is used to demonstrate how to design a buck regulator with the IR3823A. The

application circuit is shown in Figure 13. The design specifications are given below:

•

PV_in= 12 V (±10%)

V_O= 1.2 V

I_O= 3 A

V_Oripple voltage = ± 1% of V_o

Load transient response = ± 3% of V_Owith a step load current = 1 A and slew rate = 2.5 A/µs

13.1

Enabling the IRꢈ8ꢁꢈA

The IR3823A has a precise Enable threshold voltage, which can be used to implement a UVLO of the input bus

voltage by connecting the En pin to Pvin with a resistor divider, as shown in Configuration 2 of Figure 7. The

Enable feedback resistor, R_EN1and R_EN2, can be calculated as follows.

ꢯ_ꢸꢹꢳ

ꢆꢇ

ꢞ ꢇ_{ꢸꢹꢧꢨꢺꢻꢪ}

ꢈꢉꢧꢨiꢩꢪ

ꢯ_ꢸꢹꢲꢚ ꢯ_ꢸꢹꢳ

ꢇ_{ꢸꢹꢧꢨꢺꢻꢪ}

ꢆꢇ_{ꢈꢉꢧꢨiꢩꢪ}− ꢇ_{ꢸꢹꢧꢨꢺꢻꢪ}

ꢯ_ꢸꢹꢳꢞ ꢯ_ꢸꢹꢲ

Where V_{EN (max)}is the maximum spec of the Enable-start-threshold as defined in Section 7.2. For Pvin_(min)=10.8 V,

select R_EN1= ꢅꢆ.ꢆ kΩ and R_EN2= ꢊ.ꢃ kΩ.

13.2

Programming the Switching Frequency and Operation Mode

The IR3823A has very good efficiency performance and is suitable for high switching frequency operation. In this

case, 1000 kHz is selected to achieve a good compromise between efficiency, passive component size and

dynamic response. In addition, FCCM operation is selected to ensure a small output ripple voltage over the entire

load range. To select 1000 kHz and FCCM operation, the TON/MODE pin is connected to a 2.49 kΩ resistor to GND

per Table 4.

13.3

Selecting Input Capacitors

Without input capacitors, the pulse current of the Control MOSFET is provided directly from the input supply.

Due to the impedance of the cable, the pulse current can cause disturbance on the input voltage and potential

EMI issues. The input capacitors filter the pulse current, resulting in almost constant current from the input

supply. The input capacitors should be selected to tolerate the input pulse current, and to reduce the input

voltage ripple. The RMS value of the input ripple current can be expressed by:

ꢑ_ꢁꢙꢼ= ꢑ × ꢬ × ꢧꢍ − ꢬꢪ

√

ꢋ

ꢇ

ꢋ

ꢬ =

ꢆꢇ

ꢈꢉ

Where I_RMSis the RMS value of the input capacitor current. I_ois the output current and D is the Duty Cycle. For I_O

= 3 A and D_(max)= 0.1, the resulting RMS current flowing into the input capacitor is I_rms= 0.9 A.

To meet the requirement of the input ripple voltage, the minimum input capacitance can be calculated as

follows.

Final Datasheet

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Design example

ꢑ_ꢋ× ꢧꢍ − ꢬꢪ × ꢬ

ꢴ_{ꢈꢉꢧꢨiꢩꢪ}

ꢧ

ꢪ

ꢎ × ꢧ∆ꢆꢇ − ꢽꢾꢯ × ꢑ_ꢋ× ꢍ − ꢬ ꢪ

ꢏꢐ

ꢈꢉ

Where ∆Pvin is the maximum allowable peak-to-peak input ripple voltage, and ESR is the equivalent series

resistance of the input capacitors. Ceramic capacitors are recommended due to low ESR, ESL and high RMS

current capability. For I_o= 3 A, f_sw= 10ꢁꢁ kHz, ESR = ꢇ mΩ, and ∆Pvin = 240 mV, C_in(min)> 2.0 µF. To account for the

derating of ceramic capacitors under a bias voltage, two 22 µF/0805/25V MLCC are used for the input capacitor.

In addition, a bulk capacitor is recommended if the input supply is not located close to the voltage regulator.

13.4

Inductor Selection

The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor

value results in a large ripple current, lower efficiency and high output noise, but helps with size reduction and

transient load response. Generally, the desired peak-to-peak ripple current in the inductor ꢍ∆iꢎ is found between

20% and 50% of the output current.

The inductor saturation current must be higher than the maximum spec of the OCP limit plus the peak-to-peak

inductor ripple current. For some core material, inductor saturation current may decrease with increasing

temperature. It is important to check the inductor saturation current at the maximum operating temperature.

The inductor value for the desired operating ripple current can be determined using the following relations:

ꢬ_ꢟꢈꢉ

ꢵ = ꢧꢆꢇ_{ꢈꢉꢧꢨꢺꢻꢪ}− ꢇ ꢪ ×

ꢋ

∆ꢛ_{ꢗꢧꢨꢺꢻꢪ}× ꢿ

ꢏꢐ

ꢇ

ꢋ

ꢬ_ꢟꢈꢉ

ꢆꢇ

ꢈꢉꢧꢨꢺꢻꢪ

ꢑ_ꢏꢝꢓꢞ ꣀꢴꢆ_ꢟꢝꢠꢚ ∆ꢛ_{ꢗꢧꢨꢺꢻꢪ}

Where: PV_{in (max)}= Maximum input voltage; ∆iL_max= Maximum peak-to-peak inductor ripple current; OCP_max

maximum spec of the OCP limit as defined in Section 7.2; and I_sat= inductor saturation current. In this case, select

inductor L = 1.0 µH to achieve ∆iL_max= 35% of I_omax. The I_satshould be no less than 6.0 A.

13.5

Output Capacitor Selection

The output capacitor selection is mainly determined by the output voltage ripple and transient requirements.

To satisfy the V_oripple requirement, C_oshould satisfy the following criterion:

∆ꢛ_ꢗꢟꢝꢠ

ꢴ_ꢋ>

ꣁ × ∆ꢇ × ꢎ

ꢋꢭ

ꢏꢐ

Where ∆V_oris the desired peak-to-peak output ripple voltage. For ∆iL_max= 1 A, ∆V_or= 12 mV, f_sw= 1000 kHz, C_omust

be larger than 12 µF. The ESR and ESL of the output capacitors, as well as the parasitic resistance or inductance

due to PCB layout, can also contribute to the output voltage ripple. It is suggested to use Multi-Layer Ceramic

Capacitor (MLCC) for their low ESR, ESL and small size.

To meet the transient response requirements, the output capacitors should also meet the following criterion:

ꢵ × ∆ꢑ_ꢋ^ꢳ_{ꢧꢨꢺꢻꢪ}

ꢴ_ꢋ>

ꢜ × ∆ꢇ × ꢇ

ꢋꢗ

ꢋ

Where ∆V_OLis the allowable V_odeviation during the load transient. ∆I_o(max)is the maximum step load current.

Please note that the impact of ESL, ESR, control loop response, transient load slew rate, and PWM latency is not

considered in the calculation shown above. Extra capacitance is usually needed to meet the transient

requirements. As a rule of thumb, we can triple the C_othat is calculated above as a starting point, and then

Final Datasheet

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Design example

optimize the design based on bench measurement. In this case, to meet the transient load requirement ꢍi.e. ∆V_OL=

36 mV, ∆I_o(max)= 1 A), select C_o= ~36 µF. For more accurate estimation of C_o, simulation tools should be used to aid

the design.

13.6

Output Voltage Programming

Output voltage can be programmed with an external voltage divider. The FB voltage is compared to an internal

reference voltage of 0.6 V. The divider ratio is set to provide 0.6 V at the FB pin when the output is at its desired

value. The calculation of the feedback resistor divider is shown below.

ꢯ_ꢰꢱꢲ

ꢇ = ꢇ × ꢧꢍ ꢚ

ꢪ

ꢋ

ꢭꢮꢫ

ꢯ_ꢰꢱꢳ

Where R_FB1and R_FB2are the top and bottom feedback resistors. Select R_FB1= 10 kΩ and R_FB2= 10 kΩ, to achieve V_o

= 1.2 V.

13.7

Feedforward Capacitor

A small MLCC capacitor, C_ff, can be placed in parallel with the top feedback resistor, R_FB1, to improve the transient

response. Based on Section 12.14, C_ffcan be selected using the following formula.

ꢵ ꢴ

√

ꢌ

ꢯ_ꢰꢱꢲꢴ_ꢫꢫ

ꣂ.ꣃ × 4.ꢷ

With Lo = 1.0 µH, Co = 36 µF and R_FB1= 10 kΩ, C_ff= ~150 pF. C_ffcan be further optimized based on bench testing of

transient load response.

13.8

Bootstrap Capacitor

For most applications, a 0.1 µF ceramic capacitor is recommended for bootstrap capacitor placed between SW

and BOOT. For applications requiring Pvin equal to or above 14 V, a small resistor between 1 Ω and 2 Ω can be

used in series with the BOOT pin to ensure the maximum SW node spike voltage does not exceed 20 V.

13.9

Vin and VCC/LDO bypass Capacitor

Please see the recommendation in Section 12.7. A 10 µF MLCC is selected for the VCC/LDO bypass capacitor and

a 4.7 µF MLCC is selected for the Vin bypass capacitor.

Final Datasheet

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Application information

14 Application information

14.1

Application Diagram

Cin2

2 x 22 uF

CinHF Cin1

0.1 nF 4.7 uF

Vin = 12 V ± 10%

REN1

REN2

Optional

49.9 k ꢀ

7.5 k ꢀ

Cvin

4.7 uF

RBoot

0 ꢀ

PVin

Vin

BOOT

CBoot

0.1 uF

VCC/LDO

Vo = 1.2 V

RPG

49.9 k ꢀ

Cvcc

10 uF

PGood

1.0 uH

CoHF

1x0.1 uF

Co1

Co2

1x 4.7 uF

PGood

IR3823A

1x 47 uF

RFB1

10 k ꢀ

Cff

150 pF

Float (4 ms)

TON/MODE

RTon

2.49 k ꢀ

RFB2

10 k ꢀ

PGND

AGND

Figure 13 Application diagram of IR3823A. Pvin = 12 V, Vo = 1.2 V, Io = 3 A, fsw = 1000 kHz.

14.2

Typical Operating Waveforms

PV_in= V_in= 12.0 V, Vo = 1.2 V, I_o= 0 – 3 A, f_sw= 1000 kHz, Room Temperature, no airflow

Figure 14

Start up at 3 A Load, (Ch1: Pvin, Ch2: Pgood, Ch3: Enable, Ch4: Vout)

Final Datasheet

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Application information

Figure 15

Pre-bias Start up at 0 A Load, (Ch1: Pvin, Ch2: Pgood, Ch3: Enable, Ch4: Vout)

Figure 16

Vout ripple at 3 A Load, fsw = 1000 kHz, (Ch4: Vo)

Figure 17

SW node, 3 A load, fsw = 1000 kHz, (Ch2: SW)

Final Datasheet

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Application information

Figure 18

Short circuit and UVP (Hiccup), (Ch2: Vo, Ch3: Pgood)

Load step up: 2 A to 3 A

Load step down: 3 A to 2 A

Figure 19

Transient response at 1 A step load current: Io= 2 A – 3 A, (Ch1: Io, Ch4: Vo), pk-pk: 30.96 mV,

fsw = 1000 kHz

Final Datasheet

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Layout recommendations

15 Layout recommendations

PCB layout is very important when designing high frequency switching converters. Layout will affect noise pickup

and can cause a good design to perform with less than expected results. The following design guidelines are

recommended to achieve the best performance.

•

Bypass capacitors, including input/output capacitors, Vin and VCC bypass capacitors, should be placed as

close to the corresponding pins as possible.

•

Place bypass capacitors from IR3823A power input (Drain of Control MOSFET) to PGND (Source of Synchronous

MOSFET) to reduce noise and ringing in the system. The output capacitors should be terminated to a ground

plane that is away from the input PGND to mitigate switching spikes on the Vout. The Vin and VCC bypass

capacitors should be terminated to PGND.

•

Place a boot strap capacitor as close as possible to IR3823A BOOT and SW pins to minimize loop inductance.

SW node copper should only be routed on the top layer to minimize the impact of switching noise.

Connect the AGND pin to the PGND pad through a single point connection. On the IR3823A demo board, AGND

pin is connected to the exposed AGND pad (Pin 4) and then connected to the internal PGND layer through

thermal via holes.

•

Via holes can be placed on Pvin and PGND pads to aid thermal dissipation.

Wide copper polygons are desired for Pvin and PGND connections in favor of power loss reduction and thermal

dissipation. Sufficient via holes should be used to connect power traces between different layers.

•

To implement the V_osensing, the following design guidelines should be followed, as illustrated in Figure 13.

The output voltage can be sensed from a high-frequency bypass capacitor of 0.1 µF or higher, through

a 15 mil PCB trace.

Keep the Vout sense line away from any noise sources and shield the sense line with ground planes.

The sense trace is connected to a feedback resistor divider with the lower resistor terminated at the

AGND pin.

The EN pin and configuration pins including TON/MODE and SS should be terminated to a quiet ground. On the

IR3823A standard demo board, they are terminated to the PGND copper plane away from the power current flow.

Alternatively, they can be terminated to a dedicated AGND PCB trace.

15.1

Solder mask

Evaluation has shown that the best overall performance is achieved using the substrate/PCB layout as shown in

the following figures. PQFN devices should be placed to an accuracy of 0.050 mm on both X and Y axes. Self-

centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the

limits of self-centering on specific processes.

Infineon recommends that larger Power or Land Area pads are Solder Mask Defined (SMD). This allows the

underlying copper traces to be as large as possible, which helps in terms of current carrying capability and device

cooling capability. When using SMD pads, the underlying copper traces should be at least 0.05 mm larger (on

each edge) than the openings in the solder mask. This allows for layers to be misaligned by up to 0.1 mm on both

axes. Ensure that the solder resist between the smaller signal lead areas is at least 0.15 mm wide due to the high

x/y aspect ratio of the solder mask strip.

Final Datasheet

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Layout recommendations

PCB METAL PAD SPACING

1.280

1.510

1.635

1.490

0.770

1.600

0.280

1.450

1.050

1.400

1.730

0.500

0.300

0.650

0.750

0.500

0.450

2.400

1.700

SOLDER MASK DESIGN

1.180

1.410

0.350

1.410

1.270

0.710

0.780

1.060

0.670

0.550

0.475

1.500

0.400

0.950

0.350

0.575

0.350

0.450

0.440

1.455

1.450

0.500

1.300

0.700

0.750

0.500

0.450

1.700

2.300

1.700

Figure 20

PCB metal pad spacing and Solder mask (all dimensions in mm)

15.2

Stencil design

Stencils for PQFN packages can be used with thicknesses of 0.100-0.250 mm (0.004-ꢁ.ꢁꢂꢁ”ꢎ. Stencils thinner than

0.100 mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the

ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125 mm-0.200 mm

(0.005-ꢁ.ꢁꢁꢈ”ꢎ, with suitable reductions, give the best results. A recommended stencil design is shown below.

This design is for a stencil thickness of ꢁ.ꢂꢄꢊ mm ꢍꢁ.ꢁꢁꢃ”ꢎ. The reduction should be adjusted for stencils of other

thicknesses.

Final Datasheet

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Layout recommendations

SOLDER PASTE STENCIL

0.320

0.690

1.060

0.570

0.345

0.925

0.300

1.000

0.450

0.455

0.370

0.850

0.580

0.575

0.500

0.320

0.280

0.320

0.520

0.320

0.800

0.650

0.655

0.740

0.040

0.680

0.790

0.440

0.600

0.620

0.280

Figure 21

Stencil pad size and spacing (all dimensions in mm)

Final Datasheet

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Package

This section includes mechanical and packaging information for the IR3823A.

16.1

Marking Information

3823A

PRODUCT MARKING

ASSEMBLY SITE CODE

DATE CODE (YWW)

XXXX

LOT CODE

PIN 1 MARKER

Figure 22

Package Marking

16.2

Dimensions

Dimension Table

SIDE VIEW (Back)

Millimeters

MINIMUM

NOMINALMAXIMUM

0.80

0.00

0.20

0.25

0.30

1.10

0.90

0.02

1.00

0.05

0.30

0.35

0.40

1.35

0.25

0.30

0.35

1.25

2.10

0.75

0.526

0.75

1.21

2.25

2.35

1.00

0.90

0.676

0.90

0.776

1.00

1.36

1.46

0.45

0.25

0.35

3.50 BSC

0.50 BSC

0.05

aaa

TOP VIEW

SIDE VIEW (Left)

SIDE VIEW (Right)

aaa

ccc

eee

0.10

0.08

ccc C

SEATING

PLANE

eee

SIDE VIEW (Front)

Final Datasheet

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Package

(b2)

12x

3.500

3.312

3.125

2.875

2.625

2.325

1.565

1.265

0.875

0.575

0.625

0.199

0.000

(b3)

BOTTOM METALIZATION

BOTTOM DETAIL VIEW

Figure 23

Package Dimensions (all dimensions in mm)

Final Datasheet

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IR3823A IPOL

3 A single-voltage synchronous Buck regulator

Environmental qualifications

Qualification Level

Industrial

Moisture Sensitivity

PQFN Package

JEDEC Level 2 @ 260 °C

Human Body Model

Charged Device Model

ANSI/ESDA/JEDEC JS-001, Level 2 (2000 V to < 4000 V)

ANSI/ESDA/JEDEC JS-002, Level Cꢇ ꢍꢏ 1000 V)

Yes

ESD

RoHS Compliant

Final Datasheet

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IR3823AꢀIPOL

IR3823A

RevisionꢀHistory

IR3823A

Revision:ꢀ2022-07-28,ꢀRev.ꢀ2.4

Previous Revision

Revision Date

Subjects (major changes since last revision)

2.0

2.1

2.2

Release of final version

Updated Note 3.

2021-01-15

2021-04-01

(1) Max. Vout updated to 6V in recommended operating conditions; (2) Update to Note 5

and added Note 6; (3) Fixed Typo in Fig. 1 – pad 16 name corrected to AGND.

2021-04-29

2.3

2.4

(1) Updated Ordering Information; (2) Fixed typo in 12.9 - UVP enabled after soft start

reaches 100mV.

2021-08-03

2022-07-28

Updated Orderable Part Number

Trademarks

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failureꢀofꢀsuchꢀcomponentsꢀcanꢀreasonablyꢀbeꢀexpectedꢀtoꢀcauseꢀtheꢀfailureꢀofꢀthatꢀlife-support,ꢀautomotive,ꢀaviationꢀand

aerospaceꢀdeviceꢀorꢀsystemꢀorꢀtoꢀaffectꢀtheꢀsafetyꢀorꢀeffectivenessꢀofꢀthatꢀdeviceꢀorꢀsystem.ꢀLifeꢀsupportꢀdevicesꢀorꢀsystemsꢀare

intendedꢀtoꢀbeꢀimplantedꢀinꢀtheꢀhumanꢀbodyꢀorꢀtoꢀsupportꢀand/orꢀmaintainꢀandꢀsustainꢀand/orꢀprotectꢀhumanꢀlife.ꢀIfꢀtheyꢀfail,ꢀitꢀis

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Rev.ꢀ2.4,ꢀꢀ2022-07-28

IR3823AMTRPBF [INFINEON]

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