IR3865MTR1PBF [INFINEON]
Switching Regulator, Current-mode, 10A, 750kHz Switching Freq-Max, 4 X 5 MM, PQFN-17;
| 型号： | IR3865MTR1PBF |
| 厂家： | 
Infineon |
| 描述： | Switching Regulator, Current-mode, 10A, 750kHz Switching Freq-Max, 4 X 5 MM, PQFN-17 开关 |
| 文件： | 总22页 (文件大小：1280K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD-97606
IR3865MPBF
TM
SupIRBuck
10A HIGHLY INTEGRATED
WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR
Features
Description
The IR3865 SupIRBuckTM is an easy-to-use, fully
integrated and highly efficient DC/DC voltage
regulator. The onboard constant on-time
hysteretic controller and MOSFETs make IR3865
.
.
.
.
.
.
.
Input Voltage Range: 3V to 21V
Output Voltage Range: 0.5V to 12V
Continuous 10A Load Capability
Constant On-Time Control
Compensation Loop not Required
Excellent Efficiency at Very Low Output Currents a space-efficient solution that delivers up to 10A
Programmable Switching Frequency and Soft
Start
of precisely controlled output voltage.
Programmable switching frequency, soft start,
and thermally compensated over current
protection allows for a very flexible solution
suitable for many different applications and an
ideal choice for battery powered applications.
.
Thermally Compensated Over Current
Protection
Power Good Output
Precision Voltage Reference (0.5V, +/-1%)
Enable Input with Voltage Monitoring Capability
Pre-bias Start Up
.
.
.
.
.
.
.
.
Thermal Shut Down
Additional features include pre-bias startup, very
precise 0.5V reference, over/under voltage shut
down, power good output, and enable input with
voltage monitoring capability.
Under/Over Voltage Fault Protection
Forced Continuous Conduction Mode Option
Very Small, Low Profile 4mm x 5mm QFN
Package
Applications
.
.
.
.
Notebook and Desktop Computers
Game Consoles
Consumer Electronics – STB, LCD, TV, Printers
General Purpose POL DC-DC Converters
8/8/2012 Rev3.1
1
IR3865MPBF
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND unless otherwise specified)
•
•
•
•
•
•
•
•
•
•
•
•
VIN, FF …………………………………………………. -0.3V to 25V
VCC, PGOOD, EN …………………………………..... -0.3V to 8.0V
BOOT …………………………………………………… -0.3V to 33V
PHASE …………………………………………………. -0.3V to 25V(DC), -5V(100ns)
BOOT to PHASE ………………………………………. -0.3V to 8V
ISET …………………………………………………….. -0.3V to 25V, 30mA
PGND to GND …………………………………………. -0.3V to +0.3V
All other pins …………………………………………… -0.3V to 3.9V
Storage Temperature Range ………………………… -65°C To 150°C
Junction Temperature Range ………………………… -40°C To 150°C
ESD Classification …………………………………….. JEDEC Class 1C
Moisture Sensitivity Level ……………………..……… JEDEC Level 2 @ 260°C (Note 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specifications are not implied.
PACKAGE INFORMATION
4mm x 5mm POWER QFN
JA 32o C /W
J -PCB 2o C /W
ORDERING INFORMATION
PKG DESIG
PACKAGE
PIN COUNT
PARTS PER
REEL
DESCRIPTION
M
M
IR3865MTRPbF
IR3865MTR1PbF
17
17
4000
750
8/8/2012 Rev3.1
2
IR3865MPBF
Simplified Block Diagram
8/8/2012 Rev3.1
3
IR3865MPBF
Pin Description
I/O
NUMBER LEVEL
NAME
DESCRIPTION
FCCM
1
3.3V
Forced Continuous Conduction Mode (CCM). Ground this pin
to enable diode emulation mode or discontinuous conduction
mode (DCM). Pull this pin to 3.3V to operate in CCM under all
load conditions.
ISET
PGOOD
GND
FB
2
3
Connecting resistor to PHASE pin sets over current trip point.
5V
Power good open drain output – pull up with a resistor to 3.3V
4,17
5
Reference Bias return and signal reference.
3.3V
3.3V
Inverting input to PWM comparator, OVP / PGOOD sense.
SS
6
Soft start/shutdown. This pin provides user programmable soft-
start function. Connect an external capacitor from this pin to
GND to set the startup time of the output voltage. The converter
can be shutdown by pulling this pin below 0.3V.
NC
7
8
-
-
3VCBP
3.3V
For internal LDO. Bypass with a 1.0µF capacitor to AGND. A
resistor in series with the bypass capacitor may be required in
single-ground plane designs. Refer to Layout Recommendation
for details.
NC
9
-
-
VCC
10
5V
VCC input. Gate drive supply. A minimum of 1.0µF ceramic
capacitor is required.
PGND
PHASE
VIN
11
12
13
14
Reference Power return.
VIN
VIN
Phase node (or switching node) of MOSFET half bridge.
Input voltage for the system.
BOOT
VIN +VCC Bootstrapped gate drive supply – connect a capacitor to
PHASE.
FF
15
16
VIN
5V
Input voltage feed forward – sets on-time with a resistor to VIN.
EN
Enable pin to turn on and off the device. Use two external
resistors to set the turn on threshold (see Electrical
Specifications) for input voltage monitoring.
8/8/2012 Rev3.1
4
IR3865MPBF
Recommended Operating Conditions
Symbol
VIN
Definition
Input Voltage
Min
3
Max
21*
Unit
VCC
VOUT
IOUT
Fs
Supply Voltage
4.5
5.5
V
Output Voltage
0.5
0
12
10
Output Current
A
Switching Frequency
Junction Temperature
N/A
-40
750
125
kHz
oC
TJ
* PHASE pin must not exceed 25V.
Electrical Specifications
Unless otherwise specified, these specification apply over VIN = 12V, 4.5V<VCC<5.5V, 0oC ≤ TJ ≤ 125oC.
PARAMETER
CONTROL LOOP
Reference Accuracy, VREF
On-Time Accuracy
Min Off Time
NOTE
TEST CONDITION
VFB = 0.5V
MIN TYP MAX UNIT
0.495 0.5
0.505
320
V
ns
RFF = 180K, TJ = 65oC
280
300
500
10
ns
Soft-Start Current
EN = High
8
12
0
µA
mV
DCM Comparator Offset
SUPPLY CURRENT
Measure at VPHASE
-4.5
-2.5
VCC Supply Current
(standby)
EN = Low, No Switching
EN = High, Fs = 300kHz
EN = Low
23
7
µA
mA
µA
VCC Supply Current
(dynamic)
FF Shutdown Current
2
FORCED CONTINUOUS CONDUCTION MODE (FCCM)
FCCM Start Threshold
2
V
V
FCCM Stop Threshold
0.6
8/8/2012 Rev3.1
5
IR3865MPBF
Electrical Specifications (continued)
Unless otherwise specified, these specification apply over VIN = 12V, 4.5V<VCC<5.5V, 0oC ≤ TJ ≤ 125oC.
PARAMETER
GATE DRIVE
Deadtime
NOTE
TEST CONDITION
MIN TYP MAX UNIT
1
Monitor body diode conduction
on PHASE pin
5
30
ns
BOOTSTRAP PFET
Forward Voltage
I(BOOT) = 10mA
300
23
mV
UPPER MOSFET
Static Drain-to-Source On-
Resistance
VCC = 5V, ID = 10A, TJ = 25oC
28
13
21
mΩ
LOWER MOSFET
Static Drain-to-Source On-
Resistance
VCC = 5V, ID = 10A, TJ = 25oC
10.7
mΩ
FAULT PROTECTION
ISET Pin Output Current
On the basis of 25oC
On the basis of 25oC
17
19
µA
ppm/
oC
ISET Pin Output Current
Temperature Coefficient
1
4400
Under Voltage Threshold
Under Voltage Hysteresis
Over Voltage Threshold
Over Voltage Hysteresis
VCC Turn-on Threshold
VCC Turn-off Threshold
VCC Threshold Hysteresis
EN Rising Threshold
EN Hysteresis
Falling VFB & Monitor PGOOD
Rising VFB
0.37
0.4
7.5
0.43
V
1
1
mV
V
Rising VFB & Monitor PGOOD
Falling VFB
-40oC to 125oC
0.586 0.625 0.655
7.5
mV
V
3.9
3.6
4.2
3.9
4.5
4.2
V
300
1.25
400
mV
V
-40oC to 125oC
EN = 3.3V
1.1
1.45
mV
µA
Ω
EN Input Current
15
50
PGOOD Pull Down
Resistance
25
1
PGOOD Delay Threshold
(VSS)
V
Thermal Shutdown
Threshold
1
1
125
140
20
oC
oC
Thermal Shutdown
Threshold Hysteresis
Note 1: Guaranteed by design, not tested in production
Note 2: Upgrade to industrial/MSL2 level applies from date codes 1227(marking explained on
application note AN1132 page 2). Products with prior date code of 1227 are qualified with MSL3
for Consumer Market.
8/8/2012 Rev3.1
6
IR3865MPBF
TYPICAL OPERATING DATA
Tested with demoboard shown in Figure 7, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, TA = 25oC, no
airflow, unless otherwise specified
95%
90%
85%
80%
75%
70%
65%
60%
55%
50%
45%
95%
90%
85%
80%
75%
70%
65%
60%
55%
50%
VOUT = 3.3V; L = 3.3uH, 10.8mΩ
7VIN
VOUT = 1.5V; L = 2.2uH, 6.0mΩ
VOUT = 1.05V; L = 1.5uH, 3.8mΩ
12VIN
16VIN
0.01
0.1
1
10
0.01
0.1
1
10
Load Current (A)
Load Current (A)
Figure 1. Efficiency vs. Load Current for
VOUT = 1.05V
Figure 2. Efficiency vs. Load Current for
VIN = 12V
350
1400
1200
1000
800
600
400
200
0
5.0 Vout
4.0
3.0
2.0
1.0
4.5
3.5
2.5
1.5
0.5
300
250
200
150
100
50
0
0
2
4
6
8
10
200 250 300 350 400 450 500 550 600 650 700 750
Switching Frequency (kHz)
Load Current (A)
Figure 3. Switching Frequency vs.
Load Current
Figure 4. RFF vs. Switching Frequency
1.075
1.070
1.065
1.060
1.055
1.050
1.045
1.075
1.070
1.065
1.060
1.055
1.050
1.045
16VIN
12VIN
7VIN
0
1
2
3
4
5
6
7
8
9
10
7
8
9
10
11
12
13
14
15
16
Load Current (A)
Input Voltage (V)
Figure 5. Load Regulation
Figure 6. Line Regulation at IOUT = 10A
8/8/2012 Rev3.1
7
IR3865MPBF
TYPICAL APPLICATION CIRCUIT
+3.3V
VCC
T P1
R1
VINS
10K
VIN
T P2
VIN
R2
10K
+
C1
1uF
C2
22uF
C3
68uF
EN
T P4
EN
FCCM
R3
200K
T P5
SW1
EN / FCCM
PGND
T P23
VOUTS
C4
0.22uF
R4
T P6
8.66K
PGNDS
VSW
ISET
L1
1.5uH
VSW
VOUT
T P7
VOUT
U1
IR3865
+3.3V
R5
R6
open
C13
open
C6
open
C7
open
C8
open
C9
330uF
C10
47uF
C11
open
C12
0.1uF
1
2
3
4
5
6
7
FCCM
ISET
PGOOD
GND1
FB
10K
R13
open
T P10
PGND
PGOOD
T P11
PGOOD
12
PHASE
IR3865
FB
C24
open
T P24
PGNDS
SS
T P13
SS
SS
C15
open
C16
open
C17
open
C18
open
C19
open
C26
open
C27
open
C20
0.1uF
NC1
+3.3V
T P14
+3.3V
C21
1uF
T P26
AGND
R12
4.99
C25
1uF
C14
open
R7
2.80K
T P18
VOLT AGE SENSE
VCC
T P16
VCC
C23
open
T P27
A
T P25
B
T P17
PGND
R11
20
R9
open
R8
2.55K
R10
open
Q1
open
1
T P28
VID
C22
open
Figure 7. Typical Application Circuit for VOUT = 1.05V, Fs = 300kHz
Demoboard Bill of Materials
QTY REF DESIGNATOR VALUE
DESCRIPTION
capacitor, X7R, 1.00uF, 25V, 0.1, 0603
capacitor, 47uF, 6.3V, 805
MANUFACTURER
Murata
TDK
PART NUMBER
GRM188R71E105KA12D
C2012X5R0J476M
C1608X7R1E104K
EMK316BJ226ML-T
EEV-FK1E680P
C1608X5R1A224K
2R5TPE330M9
PIMB104T-1R5MS-39
RK73H1J1002F
RK73H1JLTD20R0F
CRCW06034R99FNEA
RK73H1JLTD2003F
RK73H1JLTD8661F
RK73H1JLTD2801F
RK73H1JLTD2551F
SD02H0SK
3
1
2
1
1
1
1
1
3
1
1
1
1
1
1
1
1
C1, C21, C25
1.00uF
47uF
0.100uF
22.0uF
68uF
0.22uF
330uF
1.5uH
10.0K
20
C10
C12, C20
C2
capacitor, X7R, 0.100uF, 25V, 0.1, 603
capacitor, X5R, 22.0uF, 16V, 20%, 1206
capacitor, electrolytic, 68uF, 25V, 0.2, SMD
capacitor, X5R, 0.22uF, 10V, 0.1, 0603
capacitor, electrolytic, 330uF, 2.5V, 0.2, 7343
inductor, ferrite, 1.5uH, 16.0A, 3.8mOhm, SMT
resistor, thick film, 10.0K, 1/10W, 0.01, 0603
resistor, thick film, 20, 1/10W, 0.01, 603
resistor, thick film, 4.99, 1/10W, 0.01, 603
resistor, thick film, 200K, 1/10W, 0.01, 603
resistor, thick film, 8.66K, 1/10W, 0.01, 603
resistor, thick film, 2.80K, 1/10W, 0.01, 603
resistor, thick film, 2.55K, 1/10W, 0.01, 0603
switch, DIP, SPST, 2 position, SMT
TDK
Taiyo Yuden
Panasonic
TDK
Sanyo
Cyntec
KOA
KOA
Vishay/Dale
KOA
C3
C4
C9
L1
R1, R2, R5
R11
R12
R3
4.99
200K
R4
R7
R8
SW1
U1
8.66K
2.80K
2.55K
SPST
IR3865
KOA
KOA
KOA
C&K Components
IRF
4mm X 5mm QFN
IR3865MTRPBF
8/8/2012 Rev3.1
8
IR3865MPBF
TYPICAL OPERATING DATA
Tested with demoboard shown in Figure 7, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, TA = 25oC, no
airflow, unless otherwise specified
EN
EN
PGOOD
PGOOD
SS
SS
VOUT
VOUT
5V/div 5V/div 1V/div 500mV/div
5ms/div
5V/div 5V/div 1V/div 500mV/div
1ms/div
Figure 9: Shutdown
Figure 8: Startup
VOUT
VOUT
PHASE
PHASE
iL
iL
20mV/div 5V/div 5A/div
10µs/div
20mV/div 5V/div 10A/div
2µs/div
Figure 11: CCM (IOUT = 10A)
Figure 10: DCM (IOUT = 0.1A)
PGOOD
FB
PGOOD
VOUT
SS
VOUT
iL
IOUT
5V/div 1V/div 1V/div 10A/div
1ms/div
5V/div 1V/div 500mV/div 2A/div
50µs/div
Figure 12: Over Current Protection
(tested by shorting VOUT to PGND)
Figure 13: Over Voltage Protection
(tested by shorting FB to VOUT)
8/8/2012 Rev3.1
9
IR3865MPBF
TYPICAL OPERATING DATA
Tested with demoboard shown in Figure 7, VIN = 12V, VCC = 5V, VOUT = 1.05V, Fs = 300kHz, TA = 25oC, no
airflow, unless otherwise specified
VOUT
VOUT
PHASE
iL
PHASE
iL
50mV/div 5V/div 2A/div
50µs/div
20mV/div 5V/div 5A/div
50µs/div
Figure 15: Load Transient 6-10A
Figure 14: Load Transient 0-4A
FCCM
FCCM
PHASE
VOUT
PHASE
VOUT
iL
iL
5V/div 10V/div 500mV/div 5A/div
10µs/div
2V/div 10V/div 500mV/div 5A/div
5µs/div
Figure 17: FCCM/DCM Transition
Figure 16: DCM/FCCM Transition
Figure 18: Thermal Image at VIN = 12V, IOUT
=
Figure 19: Thermal Image at VIN = 16V, IOUT =
10A (IR3865: 81oC, Inductor: 52oC, PCB: 39oC)
10A (IR3865: 84oC, Inductor: 53oC, PCB: 39oC)
8/8/2012 Rev3.1
10
IR3865MPBF
CIRCUIT DESCRIPTION
PGOOD
PWM COMPARATOR
The PGOOD pin is open drain and it needs to be
externally pulled high. High state indicates that
output is in regulation. The PGOOD logic monitors
EN_DELAY, SS_DELAY, and under/over voltage
fault signals. PGOOD is released only when
EN_DELAY and SS_DELAY = HIGH and output
voltage is within the OV and UV thresholds.
The PWM comparator initiates a SET signal
(PWM pulse) when the FB pin falls below the
reference (VREF) or the soft start (SS) voltage.
ON-TIME GENERATOR
The PWM on-time duration is programmed with
an external resistor (RFF) from the input supply
(VIN) to the FF pin. The simplified equation for
RFF is shown in equation 1. The FF pin is held
to an internal reference after EN goes HIGH. A
copy of the current in RFF charges a timing
capacitor, which sets the on-time duration, as
shown in equation 2.
PRE-BIAS STARTUP
IR3865 is able to start up into pre-charged output,
which prevents oscillation and disturbances of the
output voltage.
With constant on-time control, the output voltage
is compared with the soft start voltage (SS) or
Vref, depending on which one is lower, and will
not start switching unless the output voltage drops
below the reference. This scheme prevents
discharge of a pre-biased output voltage.
V
OUT
R
FF
(1)
(2)
1V 20pF FSW
FF 1V 20pF
R
TON
V
IN
SHUTDOWN
CONTROL LOGIC
The IR3865 will shutdown if VCC is below its
UVLO limit. The IR3865 can be shutdown by
pulling the EN pin below its lower threshold.
Alternatively, the output can be shutdown by
pulling the soft start pin below 0.3V.
The control logic monitors input power sources,
sequences the converter through the soft-start
and protective modes, and initiates an internal
RUN signal when all conditions are met.
VCC and 3VCBP pins are continuously
monitored, and the IR3865 will be disabled if the
voltage of either pin drops below the falling
thresholds. EN_DELAY will become HIGH when
VCC and 3VCBP are in the normal operating
range and the EN pin = HIGH.
SOFT START
With EN = HIGH, an internal 10µA current
source charges the external capacitor (CSS) on
the SS pin to set the output voltage slew rate
during the soft start interval. The soft start time
(tSS) can be calculated from equation 3.
CSS 0.5V
10A
tSS
(3)
The feedback voltage tracks the SS pin until SS
reaches the 0.5V reference voltage (Vref), then
feedback is regulated to Vref. CSS will continue
to be charged, and when SS pin reaches VSS
(see Electrical Specification), SS_DELAY goes
HIGH. With EN_DELAY = LOW, the capacitor
voltage and SS pin is held to the FB pin voltage.
A normal startup sequence is shown in Figure
20.
Figure 20. Normal Startup
8/8/2012 Rev3.1
11
IR3865MPBF
CIRCUIT DESCRIPTION
UNDER/OVER VOLTAGE MONITOR
OVER CURRENT MONITOR
The IR3865 monitors the voltage at the FB node
through a 350ns filter. If the FB voltage is below
the under voltage threshold, UV# is set to LOW
holding PGOOD to be LOW. If the FB voltage is
above the over voltage threshold, OV# is set to
LOW, the shutdown signal (SD) is set to HIGH,
MOSFET gates are turned off, and PGOOD
signal is pulled low. Toggling VCC or EN will
allow the next start up. Figure 21 and 22 show
PGOOD status change when UV/OV is
detected. The over voltage and under voltage
thresholds can be found in the Electrical
Specification section.
The over current circuitry monitors the output
current during each switching cycle. The voltage
across the lower MOSFET, VPHASE, is
monitored for over current and zero crossing. The
OCP circuit evaluates VPHASE for an over
current condition typically 270ns after the lower
MOSFET is gated on. This delay functions to filter
out switching noise. The minimum lower gate
interval allows time to sample VPHASE.
The over current trip point is programmed with a
resistor from the ISET pin to PHASE pin, as
shown in equation 4. When over current is
detected, the MOSFET gates are tri-state and SS
voltage is pulled to 0V. This initiates a new soft
start cycle. If there is a total of four OC events, the
IR3865 will disable switching. Toggling VCC or
EN will allow the next start up.
R
DSON OC
I
RSET
(4)
19 A
* typical filter delay
Figure 21. Under/Over Voltage Monitor
Figure 23. Over Current Protection
UNDER VOLTAGE LOCK-OUT
The IR3865 has VCC and EN under voltage lock-
out (UVLO) protection. When either VCC or EN is
below their UVLO threshold, IR3865 is disabled.
IR3865 will restart when both VCC and EN are
above their UVLO thresholds.
* typical filter delay
Figure 22. Over Voltage Protection
8/8/2012 Rev3.1
12
IR3865MPBF
CIRCUIT DESCRIPTION
OVER TEMPERATURE PROTECTION
When the IR3863 exceeds its over temperature
threshold, the MOSFET gates are tri-state and
PGOOD is pulled low. Switching resumes once
temperature drops below the over temperature
hysteresis level.
The upper MOSFET is gated on after the
adaptive delay for PWM = HIGH and the lower
MOSFET is gated on after the adaptive delay
for PWM = LOW.
When FCCM = LOW, the lower MOSFET is
driven ‘off’ when the ZCROSS signal indicates
that the inductor current is about to reverse
direction. The ZCROSS comparator monitors
the PHASE voltage to determine when to turn
off the lower MOSFET. The lower MOSFET
stays ‘off’ until the next PWM falling edge.
When the lower peak of the inductor current is
above zero, IR3863 operates in continuous
conduction mode. The continuous conduction
mode can also be selected for all load current
levels by pulling FCCM to HIGH.
Whenever the upper MOSFET is turned ‘off’, it
stays ‘off’ for the Min Off Time denoted in the
Electrical Specifications. This minimum
duration allows time to recharge the bootstrap
capacitor and allows the over current monitor
to sample the PHASE voltage.
GATE DRIVE LOGIC
The gate drive logic features adaptive dead
time, diode emulation, and a minimum lower
gate interval.
An adaptive dead time prevents the
simultaneous conduction of the upper and lower
MOSFETs. The lower gate voltage must be
below approximately 1V after PWM goes HIGH
before the upper MOSFET can be gated on.
Also, the differential voltage between the upper
gate and PHASE must be below approximately
1V after PWM goes LOW before the lower
MOSFET can be gated on.
COMPONENT SELECTION
Selection of components for the converter is an
iterative process which involves meeting the
One can use equation 5 to find the required
inductance. ΔI is defined as shown in Figure 24.
The main advantage of small inductance is
increased inductor current slew rate during a
load transient, which leads to a smaller output
capacitance requirement as discussed in the
Output Capacitor Selection section. The draw
back of using smaller inductances is increased
switching power loss in the upper MOSFET,
which reduces the system efficiency and
increases the thermal dissipation.
specifications
and
tradeoffs
between
performance and cost. The following sections
will guide one through the process.
Inductor Selection
Inductor selection involves meeting the steady
state output ripple requirement, minimizing the
switching loss of the upper MOSFET, meeting
transient
response
specifications
and
minimizing the output capacitance. The output
voltage includes a DC voltage and a small AC
ripple component due to the low pass filter
which has incomplete attenuation of the
switching harmonics. Neglecting the inductance
in series with the output capacitor, the
magnitude of the AC voltage ripple is
determined by the total inductor ripple current
flowing through the total equivalent series
resistance (ESR) of the output capacitor bank.
IOUT
Input Current
ΔI
TS
Figure 24. Typical Input Current Waveform
TON
V
IN
VOUT
(5)
ΔI
2L
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IR3865MPBF
COMPONENT SELECTION
Input Capacitor Selection
Output Capacitor Selection
Selection of the output capacitor requires
meeting voltage overshoot requirements during
load removal, and meeting steady state output
The main function of the input capacitor bank is
to provide the input ripple current and fast slew
rate current during the load current step up. The
input capacitor bank must have adequate ripple
current carrying capability to handle the total
RMS current. Figure 24 shows a typical input
current. Equation 6 shows the RMS input
current. The RMS input current contains the DC
load current and the inductor ripple current. As
shown in equation 5, the inductor ripple current
is unrelated to the load current. The maximum
RMS input current occurs at the maximum
output current. The maximum power dissipation
in the input capacitor equals the square of the
maximum RMS input current times the input
capacitor’s total ESR.
ripple voltage requirements.
The output
capacitor is the most expensive converter
component and increases the overall system
cost. The output capacitor decoupling in the
converter typically includes the low frequency
capacitor, such as Specialty Polymer Aluminum,
and mid frequency ceramic capacitors.
The first purpose of output capacitors is to
provide current when the load demand exceeds
the inductor current, as shown in Figure 25.
Equation 7 shows the charge requirement for a
certain load step. The advantage provided by
the IR3865 at a load step is the reduced delay
compared to a fixed frequency control method.
If the load increases right after the PWM signal
goes low, the longest delay will be equal to the
minimum lower gate on-time as shown in the
Electrical Specification table. The IR3865 also
reduces the inductor current slew time, the time
it takes for the inductor current to reach equality
with the output current, by increasing the
switching frequency up to 1/(TON + Min Off
Time). This results in reduced recovery time.
Ts
1
IIN_RMS
f 2
t
dt
Ts
0
1
ΔI
2
IOUT T Fs 1
(6)
ON
3 IOUT
The voltage rating of the input capacitor needs
to be greater than the maximum input voltage
because of high frequency ringing at the phase
node. The typical percentage is 25%.
Load
Current
ISTEP
Output
Charge
Inductor
Slew
Rate
t
Δt
Figure 25. Charge Requirement during Load Step
Q CV 0.5ISTEP t (7a)
2
1
1
2
LISTEP
COUT
(7b)
V
DROP
VIN
V
OUT
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IR3865MPBF
COMPONENT SELECTION
The output voltage drop, VDROP, initially depends
on the characteristic of the output capacitor.
VDROP is the sum of the equivalent series
inductance (ESL) of the output capacitor times
the rate of change of the output current and the
ESR times the change of the output current.
Boot Capacitor Selection
The boot capacitor starts the cycle fully charged
to a voltage of VB(0). Cg equals 0.6nF in
IR3865. Choose a sufficiently small ΔV such that
VB(0)-ΔV exceeds the maximum gate threshold
voltage to turn on the upper MOSFET.
V (0)
B
CBOOT C
1 (9)
g
VESR is usually much greater than VESL. The
IR3865 requires a total ESR such that the ripple
voltage at the FB pin is greater than 7mV. The
second purpose of the output capacitor is to
minimize the overshoot of the output voltage
when the load decreases as shown in Figure
26. By using the law of energy before and after
the load removal, equation 8 shows the output
capacitance requirement for a load step down.
ΔV
Choose a boot capacitor value larger than the
calculated CBOOT in equation 9. Equation 9 is
based on charge balance at CCM operation.
Usually the boot capacitor will be discharged to a
much lower voltage when the circuit is operating
in DCM mode at light load, due to much longer
lower MOSFET off time and the bias current
drawn by the IC. Boot capacitance needs to be
increased if insufficient turn-on of the upper
MOSFET is observed at light load, typically
larger than 0.1µF is needed. The voltage rating
of this part needs to be larger than VB(0) plus
the desired derating voltage. Its ESR and ESL
needs to be low in order to allow it to deliver the
large current and di/dt’s which drive MOSFETs
most efficiently. In support of these requirements
a ceramic capacitor should be chosen.
2
LISTEP
COUT
(8)
2
V
OS2 VOUT
VOS
VOUT
VL
VDROP
VESR
ISTEP
IOUT
Figure 26. Typical Output Voltage Response
Waveform
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IR3865MPBF
DESIGN EXAMPLE
1.5V
16V 2.2H 300kHz
16V -1.5V
2.1A
2ΔI
Design Criteria:
Choose an input capacitor:
Input Voltage, VIN = 7V to 16V
Output Voltage, VOUT = 1.5V
Switching Frequency, Fs = 300kHz
Inductor Ripple Current, 2ΔI = 2A
Maximum Output Current, IOUT = 10A
Over Current Trip, IOC = 15A
Overshoot Allowance for 5A Load Step Down,
VOS = VOUT + 75mV
Undershoot Allowance for 5A Load Step Up,
VDROP = 75mV
2
1.5V
1 2.1A/ 2
I
IN_RMS 10A
1
3.1A
16V
3
10A
A
Panasonic
10µF
(ECJ3YB1E106M)
accommodates 6 Arms of ripple current at
300kHz. Due to the chemistry of multilayer
ceramic capacitors, the capacitance varies over
temperature and operating voltage, both AC and
DC. One 10µF capacitor is recommended. In a
practical solution, one 1µF capacitor is required
along with 10µF. The purpose of the 1µF
capacitor is to suppress the switching noise and
deliver high frequency current.
Find RFF
:
1.5V
RFF
250 k
1V 20pF 300kHz
Pick a standard value 255 kΩ, 1% resistor.
Choose an output capacitor:
Find RSET
:
10.7m
15A
R
SET
8.4k
To meet the undershoot and overshoot
specification, equation 7b and 8 will be used to
calculate the minimum output capacitance. As a
result, 240µF will be needed for 5A load
removal. To meet the stability requirement,
choose an output capacitors with ESR larger
than 10mΩ. Combine those two requirements,
one can choose a set of output capacitors from
manufactures such as SP-Cap (Specialty
Polymer Capacitor) from Panasonic or POSCAP
from Sanyo. A 330µF (EEFUE0E331XR) from
Panasonic with 10mΩ ESR will meet both
requirements.
19A
Pick a 8.45kΩ, 1% standard resistor.
Find a resistive voltage divider for VOUT = 1.5V:
R
2
V
FB
VOUT 0.5V
1
R2
R
R2 = 1.40kΩ, R1 = 2.80 kΩ, both 1% standard
resistors.
Choose the soft start capacitor:
Once the soft start time has chosen, such as
1000us to reach to the reference voltage, a
22nF for CSS is used to meet 1000µs.
If an all ceramic output capacitor solution is
desired, the external slope injection circuit
composed of R6, C13, and C14 is required as
explained in the Stability Consideration Section.
In this design example, we can choose C14 =
1nF and C13 = 100nF. To calculate the value of
R6 with PIMB104T-2R2MS-39 as our inductor:
Choose an inductor to meet the design
specification:
V
OUT
V
IN
V
OUT
L
V
IN 2ΔIF
s
1.5V
16V 2A300kHz
16V -1.5V
L
R6
DCRC13
2.3H
2.2H
Choose an inductor with the lowest DCR and
AC power loss as possible to increase the
overall system efficiency. For instance, choose
6.0m100nF
3.67k
a
PIMB104T-2R2MS-39 manufactured by
Pick a standard value for R6 = 3.65kΩ.
CYNTEC. The inductance of this part is 2.2µH
and has 6.0mΩ DCR. Ripple current needs to
be recalculated using the chosen inductor.
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IR3865MPBF
STABILITY CONSIDERATIONS
Constant-on-time control is a fast , ripple based
control scheme. Unstable operation can occur
if certain conditions are not met. The system
instability is usually caused by:
• System with all ceramic output capacitors:
For applications with all ceramic output
capacitors, the ESR is usually too small to
meet the stability criteria. In these
applications, external slope compensation is
necessary to make the loop stable. The ramp
injection circuit, composed of R6, C13, and
C14, shown in Figure 7 is required. The
inductor current ripple sensed by R6 and C13
is AC coupled to the FB pin through C14. C14
is usually chosen between 1 to 10nF, and
C13 between 10 to 100nF. R6 should then be
chosen such that L/DCR = C13*R6.
• Switching noise coupled to FB input:
This causes the PWM comparator to trigger
prematurely after the 400ns minimum on-time
for lower MOSFET. It will result in double or
multiple pulses every switching cycle instead
of the expected single pulse. Double pulsing
can causes higher output voltage ripple, but in
most application it will not affect operation.
This can usually be prevented by careful
layout of the ground plane and the FB sensing
trace.
• System with electrolytic output capacitors:
The electrolytic capacitors usually have higher
ESL than POSCAPs and ceramic capacitors.
The effect of high ESL is undesirable spike on
the FB node causing false trigger of a new
switching cycle. The ESR of electrolytic
capacitors also comes in a wide range, such
that in some cases we need to filter out the
spikes caused by its high ESL while providing
injected ripple to compensate for low ESR.
The circuit composed of R13, C24, and C14
shown in Figure 7 acts as a filter and a ramp
generator. As an example, if two Nichicon
PW-series, 1000uF, 16V through hole
electrolytic capacitor are used for 12Vin,
5Vout, and 300kHz switching; the suggested
compensation values are: R13 = 20Ω, C24 =
1uF, and C14 = 1000pF. Equations for
determining these values have not been
established. If electrolytic or other high ESL
capacitors are required, IR's application team
will gladly assist you to determine an optimal
compensation scheme.
• Steady state ripple on FB pin being too small:
The PWM comparator in IR3865 requires
minimum 7mVp-p ripple voltage to operate
stably. Not enough ripple will result in similar
double pulsing issue described above. Solving
this may require using output capacitors with
higher ESR.
• ESR loop instability:
The stability criteria of constant on-time is:
ESR*Cout>Ton/2. If ESR is too small that this
criteria is violated then sub-harmonic
oscillation will occur. This is similar to the
instability problem of peak-current-mode
control with D>0.5. Increasing ESR is the
most effective way to stabilize the system, but
the tradeoff is the larger output voltage ripple.
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IR3865MPBF
LAYOUT RECOMMENDATIONS
Bypass Capacitor:
As VCC bypass capacitor, a 1µF high quality
ceramic capacitor should be placed on the same
side as the IR3865 and connected to VCC and
PGND pins directly. A 1µF ceramic capacitor
should be connected from 3VCBP to AGND to
avoid noise coupling into controller circuits. For
single-ground designs, a resistor (R12) in the
range of 5 to 10Ω in series with the 1µF
capacitor as shown in Figure 7 is recommended.
Q1
IR3865
Q2
Boot Circuit:
Figure 27. Current Path of Power Stage
CBOOT should be placed near the BOOT and
PHASE pins to reduce the impedance when the
upper MOSFET turns on.
Power Stage:
Figure 27 shows the current paths and their
directions for the on and off periods. The on time
path has low average DC current and high AC
current. Therefore, it is recommended to place
the input ceramic capacitor, upper, and lower
MOSFET in a tight loop as shown in Figure 27.
The purpose of the tight loop from the input
ceramic capacitor is to suppress the high
frequency (10MHz range) switching noise and
reduce Electromagnetic Interference (EMI). If
this path has high inductance, the circuit will
cause voltage spikes and ringing, and increase
the switching loss. The off time path has low AC
and high average DC current. Therefore, it
should be laid out with a tight loop and wide
trace at both ends of the inductor. Lowering the
loop resistance reduces the power loss. The
typical resistance value of 1-ounce copper
thickness is 0.5mΩ per square inch.
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IR3865MPBF
PCB Metal and Components Placement
Lead lands (the 13 IC pins) width should be equal to nominal part lead width. The minimum lead to
lead spacing should be ≥ 0.2mm to minimize shorting.
Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The
outboard extension ensures a large toe fillet that can be easily inspected.
Pad lands (the 4 big pads) length and width should be equal to maximum part pad length and width.
However, the minimum metal to metal spacing should be no less than 0.17mm for 2 oz. Copper, or
no less than 0.1mm for 1 oz. Copper, or no less than 0.23mm for 3 oz. Copper.
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IR3865MPBF
Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist
should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads.
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist
onto the copper of 0.05mm to accommodate solder resist misalignment.
Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to the
high aspect ratio of the solder resist strip separating the lead lands from the pad land.
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IR3865MPBF
Stencil Design
The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads.
Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much
solder is deposited on the center pad the part will float and the lead lands will open.
The maximum length and width of the land pad stencil aperture should be equal to the solder resist
opening minus an annular 0.2mm pull back in order to decrease the risk of shorting the center land
to the lead lands when the part is pushed into the solder paste.
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IR3865MPBF
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been designed and qualified for the Industrial Market (Note 2)
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 03/12
8/8/2012 Rev3.1
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