IR3876TR1PBF [INFINEON]
12A HIGHLY INTEGRATED WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR; 12A高集成度的宽电压输入，同步降压稳压器
| 型号： | IR3876TR1PBF |
| 厂家： | 
Infineon |
| 描述： | 12A HIGHLY INTEGRATED WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR |
| 文件： | 总20页 (文件大小：1024K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IR3876MBF
TM
SupIRBuck
12A HIGHLY INTEGRATED
WIDE-INPUT VOLTAGE, SYNCHRONOUS BUCK REGULATOR
Features
Description
. Input Voltage Range: 3V to 21V
. Output Voltage Range: 0.5V to 12V
. Continuous 12A Load Capability
. Constant On-Time control
. Excellent Efficiency at very low output current levels
. Compensation Loop not Required
. Programmable switching frequency, soft start, and
over current protection
. Power Good Output
. Precision Voltage Reference (0.5V, +/-1%)
. Pre-bias Start Up
. Under/Over Voltage Fault Protection
. Ultra small, low profile 5mm x 6mm QFN Package
The IR3876 SupIRBuckTM is an easy-to-use,
fully integrated and highly efficient DC/DC
voltage regulator. The onboard constant on time
hysteretic controller and MOSFETs make
IR3876 a space-efficient solution that delivers up
to 12A of precisely controlled output voltage in
60°C ambient temperature applications without
airflow.
Programmable switching frequency, soft start,
and over current protection allows for a very
flexible solution suitable for many different
applications and an ideal choice for battery
powered applications.
Applications
Additional features include pre-bias startup, very
precise 0.5V reference, over/under voltage shut
down, power good output, and enable input with
voltage monitoring capability.
. Notebook and desktop computers
. Game consoles
. Consumer electronics – STB, LCD, TV, printers
. General purpose POL DC-DC converters
1
IR3876MBF
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND unless otherwise specified)
•
•
•
•
•
•
•
•
•
•
•
•
VIN. FF ………………………………………………. -0.3V to 25V
VCC, PGood, EN ………………….…....……..….… -0.3V to 8.0V
Boot ……………………………………..………….…. -0.3V to 33V
PHASE ……………………………………………...... -0.3V to 25V(DC), -5V(100ns)
Boot to PHASE…..…………………………….…..….. -0.3V to 8V
ISET
…………………………………………..……. -0.3V to 30V
PGND to GND ……………...……………………….... -0.3V to +0.3V
All other pins ……………...……………………….….. -0.3V to 3.9V
Storage Temperature Range ................................... -65°C To 150°C
Junction Temperature Range ................................... -10°C To 150°C
ESD Classification …………………………….……… JEDEC Class 1C
Moisture sensitivity level ..……………...…………….. JEDEC Level 3@260 °C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other
conditions beyond those indicated in the operational sections of the specifications are not implied.
PACKAGE INFORMATION
5mm x 6mm POWER QFN
θJA = 35oC / W
θJ-PCB = 2oC / W
ORDERING INFORMATIO
PKG DESIG
PACKAGE
PIN COUNT
PARTS PER
REEL
DESCRIPTION
M
M
IR3876MTRPbF
IR3876TR1PbF
17
17
4000
750
2
IR3876MBF
Block Diagram
3
IR3876MBF
Pin Description
NAME
NUMBER I/O
LEVEL
DESCRIPTION
NC
1
2
-----
No connection
ISET
PGOOD
GND
FB
Connecting resistor to PHASE pin sets over current trip point
Power good – pull up to 3.3V
3
5V
4,17
5
Reference
3.3V
Bias return and signal reference
Inverting input to PWM comparator, OVP / PGood sense
Set soft start slew-rate with a capacitor to GND
No connection
SS
6
3.3V
NC
7
-----
3VCBP
NC
8
3.3V
LDO output. A minimum of 1.0 µF ceramic capacitor is required
No connection
9
-----
VCC
PGND
PHASE
VIN
10
11
12
13
14
15
16
5V
Gate drive supply
Reference
VIN
Power return
Phase node (or switching node) of MOSFET half bridge
Input voltage for the system.
VIN
BOOT
FF
VIN +VCC Bootstrapped gate drive supply – connect a capacitor to PHASE
VIN
5V
Input voltage feed forward – sets on-time with a resistor to VIN
Enable
EN
4
IR3876MBF
Recommended Operating Conditions
Symbol
VIN
Definition
Input Voltage
Min
3
Max
21*
Unit
VCC
VOUT
IOUT
Fs
Supply Voltage
4.5
7.5
V
Output Voltage
0.5
0
12
12
Output Current
A
Switching Frequency
Junction Temperature
N/A
0
1000
125
kHz
oC
TJ
* Note: PHASE pin must not exceed 25V.
Electrical Specifications
Unless otherwise specified, these specification apply over VIN = 12V, VCC = 5V, 0oC ≤ TJ ≤ 125oC.
PARAMETER
BIAS SUPPLIES
NOTE
TEST CONDITION
MIN TYP MAX UNIT
VCC Turn-on Threshold
VCC Turn-off Threshold
VCC Threshold Hysteresis
VCC Operating Current
3.9
3.6
4.2
3.9
150
9.2
4.5
4.2
V
V
mV
mA
R
FF = 200K,
EN = HIGH, Fs = 300kHz
EN = LOW
VCC Shutdown Current
FF Shutdown Current
VIN Shutdown Current
INTERNAL LDO OUTPUT
LDO Output Voltage Range
Output Current
35
2
50
µA
µA
µA
EN = LOW
EN = LOW
1
C
LDO = 1µF
3.1
3.3
3.5
8
V
mA
CONTROL LOOP
Reference Accuracy, VREF
On-Time Accuracy
VREF
0.495 0.5
0.505
320
V
ns
RFF = 180K, TJ = 65oC
280
300
400
10
Min Off Time
1
1
ns
Soft-Start Current
EN = HIGH
8
12
0
µA
mV
Zero Current Threshold
FAULT PROTECTION
ISET Pin Output Current
Under Voltage Threshold
Under Voltage Hysteresis
Over Voltage Threshold
Over Voltage Hysteresis
Measure at VPHASE
-5
-2.4
18
20
0.4
10
22
µA
V
Falling VFB & Monitor PGOOD
Rising VFB
0.37
0.43
1
1
mV
V
Rising VFB & Monitor PGOOD
Falling VFB
0.58 0.62
0.66
10
1
mV
V
PGOOD Delay Threshold
(VSS)
5
IR3876MBF
Electrical Specifications (continued)
Unless otherwise specified, these specification apply over VIN = 12V, VCC = 5V, 0oC ≤ TJ ≤ 125oC.
PARAMETER
GATE DRIVE
Dead Time
NOTE
TEST CONDITION
MIN TYP MAX UNIT
1
Monitor body diode conduction
on PHASE pin
5
30
ns
BOOTSTRAP PFET
Forward Voltage
I(BOOT) = 10mA
100
7
200
12
300
16
mV
UPPER MOSFET
Static Drain-to-Source On-
Resistance
VCC = 5V, ID = 12A, TJ = 25oC
mΩ
LOWER MOSFET
Static Drain-to-Source On-
Resistance
VCC = 5V, ID = 12A, TJ = 25oC
4
5.3
7
mΩ
LOGIC INPUT AND OUTPUT
EN High Logic Level
2
-
-
-
V
V
EN Low Logic Level
-
0.6
EN Input Current
EN = 3.3V
11
25
µA
Ω
PGOOD Pull Down
Resistance
50
Note1: Guaranteed by design, not tested in production
6
IR3876MBF
TYPICAL OPERATING DATA
Tested with demoboard shown in Figure 7, VIN = 12.6V, VCC = 5V, Vout = 1.05V, Fs = 300kHz, TA = 25oC, no airflow,
unless otherwise specified
95%
85%
75%
65%
55%
45%
35%
100%
90%
80%
70%
60%
50%
40%
1.05VOUT; L = 1.2uH, 2.9mΩ
1.5VOUT; L = 1.2uH, 2.9mΩ
3.3VOUT; L = 2.2uH, 4.2mΩ
16VIN
12.6VIN
7VIN
0.01
0.1
1
10
100
0.01
0.1
1
10
100
Output Current (A)
Output Current (A)
Figure 1. Efficiency vs. Output Current for
Figure 2. Efficiency vs. Output Current for
VIN = 12.6V
VOUT = 1.05V, L = 1.2µH (2.9mΩ)
1200
1000
800
600
400
200
0
350
300
250
200
150
100
50
5.0 Vout
4.0
3.0
2.0
1.0
4.5
3.5
2.5
1.5
0.5
0
0
2
4
6
8
10
12
200
400
600
Frequency (kHz)
800
1000
Output Current (A)
Figure 3. Switching Frequency vs. Output
Current
Figure 4. Frequency vs. RFF
1.058
1.058
VOUT @ 12.6VIN
1.057
1.056
1.055
1.054
1.057
1.056
1.055
1.054
VOUT @ 16VIN
VOUT @ 7VIN
0
2
4
6
8
10
12
6
7
8
9
10 11 12 13 14 15 16 17
Input Voltage (V)
Output Current (A)
Figure 5. Output Voltage Regulation vs.
Output Current
Figure 6. Output Voltage Regulation vs.
Input Voltage at IOUT = 12A
7
IR3876MBF
TYPICAL APPLICATION CIRCUIT
Demoboard Schematic: VOUT = 1.05V, Fs = 300kHz
Figure 7. Typical Application Circuit for VOUT = 1.05V, Fs = 300kHz
Bill of Materials
8
IR3876MBF
TYPICAL OPERATING DATA
Tested with demoboard shown in Figure 7, VIN = 12.6V, VCC = 5V, Vout = 1.05V, Fs = 300kHz, TA = 25oC, no airflow,
unless otherwise specified
EN
EN
PGOOD
PGOOD
SS
SS
VOUT
VOUT
5V/div
5V/div 1V/div 500mV/div
5ms/div
5V/div 5V/div 1V/div 500mV/div
200µs/div
Figure 9: Shutdown
Figure 8: Startup
VOUT
VOUT
PHASE
PHASE
iL
iL
20mV/div
20mV/div
5V/div 5A/div
5V/div 2A/div
10µs/div
2µs/div
Figure 11: CCM (IOUT = 12A)
Figure 10: DCM (IOUT = 0.1A)
PGOOD
FB
PGOOD
SS
VOUT
iL
VOUT
IOUT
5V/div 1V/div 1V/div 10A/div
2ms/div
5V/div 1V/div 500mV/div 2A/div
50µs/div
Figure 12: Over Current Protection
(tested by shorting VOUT to PGND)
Figure 13: Over Voltage Protection
(tested by shorting FB to VOUT)
9
IR3876MBF
TYPICAL OPERATING DATA
Tested with demoboard shown in Figure 7, VIN = 12.6V, VCC = 5V, Vout = 1.05V, Fs = 300kHz, TA = 25oC, no airflow,
unless otherwise specified
VOUT
VOUT
PHASE
PHASE
iL
iL
50mV/div
50mV/div
10V/div 5A/div
20µs/div
10V/div 5A/div
20µs/div
Figure 15: Load Transient 4-12A
Figure 14: Load Transient 0-8A
Figure 16: Thermal Image at IOUT = 12A
(IR3876: 81oC, Inductor: 58oC, PCB: 54oC)
10
IR3876MBF
CIRCUIT DESCRIPTION
PWM COMPARATOR
GATE DRIVE LOGIC
The PWM comparator initiates a SET signal
(PWM pulse) when the FB pin falls below the
reference (VREF) or the soft start (SS) voltage.
The gate drive logic features adaptive dead
time, diode emulation, and a minimum lower
gate interval.
An adaptive dead time prevents the
simultaneous conduction of the upper and lower
MOSFETs. The lower gate voltage (LGATE)
must be below approximately 1V after PWM
goes HIGH before the upper MOSFET can be
gated on. Also, the upper gate voltage
(UGATE), the difference voltage between
UGATE and PHASE, must be below
approximately 1V after PWM goes LOW before
the lower MOSFET can be gated on.
ON-TIME GENERATOR
The PWM on-time duration is programmed with
an external resistor (RFF) from the input supply
(VIN) to the FF pin. The simplified equation for
RFF is shown in equation 1. The FF pin is held to
an internal reference after EN goes HIGH. A copy
of the current in RFF charges a timing capacitor,
which sets the on-time duration, as shown in
equation 2.
V
OUT
The control MOSFET is gated on after the
adaptive delay for PWM = HIGH and the
synchronous MOSFET is gated on after the
adaptive delay for PWM = LOW. The lower
MOSFET is driven ‘off’ when the signal
ZCROSS indicates that the inductor current has
reversed as detected by the PHASE voltage
crossing the zero current threshold. The
synchronous MOSFET stays ‘off’ until the next
PWM falling edge. When the lower peak of
inductor current is above zero, a forced
continuous current condition is selected. The
control MOSFET is gated on after the adaptive
delay for PWM = HIGH, and the synchronous
MOSFET is gated on after the adaptive delay for
PWM = LOW.
R
FF
(1)
1V 20pF FSW
FF 1V 20pF
R
T
ON
(2)
V
IN
SOFT START
An internal 10µA current source charges the
external capacitor on the SS pin to set the output
voltage slew rate during the soft start interval. The
output voltage reaches regulation when the FB pin
is above the under voltage threshold and the UV#
= HIGH. Once the voltage on the SS pin is above
the PGOOD delay threshold, the combination of
the SSDelay and UV# signals release the
PGOOD pin. With EN = LOW, the capacitor
voltage and SS pin is held to the FB pin voltage.
The synchronous MOSFET gate is driven on for
a minimum duration. This minimum duration
allows time to recharge the bootstrap capacitor
and allows the current monitor to sample the
PHASE voltage.
CONTROL LOGIC
The control logic monitors input power sources,
sequences the converter through the soft-start
and protective modes, and indicates output
voltage status on the PGOOD pin. VCC and
3VCBP pins are continuously monitored, and the
IR3876 will be disabled if the voltage of either pin
drops below the falling thresholds.
The IR3876 will initiate a soft start when VCC is in
the normal range and the EN pin = HIGH. In the
event of a sustained overload, a counter keeps
track of four soft-start cycles and then disables the
IR3876. The overload counter is only reset by EN
or UVLO.
11
IR3876MBF
CIRCUIT DESCRIPTION
OVER CURRENT MONITOR
STABILITY CONSIDERATIONS
The over current circuitry monitors the output
current during each switching cycle. The voltage
across the synchronous MOSFET, VPHASE, is
monitored for over current and zero crossing. The
minimum LGATE interval allows time to sample
VPHASE.
The over current trip point is programmed with a
resistor from the ISET pin to PHASE pin, as
shown in equation 3, where Tj is the junction
temperature of Q2 at operation conditions, and 0.4
is the temperature coefficient (~4000 ppm/C) of
Q2 Rdson. When over current is detected, the
output gates are tri-state and SS voltage is pulled
to 0V. This initiates a new soft start cycle. If there
was a total of three OC events, the IR3876 will
disable switching. Toggling VCC or EN will allow
the next start up.
Constant-on-time control is a fast , ripple based
control scheme. Unstable operation can occur
if certain conditions are not met. The system
instability is usually caused by:
• Switching noise coupled to FB input. This
causes the PWM comparator to trigger
prematurely after the 400ns minimum Q2 on-
time. It will result in double or multiple pulses
every switching cycle instead of the expected
single pulse. Double pulsing can causes
higher output voltage ripple, but in most
application it will not affect operation. This can
usually be prevented by careful layout of the
ground plane and the FB sensing trace.
• Steady state ripple on FB pin being too small.
The PWM comparator in IR3876 requires
minimum 7mVp-p ripple voltage to operate
stably. Not enough ripple will result in similar
double pulsing issue described above. Solving
this may require using output capacitors with
higher ESR. Another way to solve this is to
add a ~10pF ceramic capacitor from Vout to
FB to couple more Vout ripple to the FB pin.
Tj 25
R
DSON OC
I
R
SET
(1
0.4) (3)
20 A
100
OVER VOLTAGE PROTECTION
The IR3876 monitors the voltage at the FB node.
If the FB voltage is above the over voltage
threshold, the gates are turned off and the
PGOOD signal is pulled low. Toggling VCC will
allow the next start up.
• ESR loop instability. The stability criteria of
constant on-time is: ESR*Cout>Ton/2. If ESR
is too small that this criteria is violated then
sub-harmonic oscillation will occur. This is
similar to the instability problem of peak-
current-mode control with D>0.5. Increasing
ESR is the most effective way to stabilize the
system, but the price paid is the larger output
voltage ripple.
• For applications with all ceramic output
capacitors, the ESR is usually too small to
meet the stability criteria. In these
applications, external slope compensation is
necessary to make the loop stable. The ramp
injection circuit, composed of R6, C13, and
C14, shown in Figure 7 is required. The
inductor current ripple sensed by R6 and C13
is AC coupled to the FB pin through C14. The
injected ramp slope can be adjusted by
changing the RC time constant of R6 and
C13, which is similar to the circuit used for
DCR current sensing. C14 is typically chosen
by C14(R7//R8)=Ton.
12
IR3876MBF
CIRCUIT DESCRIPTION
Input Capacitor Selection
COMPONENT SELECTION
Selection of components for the converter is an
iterative process which involves meeting the
The main function of the input capacitor bank is
to provide the input ripple current and fast slew
rate current during the load current step up. The
input capacitor bank must have adequate ripple
current carrying capability to handle the total
RMS current. Figure 17 shows a typical input
current. Equation 5 shows the RMS input
current. The RMS input current contains the DC
load current and the inductor ripple current. As
shown in equation 4, the inductor ripple current
is unrelated to the load current. The maximum
RMS input current occurs at the maximum
output current. The maximum power dissipation
in the input capacitor equals the square of the
maximum RMS input current times the input
capacitor’s total ESR.
specifications
and
trade-offs
between
performance and cost. The following sections will
guide one through the process.
Inductor Selection
Inductor selection involves meeting the steady
state output ripple requirement, minimizing the
switching loss of the upper MOSFET, meeting
transient response specifications and minimizing
the output capacitance. The output voltage
includes a DC voltage and a small AC ripple
component due to the low pass filter which has
incomplete
attenuation
of
the
switching
harmonics. Neglecting the inductance in series
with the output capacitor, the magnitude of the AC
voltage ripple is determined by the total inductor
ripple current flowing through the total equivalent
series resistance (ESR) of the output capacitor
bank.
T
ON
V
IN
VOUT
(4)
ΔI
2L
Figure 17. TypicaInput Current Waveform.
One can use equation 4 to find the required
inductance. ΔI is defined as shown in Figure 17.
The main advantage of small inductance is
increased inductor current slew rate during a load
transient, which leads to a smaller output
capacitance requirement as discussed in the
Output Capacitor Selection section. The draw
back of using smaller inductances is increased
switching power loss in upper MOSFET, which
reduces the system efficiency and increases the
thermal dissipation.
Ts
1
IIN_RMS
f 2
t
dt
Ts
0
1
ΔI
2
IOUT Ton Fs 1
(5)
3 IOUT
The voltage rating of the input capacitor needs
to be greater than the maximum input voltage
because of high frequency ringing at the phase
node. The typical percentage is 25%.
13
IR3876MBF
Output Capacitor Selection
Selection of the output capacitor requires meeting
voltage overshoot requirements during load
removal, and meeting steady state output ripple
voltage requirements. The output capacitor is the
most expensive converter component and
increases the overall system cost. The output
capacitor decoupling in the converter typically
includes the low frequency capacitor, such as
Specialty Polymer Aluminum, and mid frequency
ceramic capacitors.
VESR is usually much greater than VESL. The
IR3876 requires a total ESR such that the ripple
voltage at the FB pin is greater than 7mV.
The second purpose of the output capacitor is to
minimize the overshoot of the output voltage
when the load decreases as shown in Figure
19. By using the law of energy before and after
the load removal, equation 7 shows the output
capacitance requirement for a load step.
2
L ISTEP
C
OUT
(7)
2
2
The first purpose of output capacitors is to provide
current when the load demand exceeds the
inductor current, as shown in Figure 18. Equation
6 shows the charge requirement for a certain load.
The advantage provided by the IR3876 at a load
step is to reduce the delay compared to a fixed
frequency control method (in microseconds or (1-
D)*Ts). If the load increases right after the PWM
signal goes low, the longest delay will be equal to
the minimum lower gate on as shown in the
Electrical Specification table. The IR3876 also
reduces the inductor current slew time, the time it
takes for the inductor current to reach equality
with the output current, by increasing the
switching frequency up to 2.5MHz. The result
reduces the recovery time.
V
OS VOUT
Figure 19. Typical Output Voltage Response
Waveform.
Boot Capacitor Selection
The boot capacitor starts the cycle fully charged
to a voltage of VB(0). Cg equals 1.2nF in
IR3876. Choose a sufficiently small ΔV such
that VB(0)-ΔV exceeds the maximum gate
threshold voltage to turn on the high side
MOSFET.
V (0)
B
CBOOT C
1 (8)
g
ΔV
Choose a boot capacitor value larger than the
calculated CBOOT in equation 8. Equation 8 is
based on charge balance at CCM operation.
Usually the boot capacitor will be discharged to
a much lower voltage when the circuit is
operating in DCM mode at light load, due to
much longer Q2 off time and the bias current
drawn by the IC. Boot capacitance needs to be
increased if insufficient turn-on of Q1 is
observed at light load, typically larger than
0.1µF is needed. The voltage rating of this part
needs to be larger than VB(0) plus the desired
derating voltage. Its ESR and ESL needs to be
low in order to allow it to deliver the large
current and di/dt’s which drive MOSFETs most
efficiently. In support of these requirements a
ceramic capacitor should be chosen.
Figure 18. Charge equirement during Load Step
Q CV 0.5Istept (6a)
2
1
1 LΔIstep
C
OUT
(6b)
V
DROP
2
VIN
V
OUT
The output voltage drop, VDROP, initially depends
on the characteristic of the output capacitor.
VDROP is the sum of the equivalent series
inductance (ESL) of the output capacitor times the
rate of change of the output current and the ESR
times the change of the output current.
14
IR3876MBF
DESIGN EXAMPLE
Design Criteria:
Choose an inductor with the lowest DCR and
AC power loss as possible to increase the
overall system efficiency. For instance, choose
MPL1055-1R21R manufactured by Delta. The
inductance of this part is 1.2µH and has 2.9mΩ
DCR. Ripple current needs to be recalculated
using the chosen inductor.
Input Voltage, VIN, = 7V to 16V
Output Voltage, VOUT = 1.05V
Switching Frequency, Fs = 300KHz
Inductor Ripple Current, 2ΔI = 3A
Maximum Output Current, IOUT = 12A
Over Current Trip, IOC = 18A
Overshoot Allowance, VOS = VOUT + 50mV
Undershoot Allowance, VDROP = 50mV
1.05V
216V 1.2uH 300K Hz
16V -1.05V
ΔI
1.36A
Choose an input capacitor:
Find RFF
:
2
1.05V
1 1.36A
1.05V
1V 20pF 300KHz
I
IN_RMS 12A
1
R
FF
175 K
16V
3
12A
3.1A
Pick a standard value 178 kΩ, 1% resistor.
Find RSET
:
A
Panasonic
10µF
(ECJ3YB1E106M)
accommodates 6 Arms of ripple current at
300KHz. Due to the chemistry of multilayer
ceramic capacitors, the capacitance varies over
temperature and operating voltage, both AC and
DC. One 10µF capacitor is recommended. In a
practical solution, one 1µF capacitor is required
along with the 10µF. The purpose of the 1µF
capacitor is to suppress the switching noise and
deliver high frequency current.
1.45.2m 18A
R
SET
6.55K
20A
The RDSON of the lower MOSFET could be
expected to increase by a factor of 1.4 over
temperature. Therefore, pick a 6.65kΩ, 1%
standard resistor.
Find a resistive voltage divider for VOUT = 1.05V:
R
2
Choose an output capacitor:
VFB
VOUT 0.5V
1
R
2
R
To meet the undershoot specification, select a
set of output capacitors which has an equivalent
ESR of 10mΩ (50mV/5A). To meet the
overshoot specification, equation 7 will be used
to calculate the minimum output capacitance. As
a result, 300µF will be needed for 5A load
removal. Combine those two requirements, one
can choose a set of output capacitors from
manufactures such as Sanyo or Rubycon. A
330µF (2SWZ330M R05) from Rubycon is
recommended. This capacitor has 4.5mΩ ESR
which leaves margin for the voltage drop of the
ESL during load step up.
R2 = 2.55kΩ, R1 = 2.80kΩ, both 1% standard
resistors.
Choose the soft start capacitor:
Once the soft start time has chosen, such as
1000us to reach to the reference voltage, a 22nF
for CSS is used to meet 1000us.
Choose an inductor to meet the design
specification:
V
OUT
V
IN
V
OUT
s
L
V
IN 2ΔIF
1.05V
16V 3A300KHz
16V -1.05V
1.1H
15
IR3876MBF
LAYOUT RECOMMENDATION
Bypass Capacitor:
V
IN
One 1µF high quality ceramic capacitor should be
placed as near VCC pin as possible. The other
end of capacitor can be connected to a via or
connected directly to GND plane. Use a GND
plane instead of a thin trace to the GND pin
because a thin trace have too much impedance.
ON
VOUT
IR3876
OFF
CIN
COUT
Boot Circuit:
CBOOT should be placed near the BOOT and
PHASE pins to reduce the impedance when the
upper MOSFET turns on.
Figure 20. Current Path of Power Stage
Power Stage:
Figure 20 shows the current paths and their
directions for the on and off periods. The on time
path has low average DC current and high AC
current. Therefore, it is recommended to place the
input ceramic capacitor, upper, and lower
MOSFET in a tight loop as shown in Figure 20.
The purpose of the tight loop from the input
ceramic capacitor is to suppress the high
frequency (10MHz range) switching noise and
reduce Electromagnetic Interference (EMI). If this
path has high inductance, the circuit will cause
voltage spikes and ringing, and increase the
switching loss. The off time path has low AC and
high average DC current. Therefore, it should be
laid out with a tight loop and wide trace at both
ends of the inductor. Lowering the loop resistance
reduces the power loss. The typical resistance
value of 1-ounce copper thickness is 0.5mΩ per
square inch.
16
IR3876MBF
PCB Metal and Components Placement
Lead lands (the 13 IC pins) width should be equal to nominal part lead width. The minimum lead to
lead spacing should be ≥ 0.2mm to minimize shorting.
Lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. The
outboard extension ensures a large toe fillet that can be easily inspected.
Pad lands (the 4 big pads) length and width should be equal to maximum part pad length and width.
However, the minimum metal to metal spacing should be no less than; 0.17mm for 2 oz. Copper or
no less than 0.1mm for 1 oz. Copper or no less than 0.23mm for 3 oz. Copper.
17
IR3876MBF
Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist
should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD pads.
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist
onto the copper of 0.05mm to accommodate solder resist misalignment.
Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to the
high aspect ratio of the solder resist strip separating the lead lands from the pad land.
18
IR3876MBF
Stencil Design
The Stencil apertures for the lead lands should be approximately 80% of the area of the lead lads.
Reducing the amount of solder deposited will minimize the occurrences of lead shorts. If too much
solder is deposited on the center pad the part will float and the lead lands will open.
The maximum length and width of the land pad stencil aperture should be equal to the solder resist
opening minus an annular 0.2mm pull back in order to decrease the risk of shorting the center land
to the lead lands when the part is pushed into the solder paste.
19
IR3876MBF
MILIMITERS
MIN MAX
INCHES
MILIMITERS
INCHES
DIM
A
A1
b
b1
c
D
E
e
e1
e2
MIN
0.0315
0
MAX
0.0394
0.002
DIM
L
M
N
O
P
Q
R
MIN
MAX
0.45
MIN
MAX
0.0177
0.1001
0.0314
0.0858
0.1316
0.05374
0.1081
0.063
0.8
0
0.375
0.25
1
0.35
2.441
0.703
2.079
3.242
1.265
2.644
1.5
0.0138
0.0962
0.0277
0.0819
0.1276
0.0498
0.1042
0.0591
0.05
0.475
0.35
2.541
0.803
2.179
3.342
1.365
2.744
1.6
0.1477
0.0098
0.1871
0.1379
0.203 REF.
0.008 REF.
5.000 BASIC
6.000 BASIC
1.033 BASIC
0.650 BASIC
0.852 BASIC
1.970 BASIC
2.364 BASIC
0.0407 BASIC
0.0256 BASIC
0.0259 BASIC
S
t1, t2, t3
t4
0.401 BASIC
1.153 BASIC
0.727 BASIC
0.016 BACIS
0.045 BASIC
0.0286 BASIC
t5
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 09/2010
20
相关型号：
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