IR3892M_技术文档

Dual output, 6A/Phase, Highly Integrated SupIRBuck^®

IR3892

Single-Input Voltage, Synchronous Buck Regulator

FEATURES

DESCRIPTION

The IR3892 SupIRBuck^®is an easy-to-use, fully

integrated and highly efficient DC/DC regulator. The

onboard PWM controller and MOSFETs make IR3892

a space-efficient solution, providing accurate power

delivery for low output voltage.

• Single 5V to 21V application

• Wide Input Voltage Range from 1V to 21V with

external Vcc

• Output Voltage Range: 0.5V to 0.86*PVin

• Dual output, 6A/Phase

IR3892 is

a

versatile regulator which offers

• Enhanced Line/Load Regulation with Feed-

Forward

programmability of switching frequency and a fixed

current limit while operating in wide input and output

voltage range.

• Programmable Switching Frequency up to 1.0MHz

• Internal Digital Soft-Start

• Enable input with Voltage Monitoring Capability

The switching frequency is programmable from

300kHz to 1.0MHz for an optimum solution.

• Thermally compensated current limit and Hiccup

Mode Over Current Protection

It also features important protection functions, such as

Over Voltage Protection (OVP), Pre-Bias startup,

hiccup current limit and thermal shutdown to give

required system level security in the event of fault

conditions.

• External synchronization with Smooth Clocking

• Precision Reference Voltage (0.5V +/-1%)

• Seq pin for Sequencing Applications

• Integrated MOSFETs, drivers and Bootstrap diode

• Thermal Shut Down

APPLICATIONS

• Open Feedback Line Protection

• Sever Applications

• Over Voltage Protection

• Netcom Applications

• Interleaved Phases to reduce Input Capacitors

• Monotonic Start-Up

• Operating Junction Temp: -40^oC<Tj<125^oC

• Set Top Box Applications

• Storage Applications

• Small Size 5mm x 6mm PQFN

• Embedded telecom Systems

• Distributed Point of Load Power Architectures

• Computing Peripheral Voltage regulators

• General DC-DC Converters

• Lead-free, Halogen-free, and RoHS Compliant

ORDERING INFORMATION

Base Part

Standard Pack

Quantity

4000

Orderable Part

Number

Package Type

Form

Number

IR3892

PQFN 5mm x 6mm

Tape and Reel

IR3892MTRPBF

IR3892

PBF

TR

M

Lead Free

Tape and Reel

Package Type

1

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IR3892

BASIC APPLICATION

5V < Vin < 21V

Seq

Vcc

PG2 PG1

Vin

PVin1/2

Boot1

SW1

Boot2

Vo2

Vo1

SW2

Vsns2

Vsns1

Fb2

Fb1

Comp1

Comp

2

Rt/

Gnd PGnd1/2

Sync

Figure 1: IR3892 Basic Application Circuit

Figure 2: Efficiency [Vin=12V, Fsw=600kHz]

PIN DIAGRAM

5mm X 6mm POWER QFN

Top View

22

21

20

19

PGnd1 23

18 PGnd2

17 PGnd2

PGnd1 24

PGnd1 25

SW1

SW2

16 PGnd2

15 PVin2

14 PVin2

13 Boot2

PVin1 26

PVin1 27

Boot1 28

PGood1 29

Comp1 30

12 PGood2

11 Comp2

10 FB2

FB1 31

1

2

3

4

5

6

7

8

9

2

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IR3892

FUNCTIONAL BLOCK DIAGRAM

Vin

VCC/LDO_out

UVLO

LDO

-

UVLO

+

VCC

Boot

+

-

THERMAL

SHUTDOWN

TSD

V_{LDO_REF}

FAULT

CONTROL

Gnd

OV/OFLP

POR

OC

Comp

Seq*

VREF

+

FAULT

E/A

PVin

-

+

FB

HDin

HDrv

LDrv

fb

Intl_SS

GATE

DRIVE

LOGIC

Rff

FAULT

SW

FAULT

POR

Vin

SOFT

START

VCC

LDin

OC

SSOK

VREF

POR

CONTROL

LOGIC

UVEN

POR

PGnd

UVEN

EN

OVER CURRENT

PROTECTION

UVLO

VREF

FB

UV/

OV/OLFP

UV/

OV/OLFP

Rt/Sync

Vsns

PGood

*The Seq pin is only available for channel 2

Figure 3: IR3892 Simplified Block Diagram (one phase)

3

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IR3892

PIN DESCRIPTIONS

PIN #

PIN NAME

PIN DESCRIPTION

Sense pins for over-voltage protection and PGood. A resistor divider

with the same ratio as the respective feedback resistor divider should be

connected between each Vsns pin and its respective Vout.

1, 9

2, 8

3

Vsns 1/2

EN 1/2

Vin

Enable pins for turning on and off the regulator.

Input voltage for Internal LDO. A 1.0µF capacitor should be connected

between this pin and PGnd. If external supply is connected to VCC pin,

this pin should be shorted to VCC pin.

Input Bias Voltage, output of the internal LDO. Place a minimum 2.2µF

cap from this pin to PGnd.

4

5

VCC/LDO_out

GND

Signal ground for internal reference and control circuitry.

Input to error amplifier for sequencing purposes. Can be left floating for

non-sequencing applications. It is only connected to the Error-Amplifier

of channel 2.

6

7

Seq

Multi-function pin to set switching frequency. Use an external resistor

from this pin to Gnd to set the free-running switching frequency. Or use

an external clock signal to connect to this pin through a diode, the

device’s switching frequency is synchronized with the external clock.

Rt/Sync

Inverting inputs to the error amplifiers. These pins are connected directly

to the outputs of the regulator via resistor dividers to set the output

voltages and provide feedback to the error amplifiers.

10, 31

11, 30

FB 2/1

Output of the error amplifiers. External resistor and capacitor networks

are typically connected from these pins to its respective Fb pin to provide

loop compensation.

Comp 2/1

Power Good status pins are open drain outputs. The pins are typically

connected to VCC via pull up resistors.

12, 29

13, 28

PGood 2/1

Boot 2/1

Supply voltages for high side drivers, 100nF capacitors should be

connected between these pins and their respective SW pin.

14, 15, 26,

27

PVin 2/1

PGnd 2/1

SW 2/1

Input voltage for power stage.

Power Ground. These pins serve as a separated ground for the

MOSFET drivers and should be connected to the system’s power ground

plane.

16, 17, 18,

23, 24, 25

19, 20, 21,

22

Switch nodes. These pins are connected to the output inductors.

4

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IR3892

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications are not implied.

PVin

-0.3V to 25V

Vin

-0.3V to 25V

VCC

SW

BOOT

-0.3V to 8V (Note 1)

-0.3V to 25V (DC), -4V to 25V (AC, 100ns)

-0.3V to 33V

BOOT to SW

EN, PGood

Other Input/Output pins

PGnd to GND

Junction Temperature Range

Storage Temperature Range

-0.3V to VCC + 0.3V (Note 2)

-0.3V to 3.9V

-0.3V to + 0.3V

-40°C to 150°C

-55°C to 150°C

Machine Model

Class A

Human Body Model

ESD

Class 1C

Class III

Charged Device Model

Moisture Sensitivity level

RoHS Compliant

JEDEC Level 2 @ 260°C

Yes

Note:

1. VCC must not exceed 7.5V for Junction Temperature between -10°C and -40°C.

2. Must not exceed 8V.

THERMAL INFORMATION

Thermal Resistance, Junction to Case Top (θ_{JC_TOP}

)

36 °C/W

3.6 °C/W

24.7 °C/W

Thermal Resistance, Junction to PCB (θ_JB)

Thermal Resistance, Junction to Ambient (θ_JA) (Note 3)

Note:

3. Thermal resistance (θ_JA) is measured with components mounted on a high effective thermal conductivity

test board in free air.

5

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IR3892

ELECTRICAL SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

SYMBOL

UNIT

DEFINITION

Input Bus Voltage *

Supply Voltage

Supply Voltage **

Supply Voltage

Output Voltage

Output Current

Switching Frequency

Junction Temperature

MIN

1.0

5.0

4.5

0.5

0

MAX

21

7.5

PVin

Vin

VCC

V

Boot to SW

V_O

I_O

Fs

T_J

0.86 * PVin

6

A / Phase

kHz

300

-40

1000

125

°C

*

**

SW1/2 node must not exceed 25V

When VCC is connected to an externally regulated supply, also connect Vin.

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, these specifications apply over, 6.8V < Vin=PVin < 21V in 0°C < T_J< 125°C.

Typical values are specified at T_a= 25°C.

PARAMETER

Power Stage

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

Vin = 12V, Vout₁= 1.8V,

Vout₂= 1.2V, I_O=

6A/phase, Fs = 600kHz,

L1 =1.0uH, L2=1.0uH,

Note 4

2.72

W

Power Losses

P_LOSS

VBoot - Vsw= 5.5V, I_O=

4A, Tj = 25°C

Vcc = 5.5V, I_O= 4A, Tj =

25°C

Top Switch

R_{ds(on)_Top}

R_{ds(on)_Bot}

27.5

19.5

300

36.4

24.2

mΩ

Bottom Switch

Bootstrap Diode

Forward Voltage

mV

I(Boot) = 10mA

450

1

SW Leakage Current

I_SW

SW = 0V, Enable = 0V

µA

SW = 0V, Enable = high,

VSeq = 0V

2

Dead Band Time

T_db

Note 4

10

20

30

ns

Supply Current

VIN Supply Current

(standby)

EN = Low, No Switching

EN = High, Fs = 600kHz,

100

µA

I_in(Standby)

I_in(Dyn)

175

17

VIN Supply Current

(dynamic)

mA

12.0

5.3

VCC LDO Output

Vin(min) = 6.8V, Io = 0-

60mA, Cload = 2.2uF

Output Voltage

V_cc

5

5.6

V

Icc = 60mA, Cload =

2.2uF

VCC Dropout

V_{cc_drop}

Ishort

0.75

V

Short Circuit Current

120

mA

6

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IR3892

PARAMETER

SYMBOL

CONDITIONS

Oscillator

MIN

TYP

MAX

UNIT

Rt Voltage

Vrt

F_s

1.0

300

600

V

Rt = 80.6K

270

540

900

330

660

Frequency Range

Ramp Amplitude

Rt = 39.2K

kHz

Rt = 23.2K, Note 4

1000 1100

1.02

Vin = 6.8V, Vin slew rate

max = 1V/μs, Note 4

Vin = 12V, Vin slew rate

max = 1V/μs, Note 4

1.80

3.15

0.75

Vramp

Vp-p

Vin = 21V, Vin slew rate

max = 1V/μs, Note 4

Vcc=Vin = 5V, For

external Vcc operation,

Note 4

Min Pulse Width

Max Duty Cycle

Tmin(ctrl)

Dmax

Note 4

60

ns

%

Fs = 300kHz,

Vin=Pvin=12V

86

Fixed Off Time

Toff

Fsync

Tsync

High

Note 4

200

250

ns

kHz

ns

Sync Frequency Range

Sync Pulse Duration

270

100

3

1100

Sync Level Threshold

V

Low

0.6

Error Amplifier

Seq Input Offset

Voltage

VSeq – Vfb;

VSeq=250mV

Vos_VSeq

IFb(E/A)

-3

+3

%

Input Bias Current

-200

+200

nA

Internal Seq pull-up

resistor

300

kΩ

Seq Input impedance

Rin_Seq(E/A)

Sink Current

Source Current

Slew Rate

Isink(E/A)

Isource(E/A)

SR

0.4

3

0.85

4

1.2

7

mA

Note 4

7

12

30

20

40

V/µs

MHz

Gain-Bandwidth

Product

20

GBWP

DC Gain

Gain

Note 4

80

90

2

110

2.3

dB

V

Maximum Voltage

Vmax(E/A)

1.7

Minimum Voltage

Vmin(E/A)

120

220

mV

V

Vseq Common Mode

Voltage

0

0.77

7

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IR3892

PARAMETER

Reference Voltage

Feedback Voltage

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

Vfb

VSeq=3.3V

0.5

V

0°C < Tj < 85°C

-1

+1

Accuracy

%

-40°C < Tj < 125°C,

Note 5

-1.5

+1.5

Soft Start

mV /

µs

Soft Start Ramp Rate

Ramp (SS_start)

I_CC

0.14

7.8

0.18

9

0.22

10.4

Fault Protecion

A /

Phase

Current Limit

Vcc=5.5V, Tj = 25°C

Hiccup blanking time

OFLP Trip Threshold

OFLP Fault Prop Delay

OVP Trip Threshold

Tblk_Hiccup

OFLP(threshold)

OFLP(delay)

Note 4

20.48

70

ms

%Vref

µs

Fb Falling

65

0.1

115

75

0.5

125

0.3

OVP(threshold)

Vsns Rising

120

%Vref

Vsns falling from above

120% of Vref, Sync_FET

turns off afterwards

OVP Trip Threshold

Hysteresis

OVP_Hys

25

mV

OVP Comparator Delay

Thermal Shutdown

OVP(delay)

2

µs

°C

Note 4

140

20

Thermal Hysteresis

V_CC-Start-Threshold

VCC_UVLO_Start VCC Rising Trip Level

VCC_UVLO_Stop VCC Falling Trip Level

4.0

3.7

4.2

3.9

4.4

4.1

V

V_CC-Stop-Threshold

Input / Output Signals

Enable-Start-Threshold

Enable-Stop-Threshold

Enable leakage current

EN_UVLO_Start

EN_UVLO_Stop

Ien

Supply ramping up

Supply ramping down

Enable=3.3V

1.14

0.95

1.2

1

1.26

1.05

4.5

V

3

µA

Power Good upper

Threshold

Power Good lower

Threshold

Lower Threshold Delay

PGood Voltage Low

VPG(upper)

VPG(lower)

Vsns Rising

Vsns Falling

80

85

90

85

%Vref

75

1

80

%Vref

VPG(lower)_Dly

PG(voltage)

Vsns Rising

I_Pgood= -5mA

1.3

1.6

0.5

ms

V

Note:

4. Guaranteed by design but not tested in production.

5. Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in

production.

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IR3892

TYPICAL EFFICIENCY AND POWER LOSS CURVES

PVin = 12V, Vcc = Internal LDO, Io=0-6A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the losses of

the inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table

below shows the indicator used for each of the output voltages in the efficiency measurement while running a

single channel and disabling the other.

VOUT (V)

1.0

LOUT (uH)

0.82

1.0

P/N

DCR (mΩ)

4.2

SPM6550T-R82M (TDK)

1.2

1.8

3.3

5.0

SPM6550T-1R0M100A (TDK)

7443340220 (Wurth Electronik)

4.7

4.4

1.0

2.2

9

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IR3892

TYPICAL EFFICIENCY AND POWER LOSS CURVES

PVin = 12V, Vin = Vcc = 5V, Io=0-6A, Fs= 600kHz, Room Temperature, No Air Flow. Note that the losses of the

inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table

below shows the indicator used for each of the output voltages in the efficiency measurement while running a

single channel and disabling the other.

VOUT (V)

1.0

LOUT (uH)

0.82

1.0

P/N

DCR (mΩ)

4.2

SPM6550T-R82M (TDK)

1.2

1.8

3.3

5.0

SPM6550T-1R0M100A (TDK)

7443340220 (Wurth Electronik)

4.7

4.4

1.0

2.2

10

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IR3892

TYPICAL EFFICIENCY AND POWER LOSS CURVES

PVin = 5V, Vcc = 5V, Io=0-6A, Fs = 600kHz, Room Temperature, No Air Flow. Note that the losses of the

inductor, input and output capacitors are also considered in the efficiency and power loss curves. The table

below shows the indicator used for each of the output voltages in the efficiency measurement while running a

single channel and disabling the other.

VOUT (V)

1.0

LOUT (uH)

0.68

P/N

DCR (mΩ)

PCMB065T-R65MS (Cyntec)

SPM6550T-R82M (TDK)

SPM6550T-1R0M100A (TDK)

3.9

4.2

4.7

1.2

1.8

3.3

0.82

1.0

98

96

94

92

90

88

86

84

82

80

78

76

74

0

1

2

3

4

5

6

Iout(A)

1.0Vout

1.2Vout

1.8Vout

3.3 Vout

2.0

1.5

1.0

0.5

0.0

0

1

2

3

4

5

6

Iout(A)

1.0Vout

1.2Vout

1.8Vout

3.3 Vout

11

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IR3892

THERMAL DERATING CURVES

Measurements are done on IR3892 Evaluation board. PCB is a 4 layer board with 2 oz copper and FR4 material.

Vin=PVin=12V, Vout1 = 1.8V, Vout2 = 1.2V, Iout1 = Iout2, VCC=internal LDO (5.3V), Fs = 600kHz

Vin=PVin=12V, Vout1 =3.3V, Vout2=1.8V, Iout1 = Iout2, VCC=internal LDO (5.3V), Fs = 600kHz

Note: International Rectifier Corporation specifies current rating of SupIRBuck devices conservatively. The

continuous current load capability might be higher than the rating of the device if input voltage is 12V typical and

switching frequency is below 600kHz. However, the maximum current is limited by the internal current limit and

designers need to consider enough guard bands between load current and minimum current limit to guarantee

that the device does not trip at steady state condition.

12

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IR3892

MOSFET RDSON VARIATION OVER TEMPERATURE

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IR3892

TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)

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IR3892

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IR3892

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IR3892

THEORY OF OPERATION

DESCRIPTION

voltage

exceeds

its

precise

threshold

(EN_UVLO_START), the respective channel turns on.

The precise threshold allows the user to implement an

Under-Voltage Lockout (UVLO) function. By deriving

the EN pin voltage from the bus voltage (PVin)

through a suitable resistor divider, the user can set a

PVin threshold voltage. The resistor divider scales the

PVin voltage for the EN pin. Only after the bus

voltage reaches or exceeds this level will the voltage

at the Enable pin exceeds its threshold and enable the

respective IR3892 channel. By connecting IR3892 in

this configuration, the user can enable the part by

applying PVin and ensures the IR3892 does not turn

on until the bus voltage reaches the desired level

(Figure 4). Therefore, in addition to being a logic input

pin that enables channels on IR3892, the EN pin also

offers UVLO functionality. UVLO functionality is

particularly desirable for high output voltage

applications, where it is beneficial to disable the

IR3892 until PVin exceeds the desired output voltage

level.

The IR3892 uses a PWM voltage mode control

scheme with external compensation to provide good

noise immunity and maximum flexibility in selecting

inductor values and capacitor types.

The switching frequency is programmable from

300KHz to 1.0MHz and provides the capability of

optimizing the design in terms of size and

performance.

IR3892 provides precisely regulated output voltage

programmed via two external resistors from 0.5V to

0.86*PVin.

The IR3892 operates with an internal low drop out

regulator (LDO) which is connected to the VCC pin.

This allows operation with a single supply. When

using the internal LDO supply, the Vin pin should be

connected the PVin pin. If an external bias is used, it

should be connected to the VCC pin and the Vin pin

should be shorted to the VCC pin.

12V

The device utilizes the on-resistance of the low side

MOSFET (sync FET) as a current sense element.

This method enhances the converter’s efficiency and

reduces cost by eliminating the need for an external

current sense resistor.

10.2V

PVin

Vcc

IR3892 includes two low Rds(on) MOSFETs using

> 1.2V

1.2V

EN_UVLO_START

IR’s HEXFET technology.

These are specifically

EN

designed for high efficiency applications.

UNDER-VOLTAGE LOCKOUT AND POR

Intl_SS

The under-voltage lockout circuits monitor the voltage

on the VCC pin and the EN1/2 pins. They ensure that

the MOSFET driver outputs remain in the off state

whenever either of these signals drops below the set

thresholds. Normal operation resumes once VCC and

EN rise above their thresholds.

Figure 4: Normal Startup: IR3892 Channel starts when

PVin reaches 10.2V by connecting EN to PVin using a

resistor divider.

The POR (Power On Ready) signal is high when all

these signals reach the valid logic level (see system

block diagram).

ENABLE

The EN pin offers another level of flexibility for startup.

Each channel of the IR3892 is controlled by a

separate EN pin. When the voltage at an EN pin

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IR3892

[V]

PVin=Vin

Vcc

Vo

Pre-Bias

Voltage

> 1.2V

EN1/2

Intl_SS 1/2

Vo 1/2

[Time]

Figure 7: Pre-bias Start Up

Figure 5: Recommended startup for Normal operation

...

HDRv

LDRv

...

PVin=Vin

Vcc

...

87.5%

12.5%

16

25%

...

> 1.2V

End of

PB

...

16

EN2

Intl_SS 2

Figure 8: Pre-bias startup pulses

> 1.2V

EN1

Intl_SS 1

Vo1

SOFT-START

IR3892 has an internal digital soft-start to control the

output voltage rise and to limit the current surge

during start-up. To ensure the correct start-up, the

soft-start sequence initiates when the EN and VCC

rise above their UVLO thresholds and generates

Power On Ready (POR) signal. The internal soft-start

rises with the typical rate of 0.2mV/µS from 0V to

1.5V. Figure 9 shows the waveforms during soft-start.

The normal Vout start-up time is fixed, and is equal to:

Vo2

Figure 6: Recommended startup for sequencing

operation (ratiometric or simultaneous)

Figure 5 shows the recommended start-up sequence

for the normal (non-sequencing) operation of IR3892,

when EN pins are used as a logic input. Figure 6

shows the recommended startup sequence for

sequenced operation of IR3892.

(

0.65V − 0.15V

0.18mV / µS

)

= 2.7mS

Tstart =

(1)

PRE-BIAS STARTUP

IR3892 begins each start up by pre-charging the

output to prevent oscillation and disturbances to the

output voltage. The buck converter starts in an

asynchronous fashion and keeps the synchronous

MOSFET (Sync FET) off until the first gate signal for

control MOSFET (Ctrl FET) is generated. Figure 7

shows a typical pre-bias sequence. The sync FET

always starts with a narrow pulse width (12.5% of the

switching period). The pulse width increase after 16

pulses by 12.5% until the output reaches steady state

value. There are 16 pulses for each step. Figure 8

shows the series of 16 x 8 startup pulses.

During the soft-start the over-current protection (OCP)

and the over-voltage protection (OVP) is enabled to

protect the device from short circuit or over voltage

events.

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IR3892

from Rt/Sync pin to GND is required to set the free

running frequency.

POR

3.0V

1.5V

When an external clock is applied to Rt/Sync pin after

the converter runs in steady state with its free-running

frequency, a transition from the free-running frequency

to the external clock frequency will happen. The

switching frequency gradually synchronizes to the

external clock frequency regardless of which one is

faster. On the contrary, when the external clock signal

is removed from Rt/Sync pin, the switching frequency

gradually returns to the free-running frequency. In

order to minimize the impact from these transitions to

output voltage, a diode is recommended to add

between the external clock and Rt/Sync pin. Figure 10

shows the timing diagram of these transitions.

0.65V

0.15V

Intl_SS

Vout

t₁t₂t₃

Figure 9: Theoretical operation waveforms during soft-

start (non-sequencing)

OPERATING FREQUENCY

The switching frequency can be programmed between

300KHz-1.0MHz by connecting an external resistor

from R_t/Sync pin to GND. Table 1 tabulates the

oscillator frequency versus R_t.

Free Running

Frequency

Synchronize to the

external clock

Return to free-

running freq

...

SW

Table 1: Switching Frequency (Fs) vs. External

Resistor (R_t)

Gradually change

Fs1

SYNC

Fs1

...

Freq

Rt (KΩ)

(KHz)

Fs2

80.6

60.4

48.7

39.2

34

29.4

26.1

23.2

300

400

500

600

700

800

900

1000

Figure 10: Timing diagram for synchronization to an

external clock (Fs1>Fs2 or Fs1<Fs2)

An internal compensation circuit is used to change the

PWM ramp slope according to the clock frequency

applied on Rt/Sync pin. Thus, the effective amplitude

of the PWM ramp (Vramp), which is used in

compensation loop calculation, has minor impact from

the variation of the external synchronization signal.

Vin variation also affects the ramp amplitude, which is

discussed separately in Feed-Forward section.

EXTERNAL SYNCHRONIZATION

IR3892 incorporates an internal phase lock loop (PLL)

circuit which enables synchronization of the internal

SHUTDOWN

oscillator to an external clock.

This function is

IR3892 shutdown occurs when VCC drops below its

threshold or a fault occurs. When VCC falls below

VCC_UVLO_STOP, the part detects an UVLO event

and the part turns off. Over-Voltage Protection, Over-

Current Protection and Thermal Shutdown also cause

the IR3892 shutdown. Faults are discussed in more

detail below.

important to avoid sub-harmonic oscillations due to

beat frequency for embedded systems when multiple

point-of-load (POL) regulators are used. A multiple-

function pin, Rt/Sync, is used to connect the external

clock. If the external clock is present before the

converter turns on, Rt/Sync pin can be connected to

the external clock solely and no resistor is required. If

the external clock is applied after the converter turns

on, or the converter switching frequency needs to

toggle between the external clock frequency and the

internal free-running frequency, an external resistor

Each channel of the IR3892 can be shutdown

separately by pulling the channel EN pin below its low

threshold. Each EN pin controls only one channel to

allow the user to operate each independently.

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IR3892

Figure 11: Timing diagram for pulse-by-pulse current

limit and Hiccup mode

OVER CURRENT PROTECTION (CURRENT LIMIT

AND HICCUP MODE)

THERMAL SHUTDOWN

The over-current protection is performed by sensing

current through the R_DS(on)of the Sync FET. This

method enhances the converter’s efficiency and

reduces cost by eliminating a current sense resistor.

The current limit is pre-set internally and compensated

to maintain an almost constant limit over temperature.

IR3892 provides thermal protection. A thermal fault is

detected, when the temperature of the part reaches

the Thermal Shutdown Threshold, 145°C typical. A

thermal fault results in both channels turning off. The

power MOSFETs are disabled during thermal

shutdown. IR3892 automatically restarts when the

temperature of the part drops back below the lower

thermal limit, typically 20°C below the Thermal

Shutdown Threshold.

IR3892 determines over-current events when the

Synchronous FET is on. OCP circuit samples this

current for 40 nsec typically after the rising edge of the

PWM set pulse which has a width of 12.5% of the

switching period. The PWM pulse starts at the falling

edge of the PWM set pulse. This makes valley

current sense more robust as current is sensed close

to the bottom of the inductor downward slope where

transient and switching noise are lower and helps to

prevent false tripping due to noise and transient. An

OC condition is detected if the load current exceeds

the threshold, the converter enters into hiccup mode.

PGood will go low and the internal soft start signal will

be pulled low.

FEED-FORWARD

Feed-Forward is an important feature which helps with

stability and preserves load transient performance

during PVin changes. In IR3892, Feed-Forward (F.F.)

function is enabled when Vin pin is connected to PVin

pin and Vin>5.0V. The PWM ramp amplitude (Vramp)

is proportionally changed with respect to Vin to

maintain PVin/Vramp ratio.

The ratio is almost

constant throughout the Vin range (as shown in Figure

12). By maintaining a constant PVin/Vramp, the

control loop bandwidth and phase margin are more

constant. F.F. function also helps minimize the effect

of PVin changes on the output voltage.

∆i

2

I_OCP= I_LIMIT

+

(2)

I_OCP

I_LIMIT

Δi

= DC current limit hiccup point

= Current Limit Valley Point

= Inductor ripple current

Feed-Forward is based on the Vin voltage and needs

to be accounted for when calculating IR3892

compensation.

The PVin/Vramp ratio is not

maintained when Vin and PVin are not equal. This is

the case when an external bias voltage for VCC.

When using an external VCC voltage, Vin pin should

be connected to the VCC pin instead of the PVin pin.

Compensation for the configuration should reflect the

separation.

Hiccup mode is when the converter stops and waits

before restarting. The channel waits for Tblk_Hiccup,

2.48 ms typical, before the OC signal resets and

restarts. In normal application, the converter restarts

with a pre-bias sequence and soft-start. Figure 11

shows the timing diagram of the above OC protection.

If another OC event is detected, the part repeats

hiccup mode.

16V

12V

6.8V

Vin

0

Current Limit

Hiccup

PWM Ramp

Amplitude = 2.4V

PWM Ramp

Amplitude = 1.8V

PWM Ramp

Amplitude = 1.02V

Tblk_Hiccup

20.48 mS*

IL

0

Ramp Offset

0

HDrv

...

Figure 12: Timing diagram for Feed Forward (F.F.)

Function

0

LDrv

0

*typical filter delay

PGood

0

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IR3892

LOW DROPOUT REGULATOR (LDO)

Ext VCC

PVin

Vin

IR3892

PVin

IR3892 has an integrated low dropout (LDO) regulator

which can provide gate drive voltage for both drivers.

When using an internally biased configuration, the

LDO draws from the Vin pin and provides a 5.3V

(typ.), as shown in Figure 13. Vin and PVin can be

connected together as shown in the internally biased

single rail configuration, Figure 14.

VCC

PGND

An external bias configuration can provide gate drive

voltage for the drivers instead of the internal LDO. To

use an external bias, connected to Vin and VCC to the

external bias, as shown in Figure 15. PVin can also

be connected or a different rail can be used.

Figure 15: Externally Biased Configuration

When using multiple rail configurations, calculate the

compensation Vramp associated with Vin. Vramp is

derived from Vin which can be different from PVin,

refer to Feed-Forward section.

OUTPUT VOLTAGE SEQUENCING

IR3892 can accommodate user sequencing options

using Seq, EN1/2, and PGood1/2 pins. In the block

diagram presented on page 3, the error-amplifier (E/A)

has been depicted with three positive inputs. Ideally,

the input with the lowest voltage is used for regulating

the output voltage and the other two inputs are

ignored. In practice the voltages of the other two

inputs should be at least 200mV greater than the

referenced voltage input so that their effects can

completely be ignored.

Vin

PVin

Vin

IR3892

PVin

VCC

In normal operating condition, the IR3892 channels

initially follow their internal soft-starts (Intl_SS) and

then references VREF. After Enable goes high,

Intl_SS begins to ramp up from 0V. The FB pin

follows the Intl_SS until it approaches VREF where

the E/A starts to reference the VREF instead of the

Intl_SS (refer to Figure 16). VREF and Seq are not

referenced initially because they are higher than

Intl_SS. VREF is 0.5V, typical. Seq is internally pulled

up to approximately 3.3V when left floating in normal

operation and only used by channel 2.

PGND

Figure 13: Internally Biased Configuration

Vin

IR3892

PVin

In sequencing mode of operation, Vout2 is initially

regulated with the Seq pin. Vout2 ramps up similar to

the normal operation, but Intl_SS is replaced with Seq.

Seq is kept to ground level until Intl_SS signal reaches

its final value. FB2 follows Seq, until Seq approaches

VREF where the E/A switches reference to the VREF.

Vout2 is then regulated with respect to internal VREF

(refer to Figure 17). The final Seq voltage should

between 0.7V and 3.3V.

VCC

PGND

Figure 14: Internally Biased Single Rail Configuration

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IR3892

resistor values are set up in the following way, R_A/R_B>

R_E/R_F> R_C/R_D.

0.65V

OVP

Is Activated

Intl_SS

OVP(Threshold)

Table 2 summarizes the required conditions to

achieve simultaneous or ratiometric sequencing

operations.

OVP(Hys)

LDrv

VPG(Upper)

VPG(Lower)

turned off

Table 2: Required Conditions for Simultaneous /

Ratiometric Tracking and Sequencing

FB/Vsns

PGood

Required

Condition

Operating Mode

Seq

1.3 mS*

Normal

* typical filter delay

(Non-sequencing,

Non-tracking)

Simultaneous

Sequencing

Ratiometric

Sequencing

Floating

―

Ramp up R_A/R_B>R_E/R_F=R_C/R_D

from 0V

Ramp up R_A/R_B>R_E/R_F>R_C/R_D

from 0V

Figure 16: Timing Diagram for Output Sequence

Intl_SS

(>0.7V)

VREF

Vin

Seq

Vo1

Vo2

OVP(Threshold)

Boot2

R_C

VPG(Upper)

Threshold

VPG(Lower)

Threshold

R_A

R_B

FB1

FB2

R_D

FB/Vsns

PGood

Comp1

Vsns1

PGood1

Seq

Comp2

Vsns2

PGood2

Rt/Sync

1.3 mS*

2uS*

Vo1

R_E

*typical filter delay

R_F

Figure 17: Timing Diagram for Sequence Startup (Seq

ramping up/down)

Figure 18: Application Circuit for Simultaneous

and Ratiometric Sequencing

IR3892 can perform simultaneous or ratiometric

sequencing operations. Simultaneous sequencing is

when the both outputs rise at the same rate. During

Ratiometric sequencing, the ratio of the two outputs is

held constant during power-up. Figure 19 shows

examples of the two sequencing modes.

IR3892 uses a single configuration to implement both

mode of sequencing operations. Figure 18 shows the

typical circuit configuration for both modes of

sequencing operation. The sequencing mode is

determined by the R_A/R_B, R_E/R_F, and R_C/R_Dratios. If

R_E/R_F= R_C/R_D, simultaneous startup is achieved.

Vout2 follows Vout1 until the voltage at the Seq pin

reaches VREF. After the voltage at the Seq pin

exceeds VREF, VREF dictates Vout2. In ratiometric

startup, Vout2 rises at a slower rate than Vout1. The

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IR3892

Open Feedback Loop protection (OFLP) is devised to

shutdown the channel in case the feedback is broken.

OFLP is activated when the Vsns is above the

Vcc

EN2

VPG(upper) threshold, 0.85*VREF typical,

remains active while Vsns is above the VPG(lower)

threshold, 0.80*VREF. When FB drop below

and

Intl_SS2

EN1

OFLP(threshold) threshold, 0.70*VREF, OFLP

disables switching and pulls down on PGood. The

part remains disabled until FB rises above

OFLP(threshold) plus OFLP(Hys), 0.75*VREF. This

function does not latch the part off nor does it require

an EN or a VCC toggle to re-enable the part.

Vo1 (master)

Vo2 (slave)

(a)

VPG(Lower)

Threshold

Vsns

(b)

VREF

OFLP Trip Threshold

Figure 19: Typical waveforms for sequencing mode of

operation: (a) simultaneous, (b) ratiometric

FB

PGood

OVER-VOLTAGE PROTECTION (OVP)

Figure 21: Timing Diagram for Open Feedback Line

Protection (OFLP)

Over-Voltage protection (OVP) disables the channel

when the output voltage exceeds the over-voltage

threshold. IR3892 achieves OVP by comparing Vsns

pin to the internal over-voltage threshold set at

OVP(threshold), 1.2*VREF typical. Vsns voltage is

determined by an external voltage divider resistor

network connected to the output in typical application.

When Vsns exceeds the over-voltage threshold, an

over-voltage is detected and OV signal asserts after

OVP(delay). The high side drive signal HDrv is turned

off immediately and PGood flags low. The low side

drive signal is kept on until the Vsns voltage drops

below the lower threshold. After that, HDrv is latched

off until a reset is performed by cycling either VCC or

the respective EN.

POWER GOOD OUTPUT

PGood is an open drain pin that monitors the UV,

FAULT and the POR signals. PGood signal asserts

approximately 1.3mS, after Vsns rises above

VGP(Upper) threshold, 0.85*VREF typical, while

FAULT is low and POR is high. It remains asserted

while FAULT is low and POR is high and Vsns stays

above VGP(Lower) threshold, 0.80*VREF typical.

When Vsns falls below VGP(Lower) threshold there is

a typical 2µS delay before PGood goes low. The two

PGood signals are independent of each other and are

set according to their respective channel.

SWITCH NODE PHASE SHIFT

OVP(Hys)

OVP(Threshold)

The two converters on the IR3892 run interleaving

phases by 180° to reduce input filter requirements.

The two converters are synchronized to the user

programmable oscillator. Channel 1 runs in phase with

the oscillator while channel 2 runs out of phase.

Staggering the switching cycles reduces the time the

Vsns

2uS *

PGood

HDrv

LDrv

converters

draw

current

from

the

supply

simultaneously. The pulses of current drawn from the

input induce voltage ripples across the input capacitor.

The voltage ripple shapes are dependent on the

different loading and output voltages of the two

converters. By switching the converters at different

times, the magnitude of voltage ripples reduces and

input filter requirements become less stringent.

*typical filter delay

Figure 20: Timing diagram for OVP

OPEN FEEDBACK-LOOP PROTECTION

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IR3892

MINIMUM ON-TIME CONSIDERATIONS

MAXIMUM DUTY RATIO

The minimum on-time is the shortest amount of time

which the Control FET may be reliably turned on.

Internal delays and gate drive make up a large portion

of the minimum on-time. IR3892 has a minimum on-

time of 60nS.

Maximum duty ratio is lower at higher frequencies and

higher Vin voltages. A maximum off-time of 250nS is

specified for IR3892. This provides an upper limit on

the operating duty ratio at any given switching

frequency. The off-time becomes a larger percentage

of the switching period when high switching

frequencies are used. Thus, a lower the maximum

duty ratio can be achieved when frequencies increase.

Any design or application using IR3892 should

operation with a pulse width greater than minimum on-

time. This is necessary for the circuit to operate

without jitter and pulse-skipping, which can cause high

inductor current ripple and high output voltage ripple.

Feed-Forward from the Vin voltage placed a limitation

on the maximum duty cycle by saturating the

compensation ramp.

By maintaining a constant

D

V_out

Vin/Vramp, the effective Vramp voltage is increased

while the maximum range is remains the same. The

ramp reaches the maximum limit before reaching the

expected level. Reaching the maximum limit ends the

switching cycle prematurely and results in a lower

maximum duty cycle.

t_on=

=

(3)

F_sPVin× F_s

In any application that uses IR3892, the following

condition must be satisfied:

t_on(min)≤ t_on

(4)

(5)

Maximum duty cycle is dependent on the Vin and

switching frequency. Figure 22 is a theoretical plot of

the maximum duty cycle vs. the switching frequency

using typical parameter values. It shows how the

maximum duty cycle is influenced by the Vin and the

switching frequency.

V_out

PV_in× F_s

V_out

t_on(min)

≤

∴PV_in× F_s≤

(6)

t_on(min)

The minimum output voltage is limited by the

reference voltage and hence Vout(min) = 0.5V. For

Vout(min) = 0.5V,

V_out

∴PV_in× F_s≤

0.5V

(7)

t_on(min)

∴PV_in× F_s≤

= 8.33V / µS

60nS

Therefore, with an input voltage 16V and minimum

output voltage, the converter should be designed for

switching frequency not to exceed 520kHz.

Conversely, the input voltage (PVin) should not

exceed 5.55V for operation at the maximum

recommended operating frequency (1.0MHz) and

minimum output voltage (0.5V). Increasing the PVin

greater than 5.55V will cause pulse skipping.

Figure 22: Maximum Duty Cycle vs. Switching

Frequency

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DESIGN EXAMPLE

The following example is a typical application for

IR3892. The application circuit is shown in

Output Voltage Programming

Output voltage is programmed by reference voltage

and external voltage divider. The FB pin is the

inverting input of the error amplifier, which is internally

referenced to VREF. The divider ratio is set to equal

VREF at the FB pin when the output is at its desired

value. When an external resistor divider is connected

to the output as shown in Figure 24, the output

voltage is defined by using the following equation:

V_in= PV_in= 12V (21V Max)

F_s= 600kHz

Channel 1:

V_o= 1.8V

I_o= 6A

Ripple Voltage = ± 1% * V_o

ΔV_o= ± 4% * Vo (for 30% load transient)





R

⁵

Channel 2:

V_o= 1.2V

I_o= 6A

Ripple Voltage = ± 1% * V_o

ΔV_o= ± 4% * Vo (for 30% load transient)



V_o=V_ref× 1+

(10)

(11)







R₆















V_ref

V_o−V_ref

R₆= R₅×

Enabling the IR3892

For the calculated values of R5 and R6, see feedback

compensation section.

As explained earlier, the precise threshold of the

Enable lends itself well to implementation of a UVLO

for the Bus Voltage as shown in Figure 23.

Vout

PVin

IR3892

R5

IR3892

R1

FB

R6

Enable

R2

Figure 24: Typical application of the IR3892

for programming the output voltage

Figure 23: Using Enable pin for UVLO implementation

For a typical Enable threshold of V_EN= 1.2 V

Bootstrap Capacitor Selection

To drive the Control FET, it is necessary to supply a

gate voltage at least 4V greater than the voltage at the

SW pin, which is connected to the source of the

Control FET. This is achieved by using a bootstrap

configuration, which comprises the internal bootstrap

diode and an external bootstrap capacitor (C1). The

operation of the circuit is as follows: When the sync

FET is turned on, the capacitor node connected to SW

is pulled down to ground. The capacitor charges

towards V_ccthrough the internal bootstrap diode

(Figure 25), which has a forward voltage drop V_D. The

voltage V_cacross the bootstrap capacitor C1 is

approximately given as:

R₂

PV_in(min)

×

=V_EN=1.2

(8)

(9)

R₁+ R₂

V_EN

R₂= R₁

PV_in(min)−V_EN

For PV_{in (min)}=9.2V, R₁=49.9K and R₂=7.5K ohm is a

good choice.

Programming the frequency

For F_s= 600 kHz, select R_t= 39.2 KΩ, using Table 1.

V_c≅ V_cc−V_D

(12)

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When the control FET turns on in the next cycle, the

capacitor node connected to SW rises to the bus

voltage V_in. However, if the value of C1 is

appropriately chosen, the voltage V_cacross C1

remains approximately unchanged and the voltage at

the Boot pin becomes:

Ceramic capacitors are recommended due to their

peak current capabilities. They also feature low ESR

and ESL at higher frequency which enables better

efficiency. For this application, it is advisable to have

4x10uF, 25V ceramic capacitors, C3216X5R1E106K

from TDK.

In addition to these, although not

mandatory, a 1x330uF, 25V SMD capacitor EEV-

FK1E331P from Panasonic may also be used as a

bulk capacitor and is recommended if the input power

supply is not located close to the converter.

V_Boot≅ V_in+V_cc−V_D

(13)

Cvin

V

IN

Inductor Selection

Inductors are selected based on output power,

operating frequency and efficiency requirements. A

low inductor value causes large ripple current,

resulting in the smaller size, faster response to a load

transient but may reduce efficiency and cause higher

output noise. Generally, the selection of the inductor

value can be reduced to the desired maximum ripple

current in the inductor (Δi). The optimum point is

usually found between 20% and 50% ripple of the

output current. For the buck converter, the inductor

value for the desired operating ripple current can be

determined using the following relation:

+ V_D

-

Boot

V

cc

+

Vc

-

C1

SW

L

IR3892

PGnd

Figure 25: Bootstrap circuit to generate Vc voltage

∆i

∆t

1

V_in−V_o= L× ;∆t = D×

A bootstrap capacitor of value 0.1uF is suitable for

most applications.

F_s

V_o

L =

(

V_in−V_o

)

×

(16)

Input Capacitor Selection

V_in× ∆i× F_s

The ripple currents generated during the on time of

the control FETs should be provided by the input

capacitor. The RMS value of this ripple for each

channel is expressed by:

Where:

V_in= Maximum input voltage

V₀= Output Voltage

Δi = Inductor Peak-to-Peak Ripple Current

F_s= Switching Frequency

Δt = On time for Control FET

I_RMS= I_o× D×

(

1− D

)

(14)

(15)

V_o

D =

D

= Duty Cycle

V_in

If Δi ≈ 30%*I_o, then the channel 1 output inductor is

calculated to be 1.42μH. Select L=1.0μH, SPM6550T-

1R0M100A, from TDK which provides a compact, low

profile inductor suitable for this application. For

channel 2, the output inductor is calculated to be

1.0μH. Select L=1.0μH, SPM6550T-1R0M100A, from

TDK.

Where:

D is the Duty Cycle

I_RMSis the RMS value of the input capacitor

current.

Io is the output current.

For channel 1, I_o=6A and D=0.15, the I_RMS= 2.14A.

For channel 2, I_o=6A and D=0.1, the I_RMS= 1.8A.

Output Capacitor Selection

The voltage ripple and transient requirements

determine the output capacitors type and values. The

criterion is normally based on the value of the

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Effective Series Resistance (ESR). However the

actual capacitance value and the Equivalent Series

Inductance (ESL) are other contributing components.

These components can be described as:

The output LC filter introduces a double pole, -

40dB/decade gain slope above its corner resonant

frequency, and a total phase lag of 180^o. The resonant

frequency of the LC filter is expressed as follows:

1

∆V_o= ∆V_o₎+ ∆V_o₎+ ∆V_o(C)

(

ESR

(

ESL

F_LC=

(18)

2×π × L_o×C_o

∆V_0(ESR)= ∆I_L× ESR

Figure 26 shows gain and phase of the LC filter. Since

we already have 180^ophase shift from the output filter

alone, the system runs the risk of being unstable.

V −V





_o



in

∆V_0(ESL)

∆V_0(C)

=

× ESL



L



Phase

Gain

∆I_L

8×C_o× F_s

=

(17)

0⁰

0dB

-40dB/Decade

Frequency

Where:

-90⁰

ΔV₀= Output Voltage Ripple

ΔI_L= Inductor Ripple Current

-180⁰

Frequency

F_LC

Since the output capacitor has a major role in the

overall performance of the converter and determines

the result of transient response, selection of the

capacitor is critical. The IR3892 can perform well with

all types of capacitors.

Figure 26: Gain and Phase of LC filter

The IR3892 uses a voltage-type error amplifier with

high-gain and high-bandwidth. The output of the

amplifier is available for DC gain control and AC

phase compensation.

As a rule, the capacitor must have low enough ESR to

meet output ripple and load transient requirements.

The error amplifier can be compensated either in type

II or type III compensation.

The goal for this design is to meet the voltage ripple

requirement in the smallest possible capacitor size.

Therefore it is advisable to select ceramic capacitors

due to their low ESR and ESL and small size. Four of

Local feedback with Type II compensation is shown in

Figure 27.

TDK

C2012X5R0J226M

(22uF/0805/X5R/6.3V)

capacitors is a good choice for channel 1 and channel

2.

This method requires that the output capacitor should

have enough ESR to satisfy stability requirements. If

the output capacitor’s ESR generates a zero at 5kHz

to 50kHz, the zero generates acceptable phase

margin and the Type II compensator can be used.

It is also recommended to use a 0.1µF ceramic

capacitor at the output for high frequency filtering.

Feedback Compensation

The ESR zero of the output capacitor is expressed as

follows:

The IR3892 is a voltage mode controller. The control

loop is a single voltage feedback path including error

amplifier and error comparator. To achieve fast

transient response and accurate output regulation, a

compensation circuit is necessary. The goal of the

compensation network is to have a stable closed-loop

transfer function with a high crossover frequency and

phase margin greater than 45^o.

1

F_ESR

=

(19)

2×π × ESR×C_o

27

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IR3892

V

OUT

F

_LC= Resonant Frequency of the Output Filter

Z_IN

C_POLE

C3

R₅= Feedback Resistor

R3

To cancel one of the LC filter poles, place the zero

before the LC filter resonant frequency pole:

R5

Z

f

Fb

E/A

F_Z= 75%× F_LC

Ve

R6

Comp

1

VREF

F_Z= 0.75×

(25)

Gain(dB)

2×π L_o×C_o

H(s) dB

Use equation (22), (23) and (24) to calculate C3.

Frequency

One more capacitor is sometimes added in parallel

with C3 and R3. This introduces one more pole which

is mainly used to suppress the switching noise.

F_POLE

F_Z

Figure 27: Type II compensation network

and its asymptotic gain plot

The additional pole is given by:

The transfer function (V_e/V_out) is given by:

1

F_p=

(26)

C₃×C_POLE

C₃+ C_POLE

2×π ×

Z _f

V_e

1+ sR₃C₃

= H(s) = −

= −

(20)

V_out

Z_IN

sR₅C₃

The pole sets to one half of the switching frequency

which results in the capacitor C_POLE

:

The (s) indicates that the transfer function varies as a

function of frequency. This configuration introduces a

gain and zero, expressed by:

1

C_POLE

=

≅

(27)

1

π

× R₃× F_S

π

× R₃× F_S−

R₃

C₃

H(s) =

(21)

(22)

R₅

For an unconditional stability general solution using

any type of output capacitors with a wide range of

ESR values, use local feedback with type III

compensation network. Type III compensation

network is typically used for voltage-mode controller

as shown in Figure 28.

1

F_z=

2×π × R₃×C₃

First select the desired zero-crossover frequency (F_o):

F_o> F_ESRand F_o≤ (1/5 ~1/10)× F_s

(23)

Use the following equation to calculate R3:

V_ramp× F_o× F_ESR× R₅

R₃=

(24)

V_in× F_L²_C

Where:

V_in= Maximum Input Voltage

V_ramp= Amplitude of the oscillator Ramp Voltage

F_o= Crossover Frequency

F

_ESR= Zero Frequency of the Output Capacitor

28

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IR3892

V_OUT

R5

1

Z_IN

F_Z1=

(32)

C2

C3

2π × R₃×C₃

C4

R4

R3

1

F_{Z 2}

=

≅

(33)

2π × C₄×

(

R₄× R₅

)

2π × C₄× R₅

Z_f

Cross over frequency is expressed as:

Fb

Ve

E A

/

R6

Comp

V_in

1

F_o= R₃×C₄×

×

(34)

V_ramp2π × L_o×C_o

V

REF

Gain (dB)

Based on the frequency of the zero generated by the

output capacitor and its ESR, relative to the crossover

frequency, the compensation type can be different.

Table 3 shows the compensation types for relative

locations of the crossover frequency.

|H(s)| dB

Frequency

F

P₃

Table 3: Different types of compensators

P₂

Z₁

Z₂

Figure 28: Type III Compensation network

and its asymptotic gain plot

Compensator

Type

Typical Output

Capacitor

F_ESRvs F_O

F_LC< F_ESR< F_O<

F_S/2

Again, the transfer function is given by:

Type II

Type III

Electrolytic

SP Cap,

Ceramic

Z _f

V_e

F_LC< F_O< F_ESR

= H(s) = −

V_out

Z_IN

The higher the crossover frequency is, the potentially

faster the load transient response will be. However,

the crossover frequency should be low enough to

allow attenuation of switching noise. Typically, the

control loop bandwidth or crossover frequency (F_o) is

selected such that:

By replacing Z_inand Z_f, according to Figure 28, the

transfer function can be expressed as:

(

1+ sR₃C₃

)

[

1+ sC₄

(

R₄+ R₅

)

]

H(s) = −













C₂×C₃





sR₅

(

C₂+ C₃

)

1+ sR

(

1+ sR C

)



3

4

C₂+ C₃





(

1/5 ~1/10 *F_s

)



F_o≤

(28)

The DC gain should be large enough to provide high

DC-regulation accuracy. The phase margin should be

greater than 45^ofor overall stability.

The compensation network has three poles and two

zeros and they are expressed as follows:

The specifications for designing channel 1:

V_in= 12V

V_o= 1.8V

F_P1= 0

F_P2=

(29)

1

V_ramp= 1.8V (This is a function of Vin, pls. see

(30)

(31)

Feed-Forward section)

V_ref= 0.5V

L_o= 1.0uH

C_o= 4x22uF, ESR≈3mΩ each

2π × R₄×C₄

1

F_P3=

≅





2π × R₃×C₂

C₂×C₃

C₂+ C₃





2π × R₃





It must be noted here that the value of the

capacitance used in the compensator design must be

29

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IR3892

Select: C₃= 4.7 nF

the small signal value. For instance, the small signal

capacitance of the 22uF capacitor used in this design

is 15uF at 1.8 V DC bias and 600 kHz frequency. It is

this value that must be used for all computations

related to the compensation. The small signal value

may be obtained from the manufacturer’s datasheets,

design tools or SPICE models. Alternatively, they may

also be inferred from measuring the power stage

transfer function of the converter and measuring the

double pole frequency F_LCand using equation (18) to

compute the small signal C_o.

1

C₂=

; C₂= 94 pF,

2×π × F_P3× R₃

Select: C₂= 100 pF

Calculate R₄, R₅and R₆:

1

R₄=

; R₄= 209.5 Ω,

2×π ×C₄× F_P2

These result to:

F_LC= 20.6 kHz

F_ESR= 3.54 MHz

Select R₄= 210 Ω

F_s/2 = 300 kHz

Select crossover frequency F₀=100 kHz

1

R₅=

; R₅= 1 kΩ,

2×π ×C₄× F_{Z 2}

Select R₅= 11.8 kΩ

V_ref

Since F_LC<F₀<Fs/2<F_ESR, Type III is selected to place

the pole and zeros.

Detailed calculation of compensation Type III:

R₆=

× R₅; R₆= 4.54 kΩ,

Desired Phase Margin Θ = 75°

V_o−V_ref

1− sinΘ

1+ sinΘ

Select R₆= 4.53 kΩ

F_{Z 2}= F_o

=

13.2 kHz

Setting the Power Good Threshold

In this design IR3892, the PGood outer limits are set

at 85% and 120% of VREF. PGood signal is asserted

1.3ms after Vsns voltage reaches 0.85*0.5V=0.425V.

1+ sin Θ

1− sin Θ

F_P2= F

=

759.6 kHz

o

Select:

As long as the Vsns voltage is between the threshold

range, Enable is high, and no fault happens, the

PGood remains high.

F_Z1= 0.5× F_{Z 2}= 6.6 kHz and

F_P3= 0.5× F_s= 300 kHz

The following formula can be used to set the PGood

threshold. V_{out (PGood}_TH can be taken as 85% of Vout.

)

Select C₄= 1nF.

Choose Rsns11=4.53 KΩ.

Calculate R₃, C₃and C₂:

V





out(PGood _TH )





Rsns12 =

−1 × Rsns11

(35)





2×π × F_o× L_o×C_o×V_ramp

0.85×VREF



R₃=

; R₃= 5.65 kΩ,

C₄×V_in

Rsns12 = 11.78 kΩ, Select 11.8 kΩ,

Select: R₃= 5.62 kΩ

OVP comparator also uses Vsns signal for Over-

Voltage detection. With above values for Rsns22 and

Rsns21, OVP trip point (Vout_{_OVP}) is

1

C₃=

; C₃= 4.29 nF,

2×π × F_Z1× R₃

30

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IR3892

(

Rsns11+ Rsns12

Rsns11

)

(36)

F_P3= 0.5× F_s= 300 kHz

Vout_{_OVP}=VREF ×1.2×

Select C₄= 1nF.

Calculate R₃, C₃and C₂:

Vout__OVP= 2.16 V

Selecting Power Good Pull-Up Resistor

2×π × F_o× L_o×C_o×V_ramp

The PGood1 and PGood2 are open drain outputs and

require pull up resistors to VCC. The value of the pull-

up resistors should limit the current flowing into the

each PGood pin to be less than 5mA. A typical value

used is 49.9kΩ.

R₃=

; R₃= 6.79 kΩ,

C₄×V_in

Select: R₃= 6.65 kΩ

1

The specifications for the channel 2 design:

C₃=

; C₃= 3.63 nF,

2×π × F_Z1× R₃

V_in=12V

V_o=1.2V

Select: C₃= 3.6 nF

V_ramp=1.8V (This is a function of Vin, pls. see feed

1

forward section)

V_ref=0.5V

L_o=1.0uH

C₂=

; C₂= 78.8 pF,

2×π × F_P3× R₃

C_o=4x22uF, ESR≈3mΩ each

Select: C₂= 82 pF

In the calculations, 18uF is used for the 22uF C_o

capacitors due to the 1.2V bias and 600 kHz

frequency.

Calculate R₄, R₅and R₆:

1

R₄=

; R₄= 209.5 Ω,

2×π ×C₄× F_P2

These result to:

F_LC= 18.8 kHz

F_ESR= 2.95 MHz

Select R₄= 210 Ω

F_s/2 = 300 kHz

Select crossover frequency F₀=100 kHz

1

R₅=

; R₅= 12.1 kΩ,

2×π ×C₄× F_{Z 2}

Select R₅= 11.8 kΩ

V_ref

Since F_LC<F₀<Fs/2<F_ESR, Type III is selected to place

the pole and zeros.

Detailed calculation of compensation Type III:

R₆=

× R₅; R₆= 8.43 kΩ,

Desired Phase Margin Θ = 75°

V_o−V_ref

1− sinΘ

1+ sinΘ

Select R₆= 8.45 kΩ

F_{Z 2}= F_o

=

13.2 kHz

Setting the Power Good Threshold

1+ sin Θ

1− sin Θ

Equation (35) shows how to set values for Rsns12

and Rsns11. Use the same equation to determine

Rsns21 and Rsns22 values, but substitute Rsns22 for

Rsns12 and Rsns21 for Rsns11.

F_P2= F

=

759.6 kHz

o

Select:

Choose Rsns21=8.45 KΩ.

F_Z1= 0.5× F_{Z 2}= 6.6 kHz and

31

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IR3892

V













out(PGood _ TH )



Rsns22 =

−1 × Rsns21

(37)

0.85×VREF

Rsns22 = 11.83 kΩ; Select 11.8 kΩ,

The typical over-voltage threshold is calculated below

for channel 2. With above values for Rsns22 and

Rsns21, OVP trip point (Vout__OVP) is

(

Rsns21+ Rsns22

Rsns22

)

(38)

Vout_{_ OVP}= VREF ×1.2×

Vout__OVP= 1.44 V

32

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IR3892

APPLICATION DIAGRAM

INTERNALLY BIASED SINGLE RAIL

Vin

Cpvin1

330 uF

Cpvin2

4 x 10 uF

Cpvin3

2 x 0.1 uF

Cvcc

2.2 uF

Cvin

1 uF

Rpg1

49.9 K

Rpg2

49.9 K

Ren12

49.9 K

Ren22

49.9 K

PG1

PGood1

EN1

PGood2

EN2

PG2

Boot1

Boot2

Ren11

7.5 K

Ren21

7.5 K

Cboot1

0.1 uF

Cboot2

0.1 uF

L0

1.0 uH

L1

SW2

SW1

Vo1

Vo2

1.0 uH

Rbd2

20

Rbd1

20

Comp2

Comp1

Co1

Cout1

4 x 22 uF

Cout2

4 x 22 uF

Co2

0.1 uF

IR3892

0.1 uF

Cc22

Cc12

4.7 nF

3.6 nF

Rsns12

11.8 K

Cc13

100 pF

Cc23

82 pF

Rsns22

11.8 K

Cc21

1000 pF

Cc11

1000 pF

Rc12

5.62 K

Rc22

6.65 K

Rfb12

11.8 K

Rc11

210

Rc21

210

Rfb22

11.8 K

FB1

Comp2

Vsns2

Vsns1

Rfb11

4.53 K

Rfb21

8.45 K

Rsns21

8.45 K

Rsns11

4.53 K

Rt

39.2 K

Figure 29: Application circuit for 12V to 1.8V and 1.2V, 6A Point of Load Converter Using the Internal LDO

33

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IR3892

Suggested Bill of Material for application circuit 12V to 1.8V and 1.2V

Part Reference Qty

Value

330uF

10uF

1.0uF

2.2uF

Description

Manufacturer

Panasonic

TDK

Part Number

EEV-FK1E331P

C3216X5R1E106M

GRM188R61E105KA12D

C1608X5R1C225M

Cpvin1

Cpvin2

Cvin

1

4

1

SMD, electrolytic, 25V, 20%

1206, 25V, X5R, 10%

0603, 25V, X5R, 10%

0603, 16V, X5R, 20%

Murata

TDK

Cvcc

Co1 Co2

Cboot1

6

0.1uF

0603, 25V, X7R, 10%

Murata

GRM188R71E104KA01D

Cboot2 Cpvin3

Cc11 Cc21

Cc12

2

1

8

1000pF

4.7nF

100pF

3.6nF

82pF

0603, 50V, X7R, 10%

0603, 50V, NPO, 5%

0805, 6.3V X5R, 20%

Murata

TDK

GRM188R71H102KA01D

GRM188R71H472KA01D

GRM1885C1H101JA01D

GRM1885C1H362JA01D

GRM1885C1H820JA01D

C2012X5R0J226M

Cc13

Cc22

Cc23

Cout1 Cout2

22uF

SMT 6.5x7x5mm,

DCR=4.7mΩ

Thick Film, 0603, 1/10W, 1%

L0 L1

2

4

1.0uH

20

TDK

SPM6550T-1R0M100A

ERJ-3EKF20R0V

Rbd1 Rbd2

Ren12 Ren22

Rpg1 Rpg2

Panasonic

49.9K

Thick Film, 0603, 1/10W, 1%

ERJ-3EKF4992V

Ren11 Ren21

Rc11 Rc21

Rc12

2

1

2

7.5K

210

5.62K

6.65K

4.53K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF7501V

ERJ-3EKF2100V

ERJ-3EKF5621V

ERJ-3EKF6651V

ERJ-3EKF4531V

Rc22

Rfb11 Rsns11

Rfb12 Rsns12

Rfb22 Rsns22

Rfb21 Rsns21

Rt

4

11.8K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF1182V

2

1

8.45K

39.2K

Thick Film, 0603, 1/10W, 1%

Panasonic

International

Rectifier

ERJ-3EKF8451V

ERJ-3EKF3922V

U1

1

IR3892

PQFN 5x6mm

IR3892MPBF

34

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IR3892

EXTERNALLY BIASED DUAL RAIL

PVin

Vin

Cpvin1

330 uF

Cpvin2

4 x 10 uF

Cpvin3

2 x 0.1 uF

Cvcc

2.2 uF

Cvin

1 uF

Rpg1

49.9 K

Rpg2

49.9 K

Ren12

49.9 K

Ren22

49.9 K

PG1

PGood1

EN1

PGood2

EN2

PG2

Boot1

Boot2

Ren11

7.5 K

Ren21

7.5 K

Cboot1

0.1 uF

Cboot2

0.1 uF

L0

1.0 uH

L1

SW2

SW1

Vo1

Vo2

1.0 uH

Rbd2

20

Rbd1

20

Comp2

Comp1

Co1

Cout1

4 x 22 uF

Cout2

4 x 22 uF

Co2

0.1 uF

IR3892

0.1 uF

Cc22

Cc12

10 nF

8.2 nF

Rsns12

11.8 K

Cc13

220 pF

Cc23

180 pF

Rsns22

11.8 K

Cc21

1000 pF

Cc11

1000 pF

Rc12

2.43 K

Rc22

2.94 K

Rfb12

11.8 K

Rc11

210

Rc21

210

Rfb22

11.8 K

FB1

Comp2

Vsns2

Vsns1

Rfb11

4.53 K

Rfb21

8.45 K

Rsns21

8.45 K

Rsns11

4.53 K

Rt

39.2 K

Figure 30: Application circuit for a 12V to 1.8V and 1.2V, 4A Point of Load Converter using external 5V VCC

35

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May 29, 2014

IR3892

Suggested Bill of Material for application circuit 12V to 1.8V and 1.2V using external 5V VCC

Part Reference Qty

Value

330uF

10uF

1.0uF

2.2uF

Description

SMD, electrolytic, 25V, 20%

Manufacturer

Panasonic

TDK

Part Number

Cpvin1

1

4

1

EEV-FK1E331P

C3216X5R1E106M

GRM188R61E105KA12D

C1608X5R1C225M

Cpvin2

1206, 25V, X5R, 10%

0603, 25V, X5R, 10%

0603, 16V, X5R, 20%

Cvin

Murata

TDK

Cvcc

Cpvin3 Cboot1

Cboot2 Co1

Co2

6

0.1uF

0603, 25V, X7R, 10%

Murata

GRM188R71E104KA01D

Cc11 Cc21

Cc12

2

1

8

1000pF

10nF

220pF

8.2nF

180pF

22uF

0603, 50V, X7R, 10%

0603, 50V, NPO, 5%

0603, 50V, X7R, 10%

0603, 50V, NPO, 5%

Murata

TDK

GRM188R71H102KA01D

GRM188R71H103KA01D

GRM1885C1H221JA01D

GRM188R71H822KA01D

GRM1885C1H181JA01D

C2012X5R0J226M

Cc13

Cc22

Cc23

Cout1 Cout2

0805, 6.3V X5R, 20%

SMT 6.5x7x5mm,

L0 L1

2

1.0uH

TDK

SPM6550T-1R0M100A

DCR=4.7mΩ

Rbd1 Rbd2

Rc11 Rc21

Rc12

Rc22

Ren11 Ren21

2

1

2

20

210

2.43K

2.94K

7.5K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF20R0V

ERJ-3EKF2100V

ERJ-3EKF2431V

ERJ-3EKF2941V

ERJ-3EKF7501V

Ren12 Ren22

Rpg1 Rpg2

Rfb11 Rsns11

Rfb12 Rsns12

Rfb22 Rsns22

4

2

4

49.9K

4.53K

11.8K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF4992V

ERJ-3EKF4531V

ERJ-3EKF1182V

Rfb21 Rsns21

Rt

2

1

8.45K

39.2K

Thick Film, 0603, 1/10W, 1%

Panasonic

International

Rectifier

ERJ-3EKF8451V

ERJ-3EKF3922V

U1

1

IR3892

PQFN 5x6mm

IR3892MPBF

36

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May 29, 2014

IR3892

EXTERNALLY BIASED SINGLE RAIL

Vin

Cpvin1

330 uF

Cpvin2

8 x 10 uF

Cpvin3

2 x 0.1 uF

Cvcc

2.2 uF

Cvin

1 uF

Rpg1

49.9 K

Rpg2

49.9 K

Ren12

41.2 K

Ren22

41.2 K

PG1

PGood1

EN1

PGood2

EN2

PG2

Boot1

Boot2

Ren11

21 K

Ren21

21 K

Cboot1

0.1 uF

Cboot2

0.1 uF

L0

1.0 uH

L1

SW2

SW1

Vo1

Vo2

1.0 uH

Rbd2

20

Rbd1

20

Comp2

Comp1

Co1

Cout1

4 x 22 uF

Cout2

4 x 22 uF

Co2

IR3892

0.1 uF

Cc22

Cc12

3.9 nF

Rsns12

11.8 K

Cc13

91 pF

Cc23

91 pF

Rsns22

11.8 K

Cc21

1000 pF

Cc11

1000 pF

Rc12

5.62 K

Rc22

5.62 K

Rfb12

11.8 K

Rc11

210

Rc21

210

Rfb22

11.8 K

FB1

Comp2

Vsns2

Vsns1

Rfb11

4.53 K

Rfb21

8.45 K

Rsns21

8.45 K

Rsns11

4.53 K

Rt

39.2 K

Figure 31: Application circuit for a 5V to 1.8V and 1.2V, 4A Point of Load Converter

37

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May 29, 2014

IR3892

Suggested bill of material for application circuit 5V to 1.8V and 1.2V

Part Reference Qty

Value

Description

Manufacturer

Part Number

Cpvin1

Cpvin2

Cvin

1

8

1

330uF

SMD, electrolytic, 25V, 20%

Panasonic

EEV-FK1E331P

C3216X5R1E106M

GRM188R61E105KA12D

C1608X5R1C225M

10uF

1.0uF

2.2uF

1206, 25V, X5R, 10%

0603, 25V, X5R, 10%

0603, 16V, X5R, 20%

TDK

Murata

TDK

Cvcc

Cpvin3 Cboot1

Cboot2 Co1

Co2

6

0.1uF

0603, 25V, X7R, 10%

Murata

GRM188R71E104KA01D

Cc11 Cc21

Cc12 Cc22

Cc13 Cc23

Cout1 Cout2

2

8

1000pF

3.9nF

91pF

0603, 50V, X7R, 10%

0603, 50V, NPO, 5%

0805, 6.3V X5R, 20%

Murata

TDK

GRM188R71H102KA01D

GRM188R71H392KA01D

GRM1885C1H910JA01D

C2012X5R0J226M

22uF

SMT 6.5x7x5mm,

L0 L1

2

1.0uH

TDK

SPM6550T-1R0M100A

DCR=4.7mΩ

Rbd1 Rbd2

Rc11 Rc21

Rc12 Rc22

Ren11 Ren21

Ren12 Ren22

Rfb11 Rsns11

2

20

210

5.62K

21K

41.2K

4.53K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF20R0V

ERJ-3EKF2100V

ERJ-3EKF5621V

ERJ-3EKF2102V

ERJ-3EKF4122V

ERJ-3EKF4531V

Rfb12 Rsns12

Rfb22 Rsns22

4

11.8K

Thick Film, 0603, 1/10W, 1%

Panasonic

ERJ-3EKF1182V

Rfb21 Rsns21

Rpg1 Rpg2

Rt

2

1

8.45K

49.9K

39.2K

Thick Film, 0603, 1/10W, 1%

Panasonic

International

Rectifier

ERJ-3EKF8451V

ERJ-3EKF4992V

ERJ-3EKF3922V

U1

1

IR3892

PQFN 5x6mm

IR3892MPBF

38

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IR3892

TYPICAL OPERATING WAVEFORMS

Vin=PVin=12V, Vo1=1.8V, Iout1=0-6A, Vo2=1.2V, Iout1=0-6A, Fs=600kHz, Room Temperature, No air flow

Figure 32: Startup with full load

CH1:Vout1, Ch2:Vout2, Ch3:Vin, CH4:Vcc

Figure 33: PGood signals at Startup with full load

CH1:Vout1, Ch2:Vout2, Ch3:PGood1, CH4:PGood2

Figure 34: Channel 1 Startup with Pre-Bias, 1.52V

CH1:Vout1, Ch3:PGood1, Ch4:Enable1

Figure 35: Channel 2 Startup with Pre-Bias, 1.05V

CH2: Vout2, Ch2: PGood2 , Ch4:Enable2

Figure 36: Inductor Switch Nodes at full load

CH1:SW1, Ch2:SW2

Figure 37: Output Voltage Ripples at full load

CH1:Vout1, Ch2:Vout2

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IR3892

TYPICAL OPERATING WAVEFORMS

Vin=PVin=12V, Vo1=1.8V, Iout1=0-6A, Vo2=1.2V, Iout1=0-6A, Fs=600kHz, Room Temperature, No air flow

Figure 38: Vout1 Transient Response, 4.2A to 6A step at 2.5A/µSec

CH1:Vout1, CH2=Vout2, CH4:Iout1

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IR3892

TYPICAL OPERATING WAVEFORMS

Vin=PVin=12V, Vo1=1.8V, Iout1=0-6A, Vo2=1.2V, Iout1=0-6A, Fs=600kHz, Room Temperature, No air flow

Figure 39: Vout2 Transient Response, 4.2A to 6A step at 2.5A/µSec

CH1:Vout1, CH2=Vout2, CH4:Iout2

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IR3892

TYPICAL OPERATING WAVEFORMS

Vin=PVin=12V, Vo1=1.8V, Iout1=0-6A, Vo2=1.2V, Iout1=0-6A, Fs=600kHz, Room Temperature, No air flow

Figure 40: CH1 Bode Plot with 6A load, CH2 disabled.

Fo = 96.3 kHz, Phase Margin = 56.2 Degrees

Figure 41: CH2 Bode Plot with 6A load, CH1 disabled.

Fo = 97 kHz, Phase Margin = 54 Degrees

42

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IR3892

LAYOUT RECOMMENDATIONS

The layout is very important when designing high

frequency switching converters. Layout will affect

noise pickup and can cause a good design to perform

with less than expected results.

pins. It is important to place the feedback components

including feedback resistors and compensation

components close to Fb and Comp pins.

In a multilayer PCB use one layer as a power ground

plane and have a control circuit ground (analog

ground), to which all signals are referenced. The goal

is to localize the high current path to a separate loop

that does not interfere with the more sensitive analog

control function. These two grounds must be

connected together on the PC board layout at a single

point. It is recommended to place all the

compensation parts over the analog ground plane on

top layer.

Make the connections for the power components on

the top layer with wide, copper filled areas or

polygons. In general, it is desirable to make proper

use of power planes and polygons for power

distribution and heat dissipation.

The inductor, input capacitors, output capacitors and

the IR3892 should be as close to each other as

possible. This helps to reduce the EMI radiated by the

power traces due to the high switching currents

through them. Place the input capacitor directly at the

PVin pin of IR3892.

The Power QFN is a thermally enhanced package.

Based on thermal performance it is recommended to

use at least a 4-layers PCB. To effectively remove

heat from the device the exposed pad should be

connected to the ground plane using vias. Figure

42a-d illustrates the implementation of the layout

guidelines outlined above, on the IRDC3892 4-layer

demo board.

The feedback part of the system should be kept away

from the inductor and other noise sources.

The critical bypass components such as capacitors for

PVin and VCC should be close to their respective

- Ground path length

between VIN- and VOUT1-

should be minimized with

maximum copper

Vout1

- Compensation parts

should be placed

as close as possible

to the Comp pins

- Bypass caps should

be placed as close as

possible to their

PVin

AGND

- Single point connection

between AGND &

PGND, should be placed

near the part and kept

away from noise sources

- SW node copper is

kept only at the top

layer to minimize the

switching noise

PGND

- Ground path length

between VIN- and

VOUT2- should be

minimized with

Vout2

maximum copper

Figure 42a: IRDC3892 Demo board Layout Considerations – Top Layer

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IR3892

PGND

Figure 42b: IRDC3892 Demo board Layout Considerations – Bottom Layer

Feedback and Vsns trace

routing should be kept

away from noise sources

PGND

AGND

Figure 42c: IRDC3892 Demo board Layout Considerations – Mid Layer 1

Vin

PGND

Figure 42d: IRDC3892 Demo board Layout Considerations – Mid Layer 2

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IR3892

PCB METAL AND COMPONENT PLACEMENT

Evaluations have shown that the best overall

performance is achieved using the substrate/PCB

layout as shown in following figures. PQFN devices

should be placed to an accuracy of 0.050mm on

both X and Y axes. Self-centering behavior is highly

dependent on solders and processes, and

experiments should be run to confirm the limits of

self-centering on specific processes. For further

information, please refer to “SupIRBuck^®Multi-Chip

Module (MCM) Power Quad Flat No-Lead (PQFN)

Board Mounting Application Note.” (AN1132)

Figure 43: PCB Pad Sizes Detail 1

(Dimensions in mm)

Figure 44: PCB Pad Sizes Detail 2

(Dimensions in mm)

Figure 45: PCB Metal Pad Spacing (Dimensions in mm)

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IR3892

SOLDER RESIST

•

IR recommends that the larger Power or Land

Area pads are Solder Mask Defined (SMD).

This allows the underlying Copper traces to be

as large as possible, which helps in terms of

current carrying capability and device cooling

capability.

•

However, for the smaller Signal type leads

around the edge of the device, IR recommends

that these are Non Solder Mask Defined or

Copper Defined.

When using NSMD pads, the Solder Resist

Window should be larger than the Copper Pad

by at least 0.025mm on each edge, (i.e.

0.05mm in X & Y), in order to accommodate any

layer to layer misalignment.

•

When using SMD pads, the underlying copper

traces should be at least 0.05mm larger (on

each edge) than the Solder Mask window, in

order to accommodate any layer to layer

misalignment. (i.e. 0.1mm in X & Y).

•

Ensure that the solder resist in-between the

smaller signal lead areas are at least 0.15mm

wide, due to the high x/y aspect ratio of the

solder mask strip.

Figure 46: SMD Pad Sizes Detail 1 (Dimensions in mm)

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IR3892

Figure 47: SMD Pad Sizes Detail 2 (Dimensions in mm)

Figure 48: SMD Pad Spacing (Dimensions in mm)

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IR3892

STENCIL DESIGN

• Stencils for PQFN can be used with thicknesses of

0.100-0.250mm (0.004-0.010"). Stencils thinner

than 0.100mm are unsuitable because they

deposit insufficient solder paste to make good

solder joints with the ground pad; high

reductions sometimes create similar problems.

Stencils in the range of 0.125mm-0.200mm

(0.005-0.008"), with suitable reductions, give the

best results.

• Evaluations have shown that the best overall

performance is achieved using the stencil design

shown in following figure. This design is for a

stencil thickness of 0.127mm (0.005"). The

reduction should be adjusted for stencils of other

thicknesses.

Figure 49: Stencil Pad Sizes (Dimensions in mm)

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IR3892

Figure 50: Stencil Pad Spacing Detail 1 (Dimensions in mm)

Figure 51: Stencil Pad Spacing Detail 2 (Dimensions in mm)

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IR3892

MARKING INFORMATION

Figure 52: Marking Information

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IR3892

PACKAGING INFORMATION

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IR3892

ENVIRONMENTAL QUALIFICATIONS

Industrial

Qualification Level

Moisture Sensitivity Level

5mm x 6mm PQFN

MSL2

Class A

<200V

Machine Model

(JESD22-A115A)

Class 1C

Human Body Model

(JESD22-A114F)

ESD

≥1000V to <2000V

Class III

Charged Device Model

(JESD22-C101D)

≥500V to ≤1000V

Yes

RoHS Compliant

Data and specifications subject to change without notice.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.

www.irf.com

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型号：	IR3892M
厂家：	Infineon
描述：	Single-Input Voltage, Synchronous Buck Regulator
文件：	总52页 (文件大小：3350K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IR3892M [INFINEON]

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