IR3899AMTRPBF [INFINEON]
9 A 单输出同步降压调节器;
| 型号： | IR3899AMTRPBF |
| 厂家： | 
Infineon |
| 描述： | 9 A 单输出同步降压调节器 调节器 |
| 文件： | 总38页 (文件大小：1089K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IR3899A
IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Features
•
•
•
•
•
•
•
•
•
•
•
•
Single 4.3 V to 17 V application
Precision Reference Voltage (0.6 V +/-0.5%)
Enhanced Fast COT engine stable with Ceramic Output Capacitors and No External Compensation
Optional Forced Continuous Conduction Mode or Diode Emulation for Enhanced Light Load Efficiency
Programmable Switching Frequency from 600 kHz to 2 MHz
Enable input with Voltage Monitoring Capability & Power Good Output
Monotonic Start-Up with 2 ms soft start time & Enhanced Pre-Bias Start up
Thermally compensated Internal Over Current Protection with Two Selectable Settings
Thermal Shut Down
Operating Junction Temp: -40 oC < Tj < 125 oC
Small Size: 4 mm x 5 mm PQFN
Halogen-free and RoHS Compliant
Potential applications
•
•
•
•
Server Applications
Storage Applications
Telecom & Datacom Applications
Distributed Point of Load Power Architectures
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC47/20/22
Description
The IR3899A is an easy-to-use, fully integrated dc - dc Buck regulator. The onboard PWM controller and MOSFETs
with integrated bootstrap diode make IR3899A a small footprint solution, providing high-efficiency power
delivery. Furthermore, it uses a fast Constant On-Time (COT) control scheme, which simplifies design efforts and
provides fast control response.
The IR3899A has an internal low dropout voltage regulator, allowing operation with a single supply. The IR3899A
is a versatile regulator, offering programmable switching frequency from 600 kHz to 2 MHz, two selectable current
limits, Forced Continuous Conduction Mode (FCCM) and Diode Emulation Mode (DEM) operation.
It also features important protection functions, such as pre-bias start-up, thermally compensated current limits,
over voltage and under voltage protection, and thermal shutdown to give required system level security in the
event of fault conditions.
Final Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1 of 38
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Ordering information
Table of contents
Features ........................................................................................................................................ 1
Potential applications..................................................................................................................... 1
Product validation.......................................................................................................................... 1
Description .................................................................................................................................... 1
Table of contents............................................................................................................................ 2
1
2
3
4
5
Ordering information ............................................................................................................. 4
Functional block diagram........................................................................................................ 5
Typical application diagram .................................................................................................... 6
Pin descriptions ..................................................................................................................... 7
Absolute maximum ratings ..................................................................................................... 8
6
6.1
Thermal characteristics .......................................................................................................... 9
Thermal Characteristics..........................................................................................................................9
7
7.1
7.2
Electrical specifications .........................................................................................................10
Recommended operating conditions...................................................................................................10
Electrical characteristics.......................................................................................................................11
8
8.1
Typical efficiency and power loss curves..................................................................................13
PVin = Vin = 12 V, Fsw = 600 kHz ................................................................................................................13
9
Thermal de-rating cuves ........................................................................................................14
RDS(ON) of MOSFET over temperature .........................................................................................15
Typical operating characteristics (-40 °C ≤ Tj ≤ +ꢀꢁꢂ °C)..............................................................16
10
11
12
Theory of operation...............................................................................................................18
Fast Constant On-Time Control ............................................................................................................18
Enable ....................................................................................................................................................18
FCCM and DEM Operation.....................................................................................................................19
Pseudo-Constant Switching Frequency ...............................................................................................19
Soft-start................................................................................................................................................20
Pre-bias Start-up ...................................................................................................................................20
Internal Low – Dropout (LDO) Regulator..............................................................................................20
Over Current Protection (OCP) .............................................................................................................21
Under Voltage Protection (UVP) ...........................................................................................................22
Over Voltage Protection (OVP)..............................................................................................................22
Over Temperature Protection (OTP) ....................................................................................................23
Power Good (Pgood) Output ................................................................................................................23
Minimum ON – Time and Minimum OFF – Time...................................................................................24
Selection of Feedforward Capacitor and Feedback Resistors.............................................................24
Resistors for Configuration Pins ...........................................................................................................25
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
12.10
12.11
12.12
12.13
12.14
12.15
13
Design example.....................................................................................................................26
Enabling the IR3899A ............................................................................................................................26
Programming the Switching Frequency and Operation Mode............................................................26
Selecting Input Capacitors....................................................................................................................26
Inductor Selection.................................................................................................................................27
Output Capacitor Selection ..................................................................................................................27
Output Voltage Programming...............................................................................................................28
Feedforward Capacitor .........................................................................................................................28
13.1
13.2
13.3
13.4
13.5
13.6
13.7
Final Datasheet
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Ordering information
13.8
13.9
Bootstrap Capacitor..............................................................................................................................28
Vin and VCC/LDO bypass Capacitor......................................................................................................28
14
14.1
14.2
Application information.........................................................................................................29
Application Diagram..............................................................................................................................29
Typical Operating Waveforms...............................................................................................................29
15
15.1
15.2
Layout Recommendations......................................................................................................32
Solder mask...........................................................................................................................................32
Stencil design ........................................................................................................................................33
16
16.1
16.2
Package ...............................................................................................................................35
Marking Information .............................................................................................................................35
Dimensions............................................................................................................................................35
17
Environmental qualifications .................................................................................................37
Revision history.............................................................................................................................38
Final Datasheet
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Ordering information
1
Ordering information
1.
Ordering Information
Base Part Number
IR3899AMTRPBF
Package Type
Standard Pack Form and Qty
Orderable Part Number
PQFN 4 mm x 5 mm
Tape and Reel
4000
IR3899AMTRPBFXUMA1
IR3899AMTRPBF
A1
Designator
Packing type
Tape & Reel
Dry
Moisture
protection packing
UM
Packing size
330 mm
Halogen Free
RoHS compliant
Total lead free
Yes
Yes
Yes
X
PGND
11
13
12
SW
PVIN
BOOT 14
VCC/LDO
VIN
10
17
15
EN
9
8
AGND
16
VSNS
NC
1
2
3
4
5
6
7
Figure 1 Package Top View
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Functional block diagram
2
Functional block diagram
VCC/LDO
AGND
PGood
Vin
AGND
PVin
POR
UVP
UVP OTP
OVP
+
-
Threshold
VCC/LDO
LDO
Fault
En
AGND
BOOT
PVin
+
-
OVP
Threshold
Turn-on Delay
PGood
Prebias
Fault
Q
Q
S
R
HDrVin
HDrv
+
-
PGood
Threshold
Hysteresis
VSNS
En
POR
POR
+
-
VCC
4.0 V
Hiccup
OVP
GATE
DRIVE
LOGIC
SW
VCC/LDO
OTP
+
-
Fault
1.2 V
LDrVin
LDrv
PWM
PWM
COMP
SOFT
START
SS
+
-
+
ADAPTIVE
ON-TIME
GENERATOR
SET
ZC
PGND
Zero Cross
DETECTION
SW
PGND
FB
RAMP
GENERATOR
OCP
Floor
GENERATOR
+
Hiccup
-
+
S
Q
UVP
R
VREF
AGND
SW
TON/MODE
ILIM
20 ms
Delay
OCP Limit
Figure 2 Block diagram
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Typical application diagram
3
Typical application diagram
PVin
Enable
PVin
Vin
En
BOOT
SW
VCC/LDO
Vo
PGood
PGood
ILIM
IR3899A
Float or
GND
RFB1
RFB2
Cff
VSNS
FB
TON/MODE
NC
PGND
AGND
Figure 3 IR3899A basic application circuit
Final Datasheet
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Pin descriptions
4
Pin descriptions
Note:
I = Input, O = Output
Pin#
Pin Name
I/O
Type
Pin Description
Output voltage feedback pin. Connect this pin to the
output of the regulator via a resistor divider to set the
output voltage.
1
FB
I
Analog
Shorting to GND or floating the pin sets the Over Current
Protection (OCP) limit. Two User selectable OCP limits are
available.
2
ILIM
NC
I
Analog
This pin can be left floating.
3, 6, 16
4, 17
-
No connect Note: Pin 6 is internally connected and should either be left
floating or can be connected to VCC/LDO.
Signal ground for the internal reference voltage and
control circuitry. AGND and PGND are not internally
connected. AGND and PGND must be connected on the
AGND
-
Ground
PCB with a single ground connection.
Multi-function pin. This pin sets the switching frequency to
5
7
8
TON/MODE
PGood
I
O
I
Analog
Analog
Analog
1 of 8 settings and sets the mode of operation to FCCM or
DEM by connecting a resistor to ground.
Power Good status output pin is open drain. Connect a pull
up resistor from this pin to VCC/LDO or to an external bias
voltage, e.g., 3.3 V.
Sense pin for over voltage protection and PGood. Tie this
pin to Vout using a resistor divider. Alternatively, tie this pin
to the FB pin directly.
VSNS
Vin is the input voltage for the Internal LDO and it should
always be connected to PVin; also forms input to the
feedforward block. A 4.7 µF capacitor should be connected
between this pin and PGND.
Output of the internal LDO. A ceramic capacitor valued
between 2.2 µF and 10 µF is recommended for use between
VCC/LDO and the Power ground (PGND).
Power ground. This pin should be connected to the
systemꢀs power ground plane. Bypass capacitors between
PVin and PGND should be connected very close to these
pins.
9
Vin
I
I
-
Power
Power
Ground
10
11
VCC/LDO
PGND
12
13
SW
O
I
Power
Power
Switch node. This pin is connected to the output inductor.
Input voltage for power stage. Bypass capacitors between
PVin and PGND should be connected very close to these
pins.
PVin
Supply voltage for the high side driver. Connect this pin to
the SW pin through a bootstrap capacitor.
14
15
BOOT
En
I
I
Analog
Analog
Enable pin to turn the IC on and off.
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Absolute maximum ratings
5 Absolute maximum ratings
Absolute maximum ratings
Description
Min
Max
Unit
Conditions
PVin, Vin, En to PGND
-0.3
25
V
Note 1
-0.3 V(dc),
below -5 V for 5 ns
PVin to SW
25
6
V
V
V
VCC/LDO to PGND
BOOT to PGND
-0.3
Note 1
Note 1
-0.3 V(dc),
below -0.3 V for 5 ns
-0.3 (dc),
29
SW to PGND
BOOT to SW
ILIM, FB, PGood, TON/MODE and
VSNS to AGND
25
6
V
V
V
Note 1
below -5 V for 5 ns
-0.3
-0.3
6
Note 1
PGND to AGND
-0.3
-55
-40
0.3
150
150
V
Storage Temperature Range
Junction Temperature Range
°C
°C
Note:
1. PGND and AGND pins are connected together
Attention:
Stresses beyond these listed under ꢀAbsolute Maximum Ratingsꢁ may cause permanent
damage to the device. These are stress ratings only and functional operation of the device at
these or any other conditions beyond those indicated in the operational sections of the
specifications are not implied.
Final Datasheet
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Thermal characteristics
6
Thermal characteristics
6.1
Thermal Characteristics
Description
Symbol
Values
32 °C/W
2 °C/W
Test Conditions
Junction to Ambient Thermal Resistance
Junction to PCB Thermal Resistance
θJA
θJC-PCB
Final Datasheet
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Electrical specifications
7
Electrical specifications
7.1
Recommended operating conditions
Description
Min
Max
17
Unit
V
Note
Note 2, Note 3 & 6
Note 4, Note 5
Note 5
PVin Voltage Range
4.5
0.6
Typical Output Voltage Range
Continuous Output Current Range
Typical Switching Frequency
Operating Junction Temperature
6
V
9
A
600
-40
2000
125
kHz
°C
Note 6
Note:
2. A common practice is to have 20% margin on the maximum SW node voltage in the design. A 2Ω resistor in series
with the BOOT pin is recommended for PVin ꢀ ꢁꢂ.ꢃ V to ensure the maximum SW node spike voltage does not
exceed 20 V. Alternatively, an RC snubber can be used at the SW node to reduce the SW node spike.
3. For single-rail applications with PVin = Vin = 4.3 V-5.4 V, the internal LDO may enter dropout mode. OCP limits can
be reduced due to the lower VCC voltage.
4. The maximum output voltage is limited by the minimum off-time. Please refer to Section 12.13 for details. Also
note that OCP limit may be degraded when off-time is close to the minimum off-time.
5. Maximum output current capability can be reduced at elevated ambient temperatures. Lower VCC voltage can
result in higher RDS (ON) and therefore require more thermal derating.
6. The maximum LDO output current must be limited to 50 mA or less for operations requiring the full operating
temperature range of -40 °C ꢀ TJ ꢀ 125 °C. Thermal derating may be needed for operation at elevated ambient
temperatures to ensure the junction temperature remains within the recommended operating range.
Final Datasheet
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Electrical specifications
7.2
Electrical characteristics
Note:
Unless otherwise specified, the specifications apply over ꢄ.ꢅ V ꢆ Vin = PVin ꢆ ꢁ7 V, ꢇ °C < TJ < 125 °C.
Typical values are specified at Ta = 25 °C.
Parameter
Symbol
Conditions
Min Typ Max Unit
Power Stage
Top Switch
RDS (on)_Top
RDS (on)_Bot
VBOOT – VSW = 5.0 V, Tj = 25 oC
VCC = 5.0 V, Tj = 25 oC
I(Boot) = 25 mA
21
mΩ
9
Bottom Switch
Bootstrap Forward Voltage
370
600
300
300
mV
En = 0 V
SW float voltage
Dead Band Time
VSW
Tdb
mV
En = high, No Switching
SW node rising edge, Note 7
SW node falling edge, Note 7
10
10
ns
ns
Supply Current
Vin Supply Current (standby)
Vin Supply Current (static)
Iin (Standby)
Iin (Static)
En = Low, No Switching
En = 2 V, No Switching
4
10
4
µA
2.3
mA
Soft Start
Soft Start time
1.4
2
3
ms
SS time
VFB
Feedback Voltage
Feedback Voltage
0.6
V
0 °C < Tj < 85 °C, Note 8
-40 °C < Tj < 125 °C, Note 8
VFB = 0.6 V, Tj = 25 C
-0.5
-1
+0.5
1
Accuracy
%
VFB Input Current
-0.15
0
+0.15
A
IVFB
On-Time Timer Control
Vin = 12 V, Vo = 1 V,
TON/MODE = ꢁ kΩ, ꢂꢁ.ꢃ kΩ, Note 9
Vin = 12 V, Vo = 1 V,
TON/MODE = ꢂ.ꢃ kΩ, ꢂꢄ.ꢂ kΩ, Note 9
Vin = 12 V, Vo =1 V,
TON/MODE = ꢄ.ꢅꢆ kΩ, ꢂꢅ kΩ, Note 9
Vin = 12 V, Vo = 1 V,
TON/MODE = ꢇ.ꢅꢈ kΩ, ꢂꢉ.ꢄ kΩ, Note 9
152
114
91.5
77
Vin = 12 V, Vo = 1 V,
TON/MODE = ꢅ.ꢃꢇ kΩ, ꢂꢈ.ꢊ kΩ, Note 9
Vin = 12 V, Vo = 1 V,
TON/MODE = ꢃ.ꢊꢉ kΩ, ꢄꢂ.ꢃ kΩ, Note 9
Vin = 12 V, Vo = 1 V,
TON/MODE = ꢊ.ꢇꢄ kΩ, ꢄꢅ.ꢆ kΩ, Note 9
On Time
66.5
58.5
52
ns
Ton
Vin = 12 V, Vo = 1 V,
TON/MODE = ꢈ.ꢈꢊ kΩ, ꢄꢈ.ꢊ kΩ, Note 9
47
Vin = 12 V, Vo = 1 V,
TON/MODE = Floating, Note 9
114
Minimum On-Time
Minimum Off-Time
Final Datasheet
Vin = 12 V, Vo = 0 V
Tj = 25 C, VFB = 0 V
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23
32
ns
ns
Ton (Min)
Toff (Min)
270
360
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Electrical specifications
Parameter
Symbol
Conditions
Min Typ Max Unit
VCC LDO Output
5.5 V ꢋ Vin ꢋ 17 V, when Icc = 50 mA,
Cload = 2.2 µF
Output Voltage
VCC
4.7
5.0
90
5.3
V
VCC Dropout
VCC_drop Vin = 4.3 V, Icc = 50 mA, Cload = 2.2 µF
Ishort 5.5 V ꢋ Vin ꢋ 17 V
300
mV
mA
Short Circuit Current
Under Voltage Lockout
VCC-Start Threshold
VCC-Stop Threshold
Enable-Start-Threshold
Enable-Stop-Threshold
Input Impedance
Vcc_UVLO_Start VCC Rising Trip Level
Vcc_UVLO_Stop VCC Falling Trip Level
En_UVLO_Start ramping up
En_UVLO_Stop ramping down
REN
3.8
3.6
4.0
3.8
4.2
4.0
V
1.14 1.2
0.9
1.36
1.06
V
1
500 1000 1500
k
Over Current Limit
Tj = 25 °C, VCC = 5.0 V, ILIM = GND
6.8
10
9.0
10.5
15
Current Limit Threshold
(Valley Current)
Ioc
A
Tj = 25 °C, VCC = 5.0 V, ILIM = Floating
12.7
Over Voltage Protection
VSNS Rising
115 121
110 115
5
125
120
OVP Trip Threshold
OVP_Vth
% Vref
µs
VSNS Falling, OVP hysteresis
OVP Protection Delay
Under Voltage Protection
UVP Trip Threshold
OVP_Tdly
UVP_Vth
UVP_Tdly
VSNS Falling
65
70
4
75 % Vref
UVP Protection Delay
Hiccup Blanking Time
Power Good
µs
Tblk_Hiccup
20
ms
Pgood Turn on Threshold
Pgood Turn off Threshold
Pgood Sink Current
VPG (upper)
VPG (lower)
IPG
VSNS Rising
85
80
91
84
5
95 % Vref
90 % Vref
mA
VSNS Falling
PGood = 0.5 V, En = 2 V
2.5
Pgood Voltage Low
VPG (low)
Vin = VCC = 0 V, Rpull-up = 50 kΩ to 3.3 V
VSNS Rising, see VPG (upper)
VSNS < VPG (lower) or VSNS > VPG (upper)
0.3
2.5
2
0.5
V
Pgood Turn on Delay
Pgood Comparator Delay
VPG (on)_Dly
VPG (comp)_Dly
ms
µs
1
3.5
1
Pgood Open Drain Leakage
Current
PGood = 3.3 V
µA
Thermal Shutdown
Thermal Shutdown
Hysteresis
Note 7
Note 7
140
20
°C
Note:
7. Guaranteed by construction and not tested in production.
8. Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in
production.
9. Ton is trimmed so that the target switching frequency is achieved at around 4 A load current.
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Typical efficiency and power loss curves
8
Typical efficiency and power loss curves
8.1
PVin = Vin = ꢀꢁ V, Fsw = ꢃꢄꢄ kHz
PVin = Vin = 12 V, VCC = Internal LDO, Io = 0 A - 9 A, Fsw = 600 kHz, Room Temperature, No Air Flow. Note that the
efficiency and power loss curves include losses of the IR3899A, inductor losses, losses of the input and output
capacitors, and PCB trace losses. The table below shows the inductors used for each of the output voltages in
the efficiency measurement.
Table 1
Inductors for PVin = Vin = 12 V, Fs = 600 kHz
Vout (V)
Lout (nH)
360 nH
P/N
DCR (m)
0.76
1.5
Size (mm)
1.0
1.2
1.8
3.3
5.0
CMLE104T-R36MS
CMLB104T-R47MS
CMLE104T-R68MS
CMLB104T-1R0MS
CMLB104T-1R0MS
11.15 x 10.0 x 3.8
11.15 x 10.0 x 3.8
11.15 x 10.0 x 3.8
11.15 x 10.0 x 3.8
11.15 x 10.0 x 3.8
470 nH
680 nH
1.6
1000 nH
1000 nH
3.3
3.3
PVin = Vin = 12 V, Fsw = 600 kHz - Internal LDO, Natural Convention, Ta = 25 °C
1.0V - DEM
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
1.0V - FCCM
1.2V - DEM
1.2V - FCCM
1.8V - DEM
1.8V - FCCM
3.3V - DEM
3.3V - FCCM
5.0V - DEM
5.0V - FCCM
0
1
2
3
4
5
5
6
7
8
9
Output current (A)
PVin = Vin = 12 V, Fsw = 600 kHz - Internal LDO, Natural Convention, Ta = 25 °C
1.0V - DEM
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
0.3
0.1
1.0V - FCCM
1.2V - DEM
1.2V - FCCM
1.8V - DEM
1.8V - FCCM
3.3V - DEM
3.3V - FCCM
5.0V - DEM
5.0V - FCCM
0
1
2
3
4
5
6
7
8
9
Output current (A)
Final Datasheet
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Thermal de-rating cuves
9
Thermal de-rating cuves
Measurement is done on IR3899A Evaluation board at 200LFM. The PCB is a 4-layer board with 1.8 oz. copper for
top and bottom layers and 2 oz. copper for the inner layers, FR4 material, size ꢄ.ꢄ” x ꢄ.ꢉ”.
PVin = Vin = 12 V, Vout = 1.2 V, Fsw = 800 kHz
10
9
8
7
6
5
4
3
2
1
0
25
25
25
30
30
30
35
40
45
50
55
60
65
70
75
75
75
80
80
80
85
85
85
Tambinet (°C)
PVin = Vin = 12 V, Vout = 3.3 V, Fsw = 800 kHz
10
9
8
7
6
5
4
3
2
1
0
35
40
45
50
55
60
65
70
Tambinet (°C)
PVin = Vin = 12 V, Vout = 5.0 V, Fsw = 800 kHz
10
9
8
7
6
5
4
3
2
1
0
35
40
45
50
55
60
65
70
Tambinet (°C)
Figure 4 Thermal derating curves, Pvin = 12 V, Vout = 1.2 V/3.3 V/5 V, fsw = 800 kHz, VCC = Internal LDO
Final Datasheet
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
RDS(ON) of MOSFET over temperature
10
RDSꢅONꢆ of MOSFET over temperature
RDS(ON) of Control MOSFET
35
30
25
20
15
10
5
Vcc = 5V
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
RDS(ON) of Synchronous MOSFET
16
14
12
10
8
6
Vcc = 5V
4
2
-40
-20
0
20
40
60
80
100
120
140
Temperature (°C)
Figure 5 RDS(ON) of MOSFETs over Junction Temperature
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Typical operating characteristics (-ꢇꢄ C ≤ Tj ≤ +ꢀꢁꢂ Cꢆ
11
Typical operating characteristics ꢅ-ꢇꢄ °C ≤ Tj ≤ +ꢀꢁꢂ °Cꢆ
Vin Standby Supply Current
Vin Static Supply Current
1.2
1
4
3.5
3
0.8
0.6
0.4
0.2
0
2.5
2
1.5
1
-40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
-40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
LDO Voltage at Vin = 5.5 V & 17 V, Icc = 50 mA
LDO Voltage Drop at Vin = 4.3 V, Icc = 50 mA
350
5.1
300
250
200
150
100
50
5.05
5
4.95
4.9
Vin = 5.5 V
Vin = 17 V
4.85
-40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
-40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
Enable_Start and Stop Thresholds
Vcc_UVLO Start and Stop Thresholds
1.3
1.25
1.2
4.2
4.1
4
1.15
1.1
3.9
3.8
3.7
3.6
1.05
1
0.95
0.9
En_Start
Vcc_UVLO_Start
Vcc_UVLO_Stop
En_Stop
0.85
-40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
-40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Typical operating characteristics (-ꢇꢄ C ≤ Tj ≤ +ꢀꢁꢂ Cꢆ
VFB
OVP Rise and Fall Thresholds
603
125
120
115
110
105
602
601
600
599
598
597
OVP_Rise
OVP_Fall
-40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
-40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
UVP_Threshold
PGood Rise and Fall Thresholds
74
72
70
68
66
64
62
92
90
88
86
84
82
80
78
PGood_Rise
PGood_Fall
-40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
-40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
OCP Limit (9 A) - 5 V Vcc
OCP Limit (12.7 A) - 5 V Vcc
12
11
10
9
15
14
13
12
11
10
9
8
7
6
5
OCP (9 A) - Typ
OCP (12.7 A) - Typ
4
-40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
-40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
Figure 6 Typical operating characteristics
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Theory of operation
12
Theory of operation
12.1
Fast Constant On-Time Control
The IR3899A features a proprietary Fast Constant On-Time (COT) Control, which can provide fast load transient
response, good output regulation and minimize design effort. Fast COT control compares the output voltage, Vo,
to a floor voltage combined with an internal ramp signal. When Vout drops below that signal, a PWM signal is
initiated to turn on the high-side FET for a fixed on-time. The floor voltage is generated from an internally-
compensated error amplifier, which compares Vout with a reference voltage. Compared to the traditional COT
control, Fast COT control significantly improves Vout regulation.
12.2
Enable
The EN pin controls the on/off state of the IR3899A. An internal Under Voltage Lock-Out (UVLO) circuit monitors
the EN voltage. When the EN voltage is above an internal threshold, the internal LDO starts to ramp up. When the
VCC/LDO voltage rises above the VCC_UVLO_Start threshold, the soft-start sequence starts. The EN pin can be
configured in three ways, as shown in Figure 7. With configuration 2, the Enable signal is derived from the Pvin
voltage by a resistor divider, REN1 and REN2. By selecting different divider ratios, users can program a UVLO
threshold for the bus voltage. This is a very desirable feature because it prevents the IR3899A from operating until
Pvin is higher than a desired voltage level. For some space-constrained designs, the EN pin can be directly
connected to Pvin without using the external resistor divider, as shown in Configuration 3. The EN pin should not
be left floating. A pull-down resistor in the range of tens of kilohms is recommended. Figure 8 illustrates the
corresponding start-up sequences with three EN configurations.
PVin
PVin
PVin
Vin
PVin
PVin
PVin
Vin
Vin
REN1
Vcc
Vcc
Vcc
En
IR3899A
En
En
IR3899A
IR3899A
REN2
ꢁ
ꢂꢃꢄ
En = ꢁ
× ꢆꢇꢈꢉ
ꢂꢃꢄ
En = an external logic signal
Configuration 1
Pvin = Vin = En
Configuration 3
+ꢁ
ꢂꢃꢅ
Configuration 2
Figure 7 Enable Configurations
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Theory of operation
Pvin= Vin=12 V
PVin=Vin=En=12V
Pvin = Vin = 12V
Vcc_ UVLO
Vcc
Vcc
Vcc
En Threshold
0V
Vcc_UVLO
Vcc_ UVLO
0V
0V
0V
0V
En = REN2/(REN1+REN2)*PVin
Fb
0V
En>1.2V
En Threshold
0V
Fb
Fb
0V
Pgood Turn-on
threshold
2.5ms
Pgood Turn-on
threshold
2.5ms
Pgood Turn-on
threshold
2.5ms
0V
0V
0V
0V
0V
0V
PGood
PGood
PGood
Pgood stays at logic low
Pgood stays at logic low
Pgood stays at logic low
ꢁ
ꢂꢃꢄ
En = an external logic signal
Configuration 1
En = ꢁ
× ꢆꢇꢈꢉ
ꢂꢃꢄ
Pvin = Vin = En
Configuration 3
+ꢁ
ꢂꢃꢅ
Configuration 2
Figure 8 Start-up sequence
12.3
FCCM and DEM Operation
The IR3899A offers two operation modes: Forced Continuous Conduction Mode (FCCM) and Diode Emulation
Mode (DEM). With FCCM, the IR3899A always operates as a synchronous buck converter with a pseudo-constant
switching frequency leading to small output voltage ripple. In DEM, the synchronous FET is turned off when the
inductor current is close to zero, reducing the switching frequency and improving efficiency at light load. At heavy
load, both FCCM and DEM operate in the same way. The operating mode can be selected with the TON/MODE
pin, as shown in Table 2. It should be noted that the selection of the operating mode cannot be changed on the
fly. To load a new TON/MODE configuration, EN or VCC voltage must be cycled.
12.4
Pseudo-Constant Switching Frequency
The IR3899A offers eight programmable switching frequencies, fsw, from 600 kHz to 2 MHz, by connecting an
external resistor from the TON/MODE pin to ground. Based on the selected fsw, the IR3899A generates the
corresponding on-time of the Control FET for a given PVin and Vo, as shown by the formula below.
ꢌꢍ
ꢎ
ꢊ
ꢋꢉ
=
×
ꢆꢌ
ꢏ
ꢐꢑ
ꢈꢉ
Where fsw is the desired switching frequency. During operation, the IR3899A monitors PVin and Vo, and can
automatically adjust the on-time to maintain the pre-selected fsw. As load current increases, the switching
frequency can increase to compensate for power losses.
Table 2 lists resistor values for the TON/MODE pin. In this table, E96 resistors with ±1% tolerance are used. To
load a new TON/MODE configuration, En or VCC voltage must be cycled.
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Theory of operation
Table 2 Configuration Resistors for TON/MODE Pin
TON/MODE Resistor ꢅkΩꢆ
Freq (kHz)
Mode
±1% Tolerance
0
600
800
1.5
2.49
1000
1200
1400
1600
1800
2000
600
3.48
FCCM
4.53
5.76
7.32
8.87
10.5
12.1
800
14
1000
1200
1400
1600
1800
2000
800
16.2
DEM
18.7
21.5
24.9
28.7
TON/MODE = Floating
FCCM
12.5
Soft-start
The IR3899A has an internal digital soft-start to control the output voltage rise and to limit the current surge at
start-up. To ensure a correct start-up, the soft-start sequence initiates when the En and VCC voltages rise above
their respective thresholds. The internal soft-start signal linearly rises from 0 V to 0.6 V in a defined time duration.
The soft-start time does not change with the output voltage. During soft-start, the IR3899A operates in DEM until
1 ms after the output voltage ramps above the Pgood turn-on threshold. The IR3899A has a fixed soft-start time
of 2 ms.
12.6
Pre-bias Start-up
The IR3899A is able to start up into a pre-charged output without causing oscillations and disturbances of the
output voltage. When the IR3899A starts up with a pre-biased output voltage, both control FET and Sync FET are
kept off until the internal soft-start signal exceeds the FB voltage.
12.7
Internal Low – Dropout ꢅLDOꢆ Regulator
The IR3899A has an integrated low-dropout LDO regulator providing the bias voltage for the internal circuitry. To
minimize standby current, the internal LDO is disabled when the EN voltage is pulled low. The Vin pin is the input
of the LDO. The IR3899A supports internal LDO with single rail operation, i.e., the Vin pin should always be
connected to the Pvin pin. Figure 9 illustrates the configuration of VCC/LDO, and the Vin pin.
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Theory of operation
PVin
4.7 uF
VIN
PVin
VCC/LDO
IR3899A
2.2 uF ~10 uF
PGND
Single rail operation with the internal LDO
Figure 9 Configuration of using the internal LDO.
Section 7.1 specified the recommended operating voltage range of Pvin. The following design guidelines are
recommended when configuring the VCC/LDO.
•
Place a bypass capacitor to minimize disturbances on the VCC pin. For single rail operation using the internal
LDO, a 4.7 µF low ESR ceramic capacitor must be used between Vin pin and PGND and a low ESR ceramic
capacitor with value between 2.2 µF and 10 µF is required to be placed close to the VCC/LDO with reference
to PGND. 10 µF MLCC is recommended for the VCC bypass capacitor when VIN is below 5.5 V.
•
For applications using the internal LDO with 4.3 V ꢋ VIN ꢋ ꢃ.ꢅ V, the LDO can be in the dropout mode. It is
important to ensure that the LDO voltage does not fall below the VCC UVLO threshold voltage. At Vin = 4.3 V,
ICC must not exceed 50 mA under all operating conditions such as during a step-up load transient, in which the
control loop may require the increase of fsw. OCP limits can also be reduced due to the lower VCC voltage.
12.8
Over Current Protection ꢅOCPꢆ
The IR3899A offers cycle-by-cycle OCP response with two selectable current limits set by floating the ILIM pin or
shorting it to GND. The selected OCP limit is loaded to the IC during power up and cannot be changed on the fly.
To change the OCP limit, users must cycle the En signal or VCC voltage. Cycle-by-cycle OCP response allows the
IR3899A to fulfill a brief high current demand, such as a high inrush current during start-up. Detailed operation is
explained as follows:
OCP is activated when En voltage is above its threshold. The OCP circuitry monitors the current of the
Synchronous MOSFET through its RDS (on). When a new PWM pulse is requested by the control loop, if the current
of the Synchronous MOSFET exceeds the OCP limit, the IR3899A skips the PWM pulse and extends the on-time of
the Synchronous MOSFET until the current drops below the OCP limit. OCP operation is also illustrated in Figure
10. During OCP events, the valley of the inductor current is regulated around the OCP limit. However, during the
first switching cycle when the OCP is tripped, the valley of the inductor current can drop slightly below the OCP
limit. It should be noted that OCP events do not pull the Pgood signal low unless the Vo drops below the Pgood
turn-off threshold. If the OCP event persists, the output voltage can eventually drop below the Under Voltage
Protection (UVP) threshold and trigger UVP. Then the IR3899A enters hiccup mode.
The OCP limits are thermally compensated. The OCP limits specified in Section 7.2 refer to the valley of the
inductor current when OCP is tripped. Therefore, the corresponding output DC current can be calculated as
follows:
∆ꢜꢘ
ꢒꢋꢓꢔ_ꢕꢖꢗ = ꢒꢘꢙꢚ
ꢛ
ꢝ
Where: Iout_OCP = Output DC current when OCP is tripped. ILIM = OCP limit specified in the Section 7.2, which is the
valley of inductor current. ΔiL = Peak-peak inductor ripple current.
To avoid inductor saturation during OCP events, the following criterion is recommended for the inductor
saturation current rating.
ꢒꢐꢞꢔ ꢟ ꢒꢘꢙꢚ_ꢠꢞꢡ ꢛ ∆ꢜꢘ
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Theory of operation
Where: Isat is the inductor saturation current and ILIM_max is the maximum spec of the OCP limit.
OCP
Tripped
Current
Limit
UVP Hiccup
Blanking
time
Inductor
Current
Pulse
skipped
HDrv
LDrv
PGood
UVP
Threshold
Vo
PGood Turn-off
Threshold
Figure 10 Cycle-by-cycle OCP response
12.9
Under Voltage Protection ꢅUVPꢆ
Under Voltage Protection (UVP) provides additional protection during OCP fault or other faults. UVP protection
is enabled when the soft-start voltage rises above 100 mV. UVP circuitry monitors VSNS voltage. When VSNS is
below the UVP threshold for 5 µs (typical), an under voltage trip signal asserts and both Control MOSFET and
Synchronous MOSFET are turned off. The IR3899A enters hiccup mode with a blanking time of 20 ms, during
which Control MOSFET and Synchronous MOSFET remain off. After the completion of blanking time, the IR3899A
attempts to recover to the nominal output voltage with a soft-start, as shown in Figure 10. The IR3899A will
repeat hiccup mode and attempt to recover until the UVP condition is removed.
12.10
Over Voltage Protection ꢅOVPꢆ
Over Voltage Protection (OVP) is achieved by comparing the VSNS voltage to an OVP threshold voltage. When the
VSNS voltage exceeds the OVP threshold, an over voltage trip signal asserts after 4 µs (typical) delay. The Control
MOSFET is latched off immediately and Pgood flags low. The Synchronous MOSFET remains on to discharge the
output capacitor. When VSNS voltage drops below around 115% of the reference voltage, Synchronous MOSFET
turns off to prevent complete depletion of the output capacitors. Figure 11 illustrates the OVP operation. The
OVP comparator becomes active when the En signal is above the start threshold.
IR3899A has a Latched OVP response, i.e., when OVP is triggered, the Control FET remains latched off until either
VCC voltage or En signal is cycled.
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Theory of operation
HDrv
LDrv
120%Vref
115%Vref
Vref
OVP
91%Vref
91%Vref
84%Vref
VSNS
PGood
Pgood turn-on
delay =2.5 ms
Pgood turn-on
delay =2.5 ms
OVP delay = 4 us
Figure 11 Over voltage protection response and Pgood behavior.
12.11
Over Temperature Protection ꢅOTPꢆ
Temperature of the controller is monitored internally. When the temperature exceeds the over temperature
threshold, OTP circuitry turns off both Control and Synchronous MOSFETs and resets the internal soft start.
Automatic restart is initiated when the sensed temperature drops back into the operating range. The thermal
shutdown threshold has a hysteresis of 20 °C.
12.12
Power Good ꢅPgoodꢆ Output
The Pgood pin is the open drain of an internal NFET, and must be externally pulled high through a pull-up resistor.
The Pgood signal is high when three criteria are satisfied:
1. En signal and VCC voltage are above their respective thresholds.
2. No over voltage or over temperature faults occur.
3. Vo is within regulation.
In order to detect if VO is in regulation, the Pgood comparator continuously monitors VSNS voltage. When VSNS
voltage ramps up above the upper threshold, the Pgood signal is pulled high after 2.5 ms. When VSNS voltage
drops below the lower threshold, the Pgood signal is pulled low immediately. Figure 11 illustrates the Pgood
response.
During start-up with a pre-biased output voltage, the Pgood signal is held low before the first PWM is generated
and is then pulled high with 2.5 ms delay after VSNS voltage rises above the Pgood threshold. IR3899A also
integrates an additional PFET in parallel to the Pgood NFET, as shown in Figure 2. This PFET allows the Pgood
signal to stay at logic low when the VCC voltage is not present and the Pgood pin is pulled up by an external bias
voltage. Please refer to Figure 8. Since the Pgood PFET has relatively higher on resistance, a ꢃꢁ kΩ pull-up resistor
is needed for a Pgood bias voltage of 3.3V to maintain the Pgood signal at logic low when Pgood PFET is on.
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Theory of operation
12.13
Minimum ON – Time and Minimum OFF – Time
The minimum on-time refers to the shortest time for the Control MOSFET to be reliably turned on. The minimum
off-time refers to the minimum time duration in which the Synchronous FET stays on before a new PWM pulse is
generated. The minimum off-time is needed for IR3899A to charge the bootstrap capacitor, and to sense the
current of the Synchronous MOSFET for OCP.
For applications requiring a small duty cycle, it is important that the selected switching frequency results in an
on-time larger than the maximum spec of the minimum on-time in Section 7.2. Otherwise, the resulting switching
frequency may be lower than the desired target. The following formula should be used to check for the minimum
on-time requirement.
ꢌꢍ
> max ꢣꢤꢥꢦ ꢧꢏ ꢊꢋꢉ ꢩiꢪ
ꢨ
ꢫ
ꢢꢏ × ꢌ
ꢐꢑ
ꢈꢉ
Where fsw is the desired switching frequency. K is the variation of the switching frequency. As a rule of thumb,
select k = 1.25 to ensure design margin.
For applications requiring a high duty cycle, it is important to make sure a proper switching frequency is selected
so that the resulting off-time is longer than the maximum spec of the minimum off-time in Section 7.2, which can
be calculated as shown below.
ꢌ − ꢌꢍ
ꢈꢉ
> max ꢣꢤꢥꢦ ꢧꢏ ꢊꢋꢬꢬ ꢩiꢪ
ꢨ
ꢫ
ꢢꢏ × ꢌ
ꢐꢑ
ꢈꢉ
Where fsw is the desired switching frequency. K is the variation of the switching frequency. As a rule of thumb,
select k = 1.25 to ensure design margin.
The resulting maximum duty cycle is therefore determined by the selected on-time and minimum off-time.
ꢊ
ꢋꢉ
ꢭꢠꢞꢡ
=
ꢊ
ꢋꢉ
ꢛ ꢊꢋꢬꢬꢨꢩiꢪꢫ
12.14
Selection of Feedforward Capacitor and Feedback Resistors
Output voltage can be programmed with an external voltage divider. The FB voltage is compared to an internal
reference voltage of 0.6 V. The divider ratio is set to provide 0.6 V at the FB pin when the output is at its desired
value. The calculation of the feedback resistor divider is shown below.
ꢰꢱꢲꢳ
ꢌꢕ = ꢌ × (ꢎ ꢛ
)
ꢮꢯꢬ
ꢰꢱꢲꢴ
Where RFB1 and RFB2 are the top and bottom feedback resistors.
A small MLCC capacitor, Cff, is preferred in parallel with the top feedback resistor, RFB1, to provide extra phase
boost and improve the transient load response, as shown in Figure 12. The following formula can be used to
help select Cff and RFB1. The value of Cff is recommended to be 100 pF or higher to minimize the impact of circuit
parasitic capacitance, where LO and CO are the output LC filter of the buck regulator. Table 3 lists the suggested
ꢌmꢀ for some common outputs. Cff and RFB1 may be further optimized based on the transient load tests.
ꢶ ꢵ
√
ꢍ
ꢍ
ꢰꢱꢲꢳꢵꢬꢬ
=
ꢷ × 4.ꢸ
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Theory of operation
Vo
RFB1
RFB2
Cff
FB
Figure 12 Configuration of feedforward capacitor, Cff.
Table 3 Selection of m
Vo
m
0.3
0.5
0.7
ꢇ.ꢁ V ꢋ Vo ꢋ ꢃ.ꢁ V
1.2 V < Vo < 3.0 V
Vo ꢋ ꢂ.ꢄ V
12.15
Resistors for Configuration Pins
To properly configure the TON/ MODE pin, E96 resistors with ±1% tolerance must be used per Table 2 and Section
7.2. If E12 resistor values are preferred, the E96 resistors can be replaced with two or three E12 resistors in series,
as shown in Table 4. Note that the tolerance of E12 resistors must be ±0.1%.
Table 4 Replacement of E96 configuration resistors with E12 resistors in series
E96 ±1%
R ꢍkΩꢎ
4.53
1.50
5.76
2.49
7.32
3.45
8.87
10.5
12.1
21.5
14
E12 ±0.1% (R = RS1 + RS2 or RS1 + RS2 + RS3)
RS1 ꢍkΩꢎ
RS2 ꢍkΩꢎ
1.8
RS3 ꢍkΩꢎ
2.7
1.5
5.6
1.8
6.8
3.3
8.2
10
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.18
0.18
0
0.15
0.68
0.56
0.15
0.68
0.47
0.1
12
18
3.3
10
3.9
24.9
16.2
28.7
21.5
24.9
22
2.7
15
1.2
27
1.8
18
3.3
22
2.7
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Design example
13 Design example
In this section, an example is used to demonstrate how to design a buck regulator with the IR3899A. The
application circuit is shown in Figure 13. The design specifications are given below:
•
•
•
•
•
PVin = 12 V (±10%)
VO = 1.2 V
IO = 9 A
VO ripple voltage = ± 1% of VO
Load transient response = ± 3% of VO with a step load current = 4.5 A and slew rate = 5 A/µs
13.1
Enabling the IRꢈꢉꢊꢊA
The IR3899A has a precise Enable threshold voltage, which can be used to implement a UVLO of the input bus
voltage by connecting the En pin to Pvin with a resistor divider, as shown in Configuration 2 of Figure 7. The
Enable feedback resistor, REN1 and REN2, can be calculated as follows.
ꢰꢹꢺꢴ
ꢆꢌ
×
ꢟ ꢌꢹꢺꢨꢩꢻꢼꢫ
ꢈꢉꢨꢩiꢪꢫ
ꢰꢹꢺꢳ ꢛ ꢰꢹꢺꢴ
ꢌꢹꢺꢨꢩꢻꢼꢫ
ꢆꢌꢈꢉꢨꢩiꢪꢫ − ꢌꢹꢺꢨꢩꢻꢼꢫ
ꢰꢹꢺꢴ ꢟ ꢰꢹꢺꢳ
×
Where VEN (max) is the maximum spec of the Enable-start-threshold as defined in Section 7.2. For Pvin (min) =10.8 V,
select REN1 = 49.9 kΩ and REN2 = 7.5 kΩ.
13.2
Programming the Switching Frequency and Operation Mode
The IR3899A has very good efficiency performance and is suitable for high switching frequency operation. In this
case, 600 kHz is selected to achieve a good compromise between efficiency, passive component size and
dynamic response. In addition, FCCM operation is selected to ensure a small output ripple voltage over the entire
load range. To select 600 kHz and FCCM operation, the TON/MODE pin is connected to a 0 kΩ resistor to GND per
Table 2.
13.3
Selecting Input Capacitors
Without input capacitors, the pulse current of the Control MOSFET is provided directly from the input supply.
Due to the impedance of the cable, the pulse current can cause disturbance on the input voltage and potential
EMI issues. The input capacitors filter the pulse current, resulting in almost constant current from the input
supply. The input capacitors should be selected to tolerate the input pulse current, and to reduce the input
voltage ripple. The RMS value of the input ripple current can be expressed by:
ꢒꢁꢚꢽ = ꢒ × ꢭ × ꢨꢎ − ꢭꢫ
√
ꢋ
ꢌ
ꢋ
ꢭ =
ꢆꢌ
ꢈꢉ
Where IRMS is the RMS value of the input capacitor current. Io is the output current and D is the Duty Cycle. For Io =
9 A and D(max) = 0.1, the resulting RMS current flowing into the input capacitor is Irms = 2.7 A.
Final Datasheet
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Design example
To meet the requirement of the input ripple voltage, the minimum input capacitance can be calculated as
follows.
ꢒꢋ × ꢨꢎ − ꢭꢫ × ꢭ
ꢵꢈꢉꢨꢩiꢪꢫ
>
ꢨ
ꢫ
ꢏ × ꢨ∆ꢆꢌ − ꢾꢿꢰ × ꢒꢋ × ꢎ − ꢭ ꢫ
ꢐꢑ
ꢈꢉ
Where ∆Pvin is the maximum allowable peak-to-peak input ripple voltage, and ESR is the equivalent series
resistance of the input capacitors. Ceramic capacitors are recommended due to low ESR, ESL and high RMS
current capability. For Io = 9 A, fsw = 6ꢁꢁ kHz, ESR = ꢇ mΩ, and ∆Pvin = 240 mV, Cin(min) > 11.0 µF. To account for the
derating of ceramic capacitors under a bias voltage, four 22 µF/0805/25V MLCC are used for the input capacitor.
In addition, a bulk capacitor is recommended if the input supply is not located close to the voltage regulator.
13.4
Inductor Selection
The inductor is selected based on output power, operating frequency and efficiency requirements. A low inductor
value results in a large ripple current, lower efficiency and high output noise, but helps with size reduction and
transient load response. Generally, the desired peak-to-peak ripple current in the inductor ꢍ∆iꢎ is found between
20% and 50% of the output current.
The inductor saturation current must be higher than the maximum spec of the OCP limit plus the peak-to-peak
inductor ripple current. For some core material, inductor saturation current may decrease with increasing
temperature. It is important to check the inductor saturation current at the maximum operating temperature.
The inductor value for the desired operating ripple current can be determined using the following relations:
ꢭꢠꢈꢉ
ꢶ = ꢨꢆꢌꢈꢉꢨꢩꢻꢼꢫ − ꢌ ꢫ ×
ꢋ
∆ꢜꢘꢨꢩꢻꢼꢫ × ꣀ
ꢐꢑ
ꢌ
ꢋ
ꢭꢠꢈꢉ
=
ꢆꢌ
ꢈꢉꢨꢩꢻꢼꢫ
ꢒꢐꢞꢔ ꢟ ꣁꢵꢆꢠꢞꢡ ꢛ ∆ꢜꢘꢨꢩꢻꢼꢫ
Where: PVin (max) = Maximum input voltage; ∆iLmax = Maximum peak-to-peak inductor ripple current; OCPmax
=
maximum spec of the OCP limit as defined in Section 7.2; and Isat = inductor saturation current. In this case, select
inductor L = 470 nH to achieve ∆iLmax = 43% of Iomax. The Isat should be no less than 19.0 A.
13.5
Output Capacitor Selection
The output capacitor selection is mainly determined by the output voltage ripple and transient requirements.
To satisfy the Vo ripple requirement, Co should satisfy the following criterion:
∆ꢜꢘꢠꢞꢡ
ꢵꢋ >
ꣂ × ∆ꢌ × ꢏ
ꢋꢮ
ꢐꢑ
Where ∆Vor is the desired peak-to-peak output ripple voltage. For ∆iLmax = 3.8 A, ∆Vor = 24 mV, fsw = 600 kHz, Co must
be larger than 33 µF. The ESR and ESL of the output capacitors, as well as the parasitic resistance or inductance
due to PCB layout, can also contribute to the output voltage ripple. It is suggested to use Multi-Layer Ceramic
Capacitor (MLCC) for their low ESR, ESL and small size.
To meet the transient response requirements, the output capacitors should also meet the following criterion:
ꢶ × ∆ꢒꢋꢴꢨꢩꢻꢼꢫ
ꢵꢋ >
ꢝ × ∆ꢌ × ꢌ
ꢋꢘ
ꢋ
Where ∆VOL is the allowable Vo deviation during the load transient. ∆Io(max) is the maximum step load current.
Please note that the impact of ESL, ESR, control loop response, transient load slew rate, and PWM latency is not
Final Datasheet
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Design example
considered in the calculation shown above. Extra capacitance is usually needed to meet the transient
requirements. As a rule of thumb, we can triple the Co that is calculated above as a starting point, and then
optimize the design based on bench measurement. In this case, to meet the transient load requirement ꢍi.e. ∆VOL=
54 mV, ∆Io(max) = 4.5 A), select Co = ~110 µF. For more accurate estimation of Co, simulation tools should be used to
aid the design.
13.6
Output Voltage Programming
Output voltage can be programmed with an external voltage divider. The FB voltage is compared to an internal
reference voltage of 0.6 V. The divider ratio is set to provide 0.6 V at the FB pin when the output is at its desired
value. The calculation of the feedback resistor divider is shown below.
ꢰꢱꢲꢳ
ꢌ = ꢌ × ꢨꢎ ꢛ
ꢫ
ꢋ
ꢮꢯꢬ
ꢰꢱꢲꢴ
Where RFB1 and RFB2 are the top and bottom feedback resistors. Select RFB1 = ꢂꢁ kΩ and RFB2 = ꢂꢁ kΩ, to achieve Vo
= 1.2 V. The same resistor divider can be used at the VSNS pin to achieve the same voltage scaling factor.
13.7
Feedforward Capacitor
A small MLCC capacitor, Cff, can be placed in parallel with the top feedback resistor, RFB1, to improve the transient
response. Based on Section 12.14, Cff can be selected using the following formula.
ꢶ ꢵ
√
ꢍ
ꢍ
ꢰꢱꢲꢳꢵꢬꢬ
=
ꣃ.꣄ × 4.ꢸ
With Lo = 470 nH, Co = 114 µF and RFB1 = ꢂꢁ kΩ, Cff = ~220 pF. Cff can be further optimized based on bench testing
of transient load response.
13.8
Bootstrap Capacitor
For most applications, a 0.1 µF ceramic capacitor is recommended for bootstrap capacitor placed between SW
and BOOT. For applications requiring Pvin equal to or above ꢂꢅ V, a small resistor between ꢂ Ω and ꢄ Ω can be
used in series with the BOOT pin to ensure the maximum SW node spike voltage does not exceed 20 V.
13.9
Vin and VCC/LDO bypass Capacitor
Please see the recommendation in Section 12.7. A 10 µF MLCC is selected for the VCC/LDO bypass capacitor and
a 4.7 µF MLCC is selected for the Vin bypass capacitor.
Final Datasheet
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Application information
14 Application information
14.1
Application Diagram
Cin2
4 x 22 uF
Cin1
4.7 uF
CinHF
0.1 uF
Vin = 12 V ±10%
+
Optional
REN1
REN2
49.9 k ꢀ
7.5 k ꢀ
Cvin
4.7 uF
RBoot
0 ꢀ
PVin
Vin
En
BOOT
SW
VCC/LDO
CBoot
0.1 uF
Vo = 1.2 V
RPG
Cvcc
10 uF
49.9 k ꢀ
L
PGood
470 nH
CoHF
0.1uF
Co
3 x 47 uF
PGood
ILIM
IR3899A
RFB1
10 k ꢀ
Cff
220 pF
Float
VSNS
FB
(OCP = 12.7 A)
TON/MODE
RTon
0 ꢀ
RFB2
10 k ꢀ
NC
PGND
AGND
Figure 13 Application diagram of IR3899A. Pvin = 12 V, Vo = 1.2 V, Io = 9 A, fsw = 600 kHz.
14.2
Typical Operating Waveforms
PVin = Vin = 12.0 V, Vo = 1.2 V, Io = 0 – 9 A, fsw = 600 kHz, Room Temperature, no airflow
Figure 14
Start up at 9 A Load, (Ch1: Pgood, Ch2: Vout, Ch3: Pvin, Ch4: Enable)
Final Datasheet
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Application information
Figure 15
Pre-bias Start up at 0 A Load, (Ch1: Pgood, Ch2: Vout, Ch3: Pvin, Ch4: Enable)
Figure 16
Vout ripple at 9 A Load, fsw = 600 kHz, (Ch2: Vo)
Figure 17
SW node, 9 A load, fsw = 600 kHz, (Ch4: SW)
Final Datasheet
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Application information
Figure 18
Short circuit and UVP (Hiccup), (Ch1: Pgood, Ch2: Vo)
Load step up: 4.5 A to 9 A
Load step down: 9 A to 4.5 A
Figure 19 Transient response at 4.5 A step load current: Io= 4.5 A – 9 A, (Ch2: Vo, Ch4: Io), pk-pk: 50.2 mV,
fsw = 600 kHz
Final Datasheet
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Layout Recommendations
15 Layout Recommendations
PCB layout is very important when designing high frequency switching converters. Layout will affect noise pickup
and can cause a good design to perform with less than expected results. The following design guidelines are
recommended to achieve the best performance.
•
Bypass capacitors, including input/output capacitors, Vin and VCC bypass capacitors, should be placed as
close to the corresponding pins as possible.
•
Place bypass capacitors from IR3899A power input (Drain of Control MOSFET) to PGND (Source of Synchronous
MOSFET) to reduce noise and ringing in the system. The output capacitors should be terminated to a ground
plane that is away from the input PGND to mitigate switching spikes on the Vout. The Vin and VCC bypass
capacitors should be terminated to PGND.
•
•
•
Place a boot strap capacitor as close as possible to IR3899A BOOT and SW pins to minimize loop inductance.
SW node copper should only be routed on the top layer to minimize the impact of switching noise.
Connect the AGND pin to the PGND pad through a single point connection. On the IR3899A demo board, AGND
pin is connected to the exposed AGND pad (Pin 4) and then connected to the internal PGND layer through
thermal via holes.
•
•
Via holes can be placed on Pvin and PGND pads to aid thermal dissipation.
Wide copper polygons are desired for Pvin and PGND connections in favor of power loss reduction and thermal
dissipation. Sufficient via holes should be used to connect power traces between different layers.
•
To implement the Vo sensing, the following design guidelines should be followed, as illustrated in Figure 13.
o
The output voltage can be sensed from a high-frequency bypass capacitor of 0.1 µF or higher, through
a 15 mil PCB trace.
o
o
Keep the Vout sense line away from any noise sources and shield the sense line with ground planes.
The sense trace is connected to a feedback resistor divider with the lower resistor terminated at the
AGND pin.
The EN pin and configuration pins including TON/MODE and ILIM should be terminated to a quiet ground. On the
IR3899A standard demo board, they are terminated to the PGND copper plane away from the power current flow.
Alternatively, they can be terminated to a dedicated AGND PCB trace.
15.1
Solder mask
Evaluation has shown that the best overall performance is achieved using the substrate/PCB layout as shown in
the following figures. PQFN devices should be placed to an accuracy of 0.050 mm on both X and Y axes. Self-
centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the
limits of self-centering on specific processes.
Infineon recommends that larger Power or Land Area pads are Solder Mask Defined (SMD). This allows the
underlying copper traces to be as large as possible, which helps in terms of current carrying capability and device
cooling capability. When using SMD pads, the underlying copper traces should be at least 0.05 mm larger (on
each edge) than the openings in the solder mask. This allows for layers to be misaligned by up to 0.1 mm on both
axes. Ensure that the solder resist between the smaller signal lead areas is at least 0.15 mm wide due to the high
x/y aspect ratio of the solder mask strip.
Final Datasheet
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Layout Recommendations
PCB PAD
1.45
1.77
0.87
1.86
1.57
0.15
2.00
2.10
0.25
2.10
0.15
0.35
0.75
1.925
1.925
0.75
0.25
2.35
0.42
0.50
SOLDER MASK DESIGN
0.35
1.86
1.57
0.31
0.53
0.35
0.52
0.20
0.55
0.15
2.00
2.00
0.15
0.20
0.30
0.35
1.35
0.35
1.67
0.77
1.925
1.925
0.80
2.25
0.80
0.42
0.50
0.30
Figure 20
PCB Metal and Solder mask (all dimensions in mm)
15.2
Stencil design
Stencils for PQFN packages can be used with thicknesses of 0.100-0.250 mm (0.004-ꢁ.ꢁꢂꢁ”ꢎ. Stencils thinner than
0.100 mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the
ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125 mm-0.200 mm
(0.005-ꢁ.ꢁꢁꢈ”ꢎ, with suitable reductions, give the best results. A recommended stencil design is shown below.
This design is for a stencil thickness of ꢁ.ꢂꢄꢊ mm ꢍꢁ.ꢁꢁꢃ”ꢎ. The reduction should be adjusted for stencils of other
thicknesses.
Final Datasheet
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Layout Recommendations
SOLDER PASTE STENCIL
1.58
0.21
0.91
0.27
0.27
0.66
0.57
0.50
0.41
0.55
0.41
0.55
0.73
0.27
0.27
0.34
1.92
0.55
0.72
0.33
0.50
0.73
1.03
0.92
0.50
0.69
0.60
0.92
0.90
0.10
0.70
0.55
0.22
0.60
0.36
0.72
0.15
0.46
0.80
0.72
0.60
0.36
0.50
0.36
0.22
1.06
Figure 21
Stencil pad size and spacing (all dimensions in mm)
Final Datasheet
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Package
16
Package
This section includes mechanical and packaging information for the IR3899A.
16.1
Marking Information
PRODUCT MARKING
ASSEMBLY SITE CODE
DATE CODE (YWW)
LOT CODE
PIN 1 MARKER
Figure 22
Package Marking
16.2
Dimensions
SIDE VIEW (Back)
D
Dimension Table
Millimeter
B
A
A3
MINIMUM NOMINAL MAXIMUM
A
A1
A3
b1
b2
D
0.80
0.90
0.02
1.00
0.00
---
0.05
---
0.20 Ref
0.20
0.15
0.25
0.25
0.35
0.30
4.00 BSC
5.00 BSC
0.50 BSC
0.55 BSC
0.659 BSC
2.188
E
e1
e2
e3
D1
E1
D2
E2
L
24
2.038
1.05
2.288
1.30
1
1.20
A1
0.05 C
2x
1.467
2.05
0.30
1.617
1.717
2.30
0.50
2.20
SIDE VIEW (Left)
SIDE VIEW (Right)
TOP VIEW
0.40
(Bottom View Flip Line)
N
24
0.10 C
SEATING
PLANE
4
Nx
0.08 C
Final Datasheet
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Package
D1
b1
e1
13x
10x
7
2.500
1
1
7
2.100
1.747
1.747
1.547
24
8
24
8
1.147
0.647
0.020
0.547
0.000
0.230
0.230
0.530
0.530
0.930
0.930
1.480
1.480
2.030
2.180
2.500
2.030
2.180
14
18
14
18
15
17
15
17
b2
e3
11x
2x
D2
BOTTOM VIEW
Figure 23
Package Dimensions (all dimensions in mm)
Final Datasheet
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IR3899A IPOL
9 A single-voltage synchronous Buck regulator
Environmental qualifications
17
Environmental qualifications
Qualification Level
Industrial
Moisture Sensitivity
PQFN Package
JEDEC Level 2 @ 260 °C
Human Body Model
Charged Device Model
ANSI/ESDA/JEDEC JS-001, Level 1C (1000 V to < 2000 V)
ANSI/ESDA/JEDEC JS-002, Level Cꢇ ꢍꢏ 1000 V)
Yes
ESD
RoHS Compliant
Final Datasheet
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IR3899AꢀIPOL
IR3899A
RevisionꢀHistory
IR3899A
Revision:ꢀ2022-07-28,ꢀRev.ꢀ2.3
Previous Revision
Revision Date
Subjects (major changes since last revision)
2.0
2.1
Release of final version
2021-01-15
2021-05-05
(1) Max. Vout updated to 6V in recommended operating conditions; (2) Update to Note
2, 4 and added Note 5.
2.2
2.3
(1) Updated Ordering Information; (2) Fixed typo in 12.9 - UVP enabled after soft start
reaches 100mV.
2021-08-03
2022-07-28
Updated Orderable Part Number.
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38
Rev.ꢀ2.3,ꢀꢀ2022-07-28
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