IR3899 [INFINEON]
9A Highly Integrated SupIRBuck Single.Input Voltage; 9A高度集成的SupIRBuck Single.Input电压
| 型号： | IR3899 |
| 厂家： | 
Infineon |
| 描述： | 9A Highly Integrated SupIRBuck Single.Input Voltage |
| 文件： | 总45页 (文件大小：2539K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
‐
9A Highly Integrated SupIRBuckTM
IR3899
Single‐Input Voltage, Synchronous Buck Regulator
FEATURES
DESCRIPTION
The IR3899 SupIRBuckTM is an easy‐to‐use, fully integrated
and highly efficient DC/DC regulator. The onboard PWM
controller and MOSFETs make IR3899 a space‐efficient
solution, providing accurate power delivery.
Single 5V to 21V application
Wide Input Voltage Range from 1.0V to 21V with
external Vcc
Output Voltage Range: 0.5V to 0.86× Vin
IR3899 is a versatile regulator which offers programmable
switching frequency and the fixed internal current limit
while operates in wide input and output voltage range.
Enhanced Line/Load Regulation with Feed‐Forward
Programmable Switching Frequency up to 1.5MHz
Internal Digital Soft‐Start/Soft‐Stop
The switching frequency is programmable from 300kHz to
1.5MHz for an optimum solution.
Enable input with Voltage Monitoring Capability
Thermally Compensated Current Limit with robust
It also features important protection functions, such as
Pre‐Bias startup, thermally compensated current limit,
over voltage protection and thermal shutdown to give
required system level security in the event of fault
conditions.
hiccup mode over current protection
Smart internal LDO to improve light load and full
load efficiency
External Synchronization with Smooth Clocking
Enhanced Pre‐Bias Start‐Up
APPLICATIONS
Netcom Applications
Precision Reference Voltage (0.5V+/‐0.5%) with
margining capability
Vp for Tracking Applications (Source/Sink Capability
+/‐9A)
Embedded Telecom Systems
Server Applications
Integrated MOSFET drivers and Bootstrap Diode
Thermal Shut Down
Storage Applications
Distributed Point of Load Power Architectures
Programmable Power Good Output with tracking
capability
Monotonic Start‐Up
Operating temp: ‐40oC < Tj < 125oC
Small Size: 4mm x 5mm PQFN
Lead‐free, Halogen‐free and RoHS Compliant
BASIC APPLICATION
98
96
94
92
90
88
86
84
82
80
78
12Vin,Internal bias,Frequency 600KHz
0.9
1.8
2.7
3.6
4.5
Load Current (A)
1.2Vout 3.3Vout
5.4
6.3
7.2
8.1
9
Figure 1: IR3899 Basic Application Circuit
Figure 2: IR3899 Efficiency
1
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
IR3899
Single‐Input Voltage, Synchronous Buck Regulator
Package
Tape & Reel Qty
Part Number
IR3899MTR1PBF
IR3899MTRPBF
ORDERING INFORMATION
M
M
750
4000
IR3899 ―
PBF – Lead Free
TR/TR1 – Tape and Reel
M – Package Type
PIN DIAGRAM
4mm x 5mm POWER QFN
TOP VIEW
PVin
PGND
11
SW
12
13
Vcc/LDO_Out
14
10
Boot
GND
Vin
15
16
9
8
Enable
VP
17
Vsns
1
2
3
4
5
6
7
JA 32o C /W
J -PCB 2o C /W
2
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
IR3899
Single‐Input Voltage, Synchronous Buck Regulator
BLOCK DIAGRAM
Figure 3: IR3899 Simplified Block Diagram
3
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
IR3899
Single‐Input Voltage, Synchronous Buck Regulator
PIN DESCRIPTIONS
PIN #
PIN NAME
PIN DESCRIPTION
Inverting input to the error amplifier. This pin is connected directly to the output
of the regulator via resistor divider to set the output voltage and provide
feedback to the error amplifier.
1
Fb
Internal reference voltage , it can be used for margining operation also. In
normal mode and sequencing mode, a 100pF ceramic capacitor is recommended
between this pin and Gnd. In tracking mode operation, Vref should be tied to
Gnd.
2
Vref
Output of error amplifier. An external resistor and capacitor network is typically
connected from this pin to Fb to provide loop compensation.
3
4
Comp
Gnd
Signal ground for internal reference and control circuitry.
Multi‐function pin to set switching frequency. Use an external resistor from this
pin to Gnd to set the free‐running switching frequency. An external clock signal
can be connected to this pin through a diode so that the device’s switching
frequency is synchronized with the external clock.
5
6
Rt/Sync
S_Ctrl
Soft start/stop control. A high logic input enables the device to go into the
internal soft start; a low logic input enables the output soft discharged. Pull this
pin to Vcc if this function is not used.
Power Good status pin. Output is open drain. Connect a pull up resistor (49.9k)
from this pin to the voltage lower than or equal to the Vcc.
7
8
PGood
Vsns
Sense pin for over‐voltage protection and PGood. It is optional to tie this pin to
FB pin directly instead of using a resistor divider from Vout.
Input voltage for Internal LDO. A 1.0µF capacitor should be connected between
this pin and PGnd. If external supply is connected to Vcc/LDO_Out pin, this pin
should be shorted to Vcc/LDO_out pin.
9
Vin
Input Bias for external Vcc Voltage/ output of internal LDO. Place a minimum
2.2µF cap from this pin to PGnd.
10
11
Vcc/LDO_Out
PGnd
Power Ground. This pin serves as a separated ground for the MOSFET drivers
and should be connected to the system’s power ground plane.
12
13
SW
Switch node. This pin is connected to the output inductor.
Input voltage for power stage.
PVin
Supply voltage for high side driver, a 100nF capacitor should be connected
between this pin and SW pin.
14
15
Boot
Enable pin to turn on and off the device, if this pin is connected to PVin pin
through a resistor divider, input voltage UVLO can be implemented.
Enable
Input to error amplifier for tracking purposes. In the normal operation, it is left
floating and no external capacitor is required. In the sequencing or the tracking
mode operation, an external signal can be applied as the reference.
16
17
Vp
Gnd
Signal ground for internal reference and control circuitry.
4
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
IR3899
Single‐Input Voltage, Synchronous Buck Regulator
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications are not implied.
PVin, Vin
‐0.3V to 25V
VCC/LDO_Out
‐0.3V to 8V (Note 2)
‐0.3V to 33V
Boot
SW
‐0.3V to 25V (DC), ‐4V to 25V (AC, 100ns)
‐0.3V to VCC + 0.3V (Note 1)
‐0.3V to VCC + 0.3V (Note 1)
‐0.3V to +3.9V
Boot to SW
S_Ctrl, PGood
Other Input/Output Pins
PGnd to Gnd
‐0.3V to +0.3V
Storage Temperature Range
Junction Temperature Range
ESD Classification (HBM JESD22‐A114)
Moisture Sensitivity Level
‐55°C to 150°C
‐40°C to 150°C (Note 2)
2kV
JEDEC Level 2@260°C
Note 1: Must not exceed 8V
Note 2: Vcc must not exceed 7.5V for Junction Temperature between ‐10°C and ‐40°C
5
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
IR3899
Single‐Input Voltage, Synchronous Buck Regulator
ELECTRICAL SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS FOR RELIABLE OPERATION WITH MARGIN
UNITS
SYMBOL
MIN
1.0
5
MAX
21
Input Voltage Range*
Input Voltage Range**
Supply Voltage Range***
Supply Voltage Range
Output Voltage Range
Output Current Range
Switching Frequency
PVin
Vin
21
V
VCC
4.5
4.5
0.5
0
7.5
Boot to SW
7.5
VO
IO
0.86xVin
±9
A
kHz
°C
FS
TJ
300
‐40
1500
125
Operating Junction Temperature
*Maximum SW node voltage should not exceed 25V.
**For internally biased single rail operation. When Vin drops below 6.8V, the internal LDO enters dropout. Please refer to Smart LDO
section and Over Current Protection for detailed application information.
*** Vcc/LDO_Out can be connected to an external regulated supply. If so, the Vin pin should be connected to Vcc/LDO_Out pin.
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, these specifications apply over, 6.8V < Vin = PVin < 21V, Vref = 0.5V in 0°C < TJ < 125°C.
Typical values are specified at Ta = 25°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Power Stage
PVin=Vin = 12V, VO = 1.2V,
IO = 9A, Fs = 600kHz, L = 0.51uH,
Vcc = 6.4V, Note 4
Power Losses
PLOSS
1.4
W
Top Switch
Rds(on)_Top
Rds(on)_Bot
VBoot ‐Vsw=6.4V,IO=9A, Tj =25°C
Vcc = 6.4V, IO = 9A, Tj = 25°C
I(Boot) = 10mA
17.5
8.5
22.5
11.0
470
mΩ
mV
µA
ns
Bottom Switch
Bootstrap Diode Forward Voltage
SW Leakage Current
180
5
260
ISW
SW = 0V, Enable = 0V
SW = 0V, Enable = high, Vp = 0V
Note 4
1
Dead Band Time
Tdb
10
12
30
Supply Current
VIN Supply Current (standby)
VIN Supply Current (dynamic)
Iin(Standby)
Iin(Dyn)
EN = Low, No Switching
100
16
µA
EN = High, Fs = 600kHz,
Vin = PVin = 21V
mA
Vcc/ LDO_ Out
Vcc
Output Voltage
Vin(min) = 6.8V, Icc = 0‐30mA,
Cload = 2.2uF, DCM = 0
6.0
4.0
6.4
4.4
6.7
V
Vin(min) = 6.8V, Icc = 0‐30mA,
Cload = 2.2uF, DCM = 1
4.8
0.7
LDO Dropout Voltage
Vcc_drop
Ishort
Icc=30mA,Cload=2.2uF
V
mA
s
Short Circuit Current
70
Zero‐crossing Comparator Delay
Tdly_zc
Note 4
256/Fs
6
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
IR3899
Single‐Input Voltage, Synchronous Buck Regulator
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Zero‐crossing Comparator Offset
Vos_zc
Note 4
‐4
0
4
mV
Oscillator
Rt Voltage
Vrt
Fs
1.0
300
V
Frequency Range
Rt = 80.6K
Rt = 39.2K
Rt = 15.0K
270
540
330
660
600
kHz
1350
1500
1.05
1650
Ramp Amplitude
Vramp
Vin = 7.0V, Vin slew rate max =
1V/µs, Note 4
Vin = 12V, Vin slew rate max =
1V/µs, Note 4
1.80
3.15
0.75
0.16
Vp‐p
Vin = 21V, Vin slew rate max =
1V/µs, Note 4
Vcc=Vin = 5V, For external Vcc
operation, Note 4
Ramp Offset
Ramp(os)
Tmin(ctrl)
Dmax
Toff
Note 4
V
ns
%
Min Pulse Width
Max Duty Cycle
Note 4
60
Fs = 300kHz, PVin = Vin = 12V
Note 4
86
Fixed Off Time
200
200
250
ns
kHz
ns
Sync Frequency Range
Sync Pulse Duration
Sync Level Threshold
Fsync
270
100
3
1650
Tsync
High
V
Low
0.6
Error Amplifier
Input Offset Voltage
Vos_Vref
Vos_Vp
IFb(E/A)
IVp(E/A)
Isink(E/A)
Isource(E/A)
SR
VFb – Vref, Vref = 0.5V
VFb – Vp, Vp = 0.5V
‐1.5
‐1.5
‐1
+1.5
+1.5
+1
%
Input Bias Current
Input Bias Current
Sink Current
µA
0
+4
0.4
4
0.85
7.5
12
1.2
11
mA
mA
V/µs
MHz
dB
Source Current
Slew Rate
Note 4
Note 4
Note 4
7
20
Gain‐Bandwidth Product
DC Gain
GBWP
20
100
1.7
30
40
Gain
110
2.0
120
2.3
100
1.2
Maximum output Voltage
Minimum output Voltage
Common Mode input Voltage
Reference Voltage
Vmax(E/A)
Vmin(E/A)
V
mV
V
0
V
Feedback Voltage
Accuracy
Vfb
Vref and Vp pin floating
0°C < Tj < +70°C
0.5
‐0.5
‐1.0
+0.5
+1.0
%
‐40°C < Tj < +125°C, Note 3
7
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
IR3899
Single‐Input Voltage, Synchronous Buck Regulator
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Vref Margining Voltage
Sink Current
Vref_marg
Isink_Vref
0.4
1.2
V
Vref = 0.6V
12.7
12.7
16.0
16.0
19.3
19.3
0.15
µA
Source Current
Isrc_Vref
Vref = 0.4V
Vref Comparator Threshold
Vref_disable
Vref_enable
Vref pin connected externally
V
0.4
Soft Start/Stop
Soft Start Ramp Rate
Soft Stop Ramp Rate
S_Ctrl Threshold
Ramp(SS_start)
Ramp(SS_stop)
High
0.16
‐0.24
2.4
0.2
0.24
mV/µs
V
‐0.2
‐0.16
Low
0.6
Power Good
PGood Turn on Threshold
VPG(on)
Vsns Rising, 0.4V < Vref < 1.2V
Vsns Rising, Vref < 0.1V
85
85
80
80
90
90
95
95
90
90
% Vref
% Vp
% Vref
% Vp
ms
PGood Lower Turn off Threshold
VPG(lower)
Vsns Falling, 0.4V < Vref < 1.2V
Vsns Falling, Vref < 0.1V
85
85
PGood Turn on Delay
VPG(on)_Dly
VPG(upper)
Vsns Rising,see VPG(on)
1.28
120
120
2
PGood Upper Turn off Threshold
Vsns Rising, 0.4V < Vref < 1.2V
Vsns Rising, Vref < 0.1V
115
115
1
125
125
3.5
% Vref
% Vp
µs
PGood Comparator Delay
PGood Voltage Low
VPG(comp)_
Dly
Vsns < VPG(lower) or
Vsns >VPG(upper)
PG(voltage)
IPgood = ‐5mA
0.5
V
V
Tracker Comparator Upper
Threshold
VPG(tracker_
upper)
Vp Rising, Vref < 0.1V
0.4
0.3
Tracker Comparator Lower
Threshold
VPG(tracker_
lower)
Vp Falling, Vref < 0.1V
Tracker Comparator Delay
Tdelay(tracker) Vp Rising, Vref < 0.1V,see
VPG(tracker_upper)
1.28
ms
Under‐Voltage Lockout
Vcc‐Start Threshold
Vcc‐Stop Threshold
VCC_UVLO_Start
Vcc Rising Trip Level
4.0
3.7
4.2
3.9
4.4
4.1
V
VCC_UVLO_Stop
Vcc Falling Trip Level
Enable_UVLO_Start
Enable‐Start‐Threshold
Enable‐Stop‐Threshold
Enable Leakage Current
Over‐Voltage Protection
OVP Trip Threshold
Supply ramping up
1.14
0.95
1.2
1
1.26
1.05
1
V
Enable_UVLO_Stop
Supply ramping down
Ien
Enable = 3.3V
µA
OVP_Vth
Vsns Rising, 0.45V < Vref < 1.2V
Vsns Rising, Vref < 0.1V
115
115
1
120
120
2
125
125
3.5
% Vref
% Vp
µs
OVP Comparator Delay
OVP_Tdly
8
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
IR3899
Single‐Input Voltage, Synchronous Buck Regulator
PARAMETER
Over‐Current Protection
Current Limit
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
ILIMIT
Tj = 25°C, Vcc = 6.4V
Note 4
11
12.7
15.0
A
Hiccup Blanking Time
Over‐Temperature Protection
Thermal Shutdown Threshold
Hysteresis
Tblk_Hiccup
20.48
ms
Ttsd
Note 4
Note 4
145
20
°C
Ttsd_hys
Note 3: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.
Note 4: Guaranteed by design but not tested in production.
9
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = 12V, Vcc = Internal LDO (4.4V/6.4V), Io = 0A‐9A, Fs = 600KHz, Room Temperature, No Air Flow. Note that the
efficiency and power loss curves include the losses of IR3899, the inductor losses and the losses of the input and output
capacitors.
The table below shows the inductors used for each of the output voltages in the efficiency measurement.
VOUT (V)
LOUT (µH)
0.51
P/N
DCR (mΩ)
0.29
1.0
1.2
1.8
3.3
5
59PR9876N (Vitec)
59PR9876N (Vitec)
ETQP4LR68XFC (Panasonic)
MPL105‐1R2 (Delta)
MPL105‐1R2 (Delta)
0.51
0.29
0.68
1.58
1.2
2.9
1.2
2.9
98
96
94
92
90
88
86
84
82
80
78
0.9
1.8
2.7
3.6
4.5
5.4
6.3
7.2
8.1
9
Load Current (A)
1.0V
1.2V
1.8V
3.3V
5.0V
2.6
2.2
1.8
1.4
1
0.6
0.2
0.9
1.8
2.7
3.6
4.5
5.4
6.3
7.2
8.1
9
Load Current (A)
1.0V
1.2V
1.8V
3.3V
5.0V
10
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = 12V, Vcc = External 5V, Io = 0A‐9A, Fs = 600KHz, Room Temperature, No Air Flow. Note that the efficiency and power
loss curves include the losses of IR3899, the inductor losses and the losses of the input and output capacitors.
The table below shows the inductors used for each of the output voltages in the efficiency measurement.
VOUT (V)
LOUT (µH)
0.51
P/N
DCR (mΩ)
0.29
1.0
1.2
1.8
3.3
5
59PR9876N (Vitec)
59PR9876N (Vitec)
ETQP4LR68XFC (Panasonic)
MPL105‐1R2 (Delta)
MPL105‐1R2 (Delta)
0.51
0.29
0.68
1.58
1.2
2.9
1.2
2.9
97
95
93
91
89
87
85
83
81
0.9
1.8
2.7
3.6
4.5
5.4
6.3
7.2
8.1
9
Load Current (A)
1.0V
1.2V
1.8V
3.3V
5.0V
2.9
2.5
2.1
1.7
1.3
0.9
0.5
0.1
0.9
1.8
2.7
3.6
4.5
5.4
6.3
7.2
8.1
9
Load Current (A)
1.0V
1.2V
1.8V
3.3V
5.0V
11
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = 5.0V, Vcc = 5.0V, Io = 0A‐9A, Fs = 600KHz, Room Temperature, No Air Flow. Note that the efficiency and power loss
curves include the losses of IR3899, the inductor losses and the losses of the input and output capacitors.
The table below shows the inductors used for each of the output voltages in the efficiency measurement.
VOUT (V)
1.0
LOUT (µH)
0.4
P/N
DCR (mΩ)
0.29
59PR9875N (Vitec)
59PR9875N (Vitec)
59PR9876N (Vitec)
59PR9876N (Vitec)
1.2
0.4
0.29
1.8
0.51
0.29
3.3
0.51
0.29
97
95
93
91
89
87
85
83
0.9
1.8
2.7
3.6
4.5
5.4
6.3
7.2
8.1
9
Load Current (A)
1.0V
1.2V
1.8V
3.3V
2.9
2.5
2.1
1.7
1.3
0.9
0.5
0.1
0.9
1.8
2.7
3.6
4.5
5.4
6.3
7.2
8.1
9
Load Current (A)
1.0V
1.2V
1.8V
3.3V
12
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
THERMAL DERATING CURVES
Measurement done on Evaluation board of IRDC3899.PCB is 4 layer board with 2 oz Copper, FR4 material, size 2.23"x2"
PVin = 12V, Vout=1.2V, Vcc = Internal LDO (6.4V), Fs = 600kHz
10.5
10
9.5
9
8.5
Lout-0.51uH,0.29mΩ(Vitec 59PR9876N)
8
25
30
35
40
45
50
55
60
65
70
75
80
85
Tamb(ºC)
0 LFM
200 LFM
PVin = 12V, Vout=3.3V, Vcc = Internal LDO (6.4V), Fs = 600kHz
10.5
10
9.5
9
8.5
8
7.5
7
6.5
6
Lout-1.2uH,2.9mΩ(Delta MPL105-1R2)
25
30
35
40
45
50
55
60
65
70
75
80
85
Tamb(ºC)
0 LFM
200 LFM
Note: International Rectifier Corporation specifies current rating of SupIRBuck devices conservatively. The continuous current
load capability might be higher than the rating of the device if input voltage is 12V typical and switching frequency is below 750
kHz.The above derating curves are generated at 12V input ,600kHz with 0-200LFM air flow and ambient temperature up to
85°C.Detailed thermal derating information can be found in the Application Note AN-1174 “Thermal Derating of DC-DC
Convertors using IR3899/98/97”. However, the maximum current is limited by the internal current limit and designers need to
consider enough guard bands between load current and minimum current limit to guarantee that the device does not trip at
steady state condition.
13
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
RDSON OF MOSFETS OVER TEMPERATURE AT Vcc=6.4V
RDSON OF MOSFETS OVER TEMPERATURE AT Vcc=5.0V
14
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
TYPICAL OPERATING CHARACTERISTICS (‐40°C to +125°C)
15
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
TYPICAL OPERATING CHARACTERISTICS (‐40°C to +125°C)
Internal LDO in regulation
Internal LDO in dropout mode
With an External 5V Vcc Voltage
16
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
TYPICAL OPERATING CHARACTERISTICS (‐40°C to +125°C)
17
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
The POR (Power On Ready) signal is generated when all
these signals reach the valid logic level (see system block
diagram). When the POR is asserted the soft start
sequence starts (see soft start section).
THEORY OF OPERATION
DESCRIPTION
The IR3899 uses a PWM voltage mode control scheme with
external compensation to provide good noise immunity
and maximum flexibility in selecting inductor values and
capacitor types.
ENABLE
The Enable features another level of flexibility for start‐up.
The Enable has precise threshold which is internally
monitored by Under‐Voltage Lockout (UVLO) circuit.
Therefore, the IR3899 will turn on only when the voltage
at the Enable pin exceeds this threshold, typically, 1.2V.
The switching frequency is programmable from 300kHz
to 1.5MHz and provides the capability of optimizing the
design in terms of size and performance.
If the input to the Enable pin is derived from the bus
voltage by a suitably programmed resistive divider, it can
be ensured that the IR3899 does not turn on until the bus
voltage reaches the desired level (Fig. 4). Only after the bus
voltage reaches or exceeds this level and voltage at the
Enable pin exceeds its threshold, IR3899 will be enabled.
Therefore, in addition to being a logic input pin to enable
the IR3899, the Enable feature, with its precise threshold,
also allows the user to implement an Under‐Voltage
Lockout for the bus voltage (PVin). This is desirable
particularly for high output voltage applications, where we
might want the IR3899 to be disabled at least until PVIN
exceeds the desired output voltage level.
IR3899 provides precisely regulated output voltage
programmed via two external resistors from 0.5V to
0.86×Vin.
The IR3899 operates with an internal bias supply (LDO)
which is connected to the Vcc/LDO_out pin. This allows
operation with single supply. The bias voltage is variable
according to load condition. If the output load current is
less than half of the peak‐to‐peak inductor current, a lower
bias voltage, 4.4V, is used as the internal gate drive
voltage; otherwise, a higher voltage, 6.4V, is used. This
feature helps the converter to reduce power losses.
Pvin (12V)
The device can also be operated with an external supply
from 4.5 to 7.5V, allowing an extended operating input
voltage (PVin) range from 1.0V to 21V. For using the
internal LDO supply, the Vin pin should be connected to
PVin pin. If an external supply is used, it should be
connected to Vcc/LDO_Out pin and the Vin pin should be
shorted to Vcc/LDO_Out pin.
10. 2V
Vcc
The device utilizes the on‐resistance of the low side
MOSFET (synchronous MOSFET) for the over current
protection. This method enhances the converter’s
efficiency and reduces cost by eliminating the need for
external current sense resistor.
Enable
Enable Threshold=1.2V
Intl_SS
IR3899 includes two low Rds(on) MOSFETs using IR’s HEXFET
technology. These are specifically designed for high
efficiency applications.
Figure 4: Normal Start up, device turns on
when the bus voltage reaches 10.2V
UNDER‐VOLTAGE LOCKOUT AND POR
A resistor divider is used at EN pin from PVin to turn on the
device at 10.2V.
The under‐voltage lockout circuit monitors the voltage of
Vcc/LDO_out pin and the Enable input. It assures that the
MOSFET driver outputs remain in the off state whenever
either of these two signals drop below the set thresholds.
Normal operation resumes once Vcc/LDO_Out and Enable
rise above their thresholds.
18
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
Pvin(12V)
Figure 5a shows the recommended start‐up sequence for
the normal (non‐tracking, non‐sequencing) operation of
IR3899, when Enable is used as a logic input. Figure 5b
shows the recommended startup sequence for sequenced
operation of IR3899 with Enable used as logic input. Figure
5c shows the recommended startup sequence for tracking
operation of IR3899 with Enable used as logic input.
Vcc
Vp>1V
In normal and sequencing mode operation, Vref is left
floating. A 100pF ceramic capacitor is recommended
between this pin and Gnd. In tracking mode operation,
Vref should be tied to Gnd.
Enable >1.2V
Intl_SS
It is recommended to apply the Enable signal after the VCC
voltage has been established. If the Enable signal is present
before VCC, a 50kΩ resistor can be used in series with the
Enable pin to limit the current flowing into the Enable pin.
Figure 5a: Recommended startup for Normal operation
Pvin (12V)
PRE‐BIAS STARTUP
IR3899 is able to start up into pre‐charged output, which
prevents oscillation and disturbances of the output
voltage.
Vcc
The output starts in asynchronous fashion and keeps the
synchronous MOSFET (Sync FET) off until the first gate
signal for control MOSFET (Ctrl FET) is generated. Figure 6a
shows a typical Pre‐Bias condition at start up. The sync FET
always starts with a narrow pulse width (12.5% of a
switching period) and gradually increases its duty cycle
with a step of 12.5% until it reaches the steady state value.
The number of these startup pulses for each step is 16 and
it’s internally programmed. Figure 6b shows the series of
16x8 startup pulses.
Enable>1. 2V
Intl_SS
Vp
Figure 5b: Recommended startup for sequencing operation
(ratiometric or simultaneous)
[V]
Vo
Pre-Bias
Voltage
[Time]
Figure 6a: Pre‐Bias startup
...
HDRv
...
...
...
...
87.5%
12.5%
16
25%
...
LDRv
...
...
...
...
End of
PB
16
Figure 5c: Recommended startup for
memory tracking operation (VTT‐DDR4)
Figure 6b: Pre‐Bias startup pulses
19
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
TABLE 1: SWITCHING FREQUENCY (FS) VS. EXTERNAL RESISTOR (RT)
SOFT‐START
Rt (KΩ)
80.6
60.4
48.7
39.2
34
29.4
26.1
23.2
21
Freq (KHz)
300
IR3899 has an internal digital soft‐start to control the
output voltage rise and to limit the current surge at the
start‐up. To ensure correct start‐up, the soft‐start
sequence initiates when the Enable and Vcc rise above
their UVLO thresholds and generate the Power On Ready
(POR) signal. The internal soft‐start (Intl_SS) signal linearly
rises with the rate of 0.2mV/µs from 0V to 1.5V. Figure 7
shows the waveforms during soft start (also refer to Fig.
20). The normal Vout start‐up time is fixed, and is equal to:
400
500
600
700
800
900
1000
1100
1200
1300
1400
1500
0.65V-0.15V
2.5ms(1)
19.1
17.4
16.2
15
Tstart
0.2mV/s
During the soft start the over‐current protection (OCP) and
over‐voltage protection (OVP) is enabled to protect the
device for any short circuit or over voltage condition.
OVER CURRENT PROTECTION
POR
The over current (OC) protection is performed by sensing
current through the RDS(on) of the Synchronous MOSFET.
This method enhances the converter’s efficiency, reduces
cost by eliminating a current sense resistor and any layout
related noise issues. The current limit is pre‐set internally
and is compensated according to the IC temperature. So at
different ambient temperature, the over‐current trip
threshold remains almost constant.
3.0V
1.5V
0.65V
0.15V
Intl_SS
Note that the over current limit is a function of the Vcc
voltage. Refer to the typical performance curves of the
OCP current limit with the internal LDO and the external
Vcc voltage. Detailed operation of OCP is explained as
follows.
Vout
t1 t2
t3
Figure 7: Theoretical operation waveforms during
Over Current Protection circuit senses the inductor current
flowing through the Synchronous MOSFET closer to the
valley point. OCP circuit samples this current for 40nsec
typically after the rising edge of the PWM set pulse which
has a width of 12.5% of the switching period. The PWM
pulse starts at the falling edge of the PWM set pulse. This
makes valley current sense more robust as current is
sensed close to the bottom of the inductor downward
slope where transient and switching noise are lower and
helps to prevent false tripping due to noise and transient.
An OC condition is detected if the load current exceeds the
threshold, the converter enters into hiccup mode. PGood
will go low and the internal soft start signal will be pulled
low. The converter goes into hiccup mode with a 20.48ms
(typ.) delay as shown in Figure 8. The convertor stays in
this mode until the over load or short circuit is removed.
The actual DC output current limit point will be greater
than the valley point by an amount equal to approximately
soft‐start (non tracking / non sequencing)
OPERATING FREQUENCY
The switching frequency can be programmed between
300kHz – 1500kHz by connecting an external resistor from
Rt pin to Gnd. Table 1 tabulates the oscillator frequency
versus Rt.
SHUTDOWN
IR3899 can be shut down by pulling the Enable pin below
its 1.0V threshold. This will tri‐state both the high side and
the low side driver.
20
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
half of peak to peak inductor ripple current. The current
limit point will be a function of the inductor value, input
voltage, output voltage and the frequency of operation.
from Rt/Sync pin to Gnd is required to set the free‐running
frequency.
When an external clock is applied to Rt/Sync pin after the
converter runs in steady state with its free‐running
frequency, a transition from the free‐running frequency to
the external clock frequency will happen. This transition is
to gradually make the actual switching frequency equal to
the external clock frequency, no matter which one is
higher. On the contrary, when the external clock signal is
removed from Rt/Sync pin, the switching frequency is also
changed to free‐running gradually. In order to minimize
the impact from these transitions to output voltage, a
diode is recommended to add between the external clock
and Rt/Sync pin, as shown in Figure 9a. Figure 9b shows
the timing diagram of these transitions.
i
2
I
OCP ILIMIT
(2)
IOCP= DC current limit hiccup point
ILIMIT= Current limit Valley Point
Δi=Inductor ripple current
Figure 8: Timing Diagram for
Current Limit Hiccup
Figure 9a: Configuration of External Synchronization
THERMAL SHUTDOWN
Temperature sensing is provided inside IR3899. The trip
threshold is typically set to 145oC. When trip threshold is
exceeded, thermal shutdown turns off both MOSFETs and
resets the internal soft start.
Automatic restart is initiated when the sensed
temperature drops within the operating range. There is
a 20oC hysteresis in the thermal shutdown threshold.
Figure 9b: Timing Diagram for Synchronization
to the external clock (Fs1>Fs2 or Fs1<Fs2)
EXTERNAL SYNCHRONIZATION
IR3899 incorporates an internal phase lock loop (PLL)
circuit which enables synchronization of the internal
oscillator to an external clock. This function is important to
avoid sub‐harmonic oscillations due to beat frequency for
embedded systems when multiple point‐of‐load (POL)
regulators are used. A multi‐function pin, Rt/Sync, is used
to connect the external clock. If the external clock is
present before the converter turns on, Rt/Sync pin can be
connected to the external clock signal solely and no other
resistor is needed. If the external clock is applied after the
converter turns on, or the converter switching frequency
needs to toggle between the external clock frequency and
the internal free‐running frequency, an external resistor
An internal circuit is used to change the PWM ramp slope
according to the clock frequency applied on Rt/Sync pin.
Even though the frequency of the external synchronization
clock can vary in a wide range, the PLL circuit will make
sure that the ramp amplitude is kept constant, requiring no
adjustment of the loop compensation. Vin variation also
affects the ramp amplitude, which will be discussed
separately in Feed‐Forward section.
21
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
Vsw < 0 on LDrv falling edge (DCM=0), LDO output is
increased to 6.4V. A hysteresis band is added to Vsw
comparison to avoid chattering. Figure 11a shows the timing
diagram. Whenever device turns on, LDO always starts with
6.4V, then goes to 4.4V/6.4V depending upon the load
condition. For internally biased single rail operation, Vin pin
should be connected to PVin pin, as shown in Figure 11b. If
external bias voltage is used, Vin pin should be connected to
Vcc/LDO_Out pin, as shown in Figure 11c.
FEED‐FORWARD
Feed‐Forward (F.F.) is an important feature, because it
can keep the converter stable and preserve its load
transient performance when Vin varies in a large range.
In IR3899, F.F. function is enabled when Vin pin is
connected to PVin pin. In this case, the internal low
dropout (LDO) regulator is used. The PWM ramp
amplitude (Vramp) is proportionally changed with Vin to
maintain Vin/Vramp almost constant throughout Vin
variation range (as shown in Fig. 10). Thus, the control
loop bandwidth and phase margin can be maintained
constant. Feed‐forward function can also minimize
impact on output voltage from fast Vin change. The
maximum Vin slew rate is within 1V/µs.
...
IL
... ...
...
0
256/Fs
If an external bias voltage is used as Vcc, Vin pin should
be connected to Vcc/LDO_Out pin instead of PVin pin.
Then the F.F. function is disabled. A re‐calculation of
control loop parameters is needed for re‐compensation.
6.4V
Vcc/
LDO
6.4V
4.4V
0
Figure 11a: Time Diagram for Smart LDO
Figure 10: Timing Diagram for Feed‐Forward (F.F.) Function
Figure 11b: Internally Biased Single Rail Operation
SMART LOW DROPOUT REGULATOR (LDO)
IR3899 has an integrated low dropout (LDO) regulator
which can provide gate drive voltage for both drivers.
In order to improve overall efficiency over the entire
load range, LDO voltage is set to 6.4V (typ.) at mid‐ or
heavy load condition to reduce Rds(on) and thus
MOSFET conduction loss; and it is reduced to 4.4 (typ.)
at light load condition to reduce gate drive loss.
The smart LDO can select its output voltage according to
the load condition by sensing switch node (SW) voltage.
At light load condition when part of the inductor current
flows in the reverse direction (DCM=1), VSW > 0 on LDrv
falling edge in a switching cycle. If this case happens for
consecutive 256 switching cycles, the smart LDO
reduces its output to 4.4V. If in any one of the 256
cycles, Vsw < 0 on LDrv falling edge, the counter is reset
and LDO voltage doesn’t change. On the other hand, if
Figure 11c: Use External Bias Voltage
When the Vin voltage is below 6.8V, the internal LDO enters
the dropout mode at medium and heavy load. The dropout
voltage increases with the switching frequency. Figure 11d
22
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
shows the LDO voltage for 600 kHz and 1500 kHz
switching frequency respectively.
In sequencing mode of operation (simultaneous or
ratiometric), Vref is left floating and Vp is kept to ground level
until Intl_SS signal reaches the final value. Then Vp is ramped
up and Vfb follows Vp. When Vp>0.5V the error‐amplifier
switches to Vref and the output voltage is regulated with
Vref.The final Vp voltage after sequencing startup should
between 0.7V ~ 3.3V.
Figure 11d: LDO_Out Voltage in dropout mode
OUTPUT VOLTAGE TRACKING AND
SEQUENCING
IR3899 can accommodate user programmable tracking
and/or sequencing options using Vp, Vref, Enable, and
Power Good pins. In the block diagram presented on
page 3, the error‐amplifier (E/A) has been depicted with
three positive inputs. Ideally, the input with the lowest
voltage is used for regulating the output voltage and the
other two inputs are ignored. In practice the voltage of
the other two inputs should be about 200mV greater
than the low‐voltage input so that their effects can
completely be ignored. Vp is internally biased to 3.3V via
a high impedance path. For normal operation, Vp and
Vref is left floating (Vref should have a bypass
capacitor).
Figure 12: Application Circuit for Simultaneous
and Ratiometric Sequencing
Therefore, in normal operating condition, after Enable
goes high, the internal soft‐start (Intl_SS) ramps up the
output voltage until Vfb (voltage of feedback/Fb pin)
reaches about 0.5V. Then Vref takes over and the
output voltage is regulated.
Tracking and sequencing operations can be implemented to
be simultaneous or ratiometric (refer to Fig. 13 and 14).
Figure 12 shows typical circuit configuration for sequencing
operation. With this power‐up configuration, the voltage at
the Vp pin of the slave reaches 0.5V before the Fb pin of the
master. If RE/RF =RC/RD, simultaneous startup is achieved. That
is, the output voltage of the slave follows that of the master
until the voltage at the Vp pin of the slave reaches 0.5V. After
the voltage at the Vp pin of the slave exceeds 0.5V, the
internal 0.5V reference of the slave dictates its output
voltage. In reality the regulation gradually shifts from Vp to
internal Vref. The circuit shown in Fig. 12 can also be used for
simultaneous or ratiometric tracking operation if Vref of the
slave is connected to GND. Table 2 summarizes the required
conditions to achieve simultaneous/ratiometric tracking or
sequencing operations.
Tracking‐mode operation is achieved by connecting Vref
to GND. In tracking‐mode, Vfb always follows Vp, which
means Vout is always proportional to Vp voltage (typical
for DDR/VTT rail applications). The effective Vp variation
range is 0V~1.2V. Fig. 5c illustrates the start‐up of VTT
tracking for DDR4 application. Vp is proportional to
VDDQ. After Vp is established, asserting Enable initiates
the internal soft‐start. VTT, which is the output of POL,
starts to ramp up and tracks Vp.
23
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
Vcc
VREF
Vref=0.5V
This pin reflects the internal reference voltage which is used
by the error amplifier to set the output voltage. In most
operating conditions this pin is only connected to an external
bypass capacitor. A 100pF ceramic capacitor is recommended
for the bypass capacitor. To keep standby current to
minimum, Vref is not allowed to come up until EN starts going
high. In tracking mode this pin should be pulled to GND. For
margining applications, an external voltage source is
connected to Vref pin and overrides the internal reference
voltage. The external voltage source should have a low
internal resistance (<100Ω) and be able to source and sink
more than 25µA.
Enable (slave)
1.2V
Soft Start (slave)
Vo1 (master)
Vo1 (master)
(a)
Vo2 (slave)
Vo2 (slave)
(b)
Figure 13: Typical waveforms for sequencing mode of
operation: (a) simultaneous, (b) ratiometric
POWER GOOD OUTPUT (TRACKING,
SEQUENCING, VREF MARGINING)
Vcc
IR3899 continually monitors the output voltage via the sense
pin (Vsns) voltage. The Vsns voltage is an input to the window
comparator with upper and lower threshold of 0.6V and
0.45V respectively. PGood signal is high whenever Vsns
voltage is within the PGood comparator window thresholds.
The PGood pin is open drain and it needs to be externally
pulled high. High state indicates that output is in regulation.
Vref=0V (slave)
Enable (slave)
1.2V
Soft Start (slave)
Vo1 (master)
Vo2 (slave)
(a)
The threshold is set differently at different operating modes
and the results of the comparison sets the PGood signal.
Figures 15, 16, and 17 show the timing diagram of the PGood
signal at different operating modes. Vsns signal is also used by
OVP comparator for detecting output over voltage condition.
Vo1 (master)
(b)
Vo2 (slave)
Figure 14: Typical waveforms in tracking mode of operation:
(a) simultaneous, (b) ratiometric
TABLE 2: REQUIRED CONDITIONS FOR
SIMULTANEOUS/RATIOMETRIC TRACKING AND SEQUENCING (FIG.
12)
Operating
Mode
Vref
(Slave)
Vp
Required
Condition
Normal
0.5V
(Floating)
(Non‐sequencing,
Non‐tracking)
Simultaneous
Sequencing
Ratiometric
Sequencing
Simultaneous
Tracking
Floating
―
Ramp up
from 0V
Ramp up
from 0V
Ramp up
before En
Ramp up
before En
RA/RB>RE/
RF=RC/RD
RA/RB>RE/
RF>RC/RD
RE/RF
=RC/RD
RE/RF
0.5V
0.5V
0V
Figure 15: Non‐sequence, Non‐tracking Startup
and Vref Margin (Vp pin floating)
Ratiometric
Tracking
0V
>RC/RD
24
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
and Fig 18b. If either of the above conditions is not satisfied,
OVP is disabled. Vsns voltage is set by the voltage divider
connected to the output and it can be programmed
externally. Figure 18c shows the timing diagram for OVP in
non‐tracking mode.
0.4V
0.3V
Vp
0
1.2*Vp
0.9*Vp
Vsns
En
0
1.2V
PGood
1.0V
0
1.28ms
Vref
0.2V
Figure 16: Vp Tracking (Vref =0V)
OVP active region
Figure 18a: Activation of OVP in non‐tracking mode
Figure 17: Vp Sequence and Vref Margin
OVER‐VOLTAGE PROTECTION (OVP)
OVP is achieved by comparing Vsns voltage to an OVP
threshold voltage. In non‐tracking mode, OVP threshold
voltage is 1.2×Vref; in tracking mode, it is set at 1.2×Vp.
When Vsns exceeds the OVP threshold, an over voltage
trip signal asserts after 2us (typ.) delay. Then the control
FET is latched off immediately, PGood flags low. The
sync FET remains on to discharge the output capacitor.
When the Vsns voltage drops below the threshold, the
sync FET turns off to prevent the complete depletion of
the output capacitor. The control FET remains latched
off until user cycles either Vcc or Enable.
Figure 18b: Activation of OVP in tracking mode
OVP comparator becomes active only when the device is
enabled. Furthermore, for OVP to be active Vref has to
exceed 0.2V in non‐tracking mode, or Vp has to exceed
the threshold in tracking‐mode, as illustrated in Fig 18a
Figure 18c: Timing Diagram for OVP in non‐tracking mode
25
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
SOFT START/SOFT‐STOP (S_CTRL)
MINIMUM ON TIME CONSIDERATIONS
Soft‐stop function can make output voltage discharge
gradually. To enable this function, S_Ctrl is kept low first
when EN goes high. Then S_Ctrl is pulled high to cross
the logic level threshold (typ. 2V), the internal soft‐start
ramp is initiated. So Vo follows Intl_SS to ramp up until
it reaches its steady state. In soft‐stop process, S_Ctrl
needs to be pulled low before EN goes low. After S_Ctrl
goes below its threshold, a decreasing ramp is
generated at Intl_SS with the same slope as in soft‐start
ramp. Vo follows this ramp to discharge softly until
shutdown completely. Figure 19 shows the timing
diagram of S_Ctrl controlled soft‐start and soft‐stop.
The minimum ON time is the shortest amount of time for Ctrl
FET to be reliably turned on. This is very critical parameter for
low duty cycle, high frequency applications. Conventional
approach limits the pulse width to prevent noise, jitter and
pulse skipping. This results to lower closed loop bandwidth.
IR has developed a proprietary scheme to improve and
enhance minimum pulse width which utilizes the benefits of
voltage mode control scheme with higher switching
frequency, wider conversion ratio and higher closed loop
bandwidth, the latter results in reduction of output
capacitors. Any design or application using IR3899 must
ensure operation with a pulse width that is higher than this
minimum on‐time and preferably higher than 60 ns.
This is necessary for the circuit to operate without jitter and
pulse‐skipping, which can cause high inductor current ripple
and high output voltage ripple.
If the falling edge of Enable signal asserts before S_Ctrl
falling edge, the converter is still turned off by Enable.
Both gate drivers are turned off immediately and Vo
discharges to zero. Figure 20 shows the timing diagram
of Enable controlled soft‐start and soft‐stop. Soft stop
feature ensures that Vout discharges and also regulates
the current precisely to zero with no undershoot.
D
Vout
ton
(3)
F
V F
s
in
s
Enable
In any application that uses IR3899, the following condition
must be satisfied:
0
ton(min) ton(4)
S_Ctrl
0
Vout
ton(min)
(5)
(6)
0.65V
0.15V
0.65V
0.15V
Vin Fs
Intl
_SS
Vout
Vin Fs
0
ton(min)
Vout
0
The minimum output voltage is limited by the reference
voltage and hence Vout(min) = 0.5 V. Therefore, for
Figure 19: Timing Diagram for S_Ctrl controlled
Soft Start/Soft Stop
V
out(min) = 0.5 V,
Vout (min)
ton(min)
0.5 V
S_Ctrl
V Fs
in
0
V Fs
8.33 V/uS
in
60 ns
Enable
1.2V
1.0V
0
0
Therefore, at the maximum recommended input voltage 21V
and minimum output voltage, the converter should be
designed at a switching frequency that does not exceed 396
kHz. Conversely, for operation at the maximum
recommended operating frequency (1.65 MHz) and minimum
output voltage (0.5V). The input voltage (PVin) should not
exceed 5.05V, otherwise pulse skipping will happen.
0.65V
0.15V
Intl
_SS
Vout
0
Figure 20: Timing Diagram for Enable controlled
Soft Start/Shutdown
26
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
MAXIMUM DUTY RATIO
DESIGN EXAMPLE
A certain off‐time is specified for IR3899. This provides
an upper limit on the operating duty ratio at any given
switching frequency. The off‐time remains at a relatively
fixed ratio to switching period in low and mid frequency
range, while in high frequency range this ratio increases,
thus the lower the maximum duty ratio at which IR3899
can operate. Figure 21 shows a plot of the maximum
duty ratio vs. the switching frequency with built in input
voltage feed forward mechanism.
The following example is a typical application for IR3899. The
application circuit is shown in Fig.28.
V =12 V ( 10% )
in
Vo =1.2 V
Io = 9 A
Ripple Voltage= 1%*Vo
ΔVo
=
5% *Vo for 50% load transient)
F =600 kHz
s
Enabling the IR3899
As explained earlier, the precise threshold of the Enable lends
itself well to implementation of a UVLO for the Bus Voltage as
shown in Fig. 22.
Figure 21: Maximum duty cycle vs. switching frequency.
Figure 22: Using Enable pin for UVLO implementation
For a typical Enable threshold of VEN = 1.2 V
R2
V
*
VEN 1.2(7)
in(min)
R R2
1
VEN
1 Vin( min ) VEN
R2 R
(8)
For Vin (min)=9.2V, R1=49.9K and R2=7.5K ohm is a good choice.
Programming the frequency
For Fs = 600 kHz, select Rt = 39.2 KΩ, using Table 1.
Output Voltage Programming
Output voltage is programmed by reference voltage and
external voltage divider. The Fb pin is the inverting input of
the error amplifier, which is internally referenced to 0.5V.
The divider ratio is set to provide 0.5V at the Fb pin when the
output is at its desired value. The output voltage is defined by
using the following equation:
R5
R6
Vo Vref 1
(9)
27
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
When an external resistor divider is connected to the
output as shown in Fig. 23.
VIN
Cvin
+ VD
-
Boot
Vref
V
cc
R R
(10)
6
5
V o Vref
+
Vc
-
C1
For the calculated values of R5 and R6, see feedback
compensation section.
L
SW
IR3899
PGnd
Figure 24: Bootstrap circuit to generate Vc voltage
A bootstrap capacitor of value 0.1uF is suitable for most
applications.
Figure 23: Typical application of the IR3899
for programming the output voltage
Input Capacitor Selection
Bootstrap Capacitor Selection
The ripple current generated during the on time of the
control FET should be provided by the input capacitor. The
RMS value of this ripple is expressed by:
To drive the Control FET, it is necessary to supply a gate
voltage at least 4V greater than the voltage at the SW
pin, which is connected to the source of the Control FET.
This is achieved by using a bootstrap configuration,
which comprises the internal bootstrap diode and an
external bootstrap capacitor (C1). The operation of the
circuit is as follows: When the sync FET is turned on, the
capacitor node connected to SW is pulled down to
ground. The capacitor charges towards Vcc through the
internal bootstrap diode (Fig.24), which has a forward
voltage drop VD. The voltage Vc across the bootstrap
capacitor C1 is approximately given as:
IRMS Io D (1 D)(13)
V
D o (14)
V
in
Where:
D is the Duty Cycle
IRMS is the RMS value of the input capacitor current.
Io is the output current.
Vc Vcc VD(11)
For Io=9A and D = 0.1, the IRMS = 2.7A.
When the control FET turns on in the next cycle, the
capacitor node connected to SW rises to the bus voltage
Vin. However, if the value of C1 is appropriately chosen,
the voltage Vc across C1 remains approximately
unchanged and the voltage at the Boot pin becomes:
Ceramic capacitors are recommended due to their peak
current capabilities. They also feature low ESR and ESL at
higher frequency which enables better efficiency.
For this application, it is advisable to have 4x10uF, 25V
ceramic
capacitors,
C3216X5R1E106M
from
TDK.
In addition to these, although not mandatory,
a 1x330uF, 25V SMD capacitor EEV‐FK1E331P from Panasonic
may also be used as a bulk capacitor and is recommended if
the input power supply is not located close to the converter.
VBoot V Vcc VD(12)
in
Inductor Selection
The inductor is selected based on output power, operating
frequency and efficiency requirements. A low inductor value
causes large ripple current, resulting in the smaller size, faster
response to a load transient but poor efficiency and high
28
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
output noise. Generally, the selection of the inductor
Where:
ΔV0 = Output Voltage Ripple
ΔIL = Inductor Ripple Current
value can be reduced to the desired maximum ripple
current in the inductor (Δi). The optimum point is
usually found between 20% and 50% ripple of the
output current.
Since the output capacitor has a major role in the overall
performance of the converter and determines the result of
transient response, selection of the capacitor is critical. The
IR3899 can perform well with all types of capacitors.
For the buck converter, the inductor value for the
desired operating ripple current can be determined
using the following relation:
As a rule, the capacitor must have low enough ESR to meet
output ripple and load transient requirements.
i
1
Vin Vo L ; t D
t
Fs
(15)
The goal for this design is to meet the voltage ripple
requirement in the smallest possible capacitor size. Therefore
Vo
L V V
o
in
Vin i* Fs
it
is
advisable
to
select
ceramic
capacitors
due to their low ESR and ESL and small size. Six of TDK
C2012X5R0J226M (22uF/0805/X5R/6.3V) capacitors is
a good choice.
Where:
Vin = Maximum input voltage
V0 = Output Voltage
It is also recommended to use a 0.1µF ceramic capacitor at
the output for high frequency filtering.
Δi = Inductor Peak‐to‐Peak Ripple Current
Fs = Switching Frequency
Δt = On time for Control FET
D = Duty Cycle
Feedback Compensation
The IR3899 is a voltage mode controller. The control loop
is a single voltage feedback path including an error amplifier
and error comparator. To achieve fast transient response
and accurate output regulation, a compensation circuit is
necessary. The goal of the compensation network is to close
the control loop at high crossover frequency with phase
margin greater than 45o.
If Δi ≈ 40%*Io, then the output inductor is calculated to
be 0.5μH. Select L=0.51μH, 59PR9876N, from VITEC
which provides a compact, low profile inductor suitable
for this application.
Output Capacitor Selection
The voltage ripple and transient requirements
determine the output capacitors type and values.
The criteria is normally based on the value of the
Effective Series Resistance (ESR). However the actual
capacitance value and the Equivalent Series Inductance
The output LC filter introduces a double pole, ‐40dB/decade
gain slope above its corner resonant frequency, and a total
phase lag of 180o. The resonant frequency of the LC filter is
expressed as follows:
(ESL)
are
other
contributing
components.
1
These components can be described as:
FLC
(17)
2 Lo Co
V Vo(ESR) Vo(ESL) V
o
o(C)
Figure 25 shows gain and phase of the LC filter. Since we
already have 180o phase shift from the output filter alone,
the system runs the risk of being unstable.
Vo(ESR) IL *ESR
V V
o
in
Vo(ESL)
*ESL
L
(16)
IL
8*C *F
Vo(C)
o
s
29
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
Phase
00
Zf
Gain
Ve
1 sR3C
3 (19)
H(s)
Vout
ZIN
sR5C3
0dB
-40dB/Decade
Frequency
The (s) indicates that the transfer function varies as a function
of frequency. This configuration introduces a gain and zero,
expressed by:
-900
-1800
Frequency
FLC
R
FLC
H s
3 (20)
R5
Figure 25: Gain and Phase of LC filter
1
F
(21)
z
2 *R3 *C3
The IR3899 uses a voltage‐type error amplifier with
high‐gain (110dB) and high‐bandwidth (30MHz). The
output of the amplifier is available for DC gain control
and AC phase compensation.
First select the desired zero‐crossover frequency (Fo):
Fo FESR and F 1/5~1/10 * F (22)
o
s
The error amplifier can be compensated either in type II
or type III compensation. Type II compensation is shown
in Fig. 26. This method requires that the output
capacitors have enough ESR to satisfy stability
requirements. If the output capacitor’s ESR generates a
zero at 5kHz to 50kHz, the zero generates acceptable
phase margin and the Type II compensator can be used.
The ESR zero of the output capacitor is expressed as
follows:
Use the following equation to calculate R3:
Vosc *Fo *FESR *R
R3
5 (23)
V *FL2C
in
Where:
Vin = Maximum Input Voltage
osc = Amplitude of the oscillator Ramp Voltage
Fo = Crossover Frequency
ESR = Zero Frequency of the Output Capacitor
V
1
FESR
(18)
2π* ESR* Co
F
FLC = Resonant Frequency of the Output Filter
R5 = Feedback Resistor
VOUT
Z IN
CPOLE
To cancel one of the LC filter poles, place the zero before the
LC filter resonant frequency pole:
C3
R3
R5
R6
Z f
F 75 % *F
z
LC
Fb
1
E/A
Ve
F 0.75*
(24)
z
Comp
2 L *C
o
o
VREF
Gain(dB)
Use equation 21 to calculate C3.
H(s) dB
One more capacitor is sometimes added in parallel with C3
and R3. This introduces one more pole which is mainly used
to suppress the switching noise.
Frequency
FPOLE
FZ
The additional pole is given by:
Figure 26: Type II compensation network
and its asymptotic gain plot
1
FP
(25)
C3 *CPOLE
C3 CPOLE
2 *R3 *
The transfer function (Ve/Vout) is given by:
30
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
The pole sets to one half of the switching frequency
The compensation network has three poles and two zeros
and they are expressed as follows:
which results in the capacitor CPOLE
:
FP1 0(28)
1
1
CPOLE
(26)
1
1
* R 3 * Fs
* R 3 * Fs
FP2
FP3
(29)
C3
2 *R4 *C4
1
1
(30)
For a general solution for unconditional stability for any
type of output capacitors, and a wide range of ESR
values, we should implement local feedback with a type
III compensation network. The typically used
compensation network for voltage‐mode controller is
shown in Fig. 27.
2 *R3 *C2
C2 *C3
C2 C3
2 *R
3
1
FZ1
(31)
2 *R3 *C3
1
1
FZ 2
(32)
VOUT
ZIN
2 *C4 *(R4 R5 ) 2 *C4 * R5
C2
C3
C4
R4
R3
Crossover frequency is expressed as:
R5
R6
Zf
V
1
in
F R3 *C4 *
*
(33)
o
Vosc 2 *Lo *Co
Fb
Ve
E A
/
Comp
Based on the frequency of the zero generated by the output
capacitor and its ESR, relative to crossover frequency, the
compensation type can be different. Table 3 shows the
compensation types for relative locations of the crossover
frequency.
V
REF
Gain (dB)
|H(s)| dB
TABLE 3: DIFFERENT TYPES OF COMPENSATORS
Compensator
Type
Typical Output
Capacitor
Electrolytic
SP Cap, Ceramic
FESR vs FO
Frequency
Type II
Type III
FLC < FESR < FO < FS/2
FLC < FO < FESR
F
F
F
F
P3
P2
Z1
Z2
Figure 27: Type III Compensation network
and its asymptotic gain plot
The higher the crossover frequency is, the potentially faster
the load transient response will be. However, the crossover
frequency should be low enough to allow attenuation of
switching noise. Typically, the control loop bandwidth or
crossover frequency (Fo) is selected such that:
Again, the transfer function is given by:
Z f
Ve
H(s)
Vout
ZIN
Fo
1/5 ~1/10 *Fs
By replacing Zin and Zf, according to Fig. 27, the transfer
function can be expressed as:
The DC gain should be large enough to provide high DC
regulation accuracy. The phase margin should be greater than
45o for overall stability.
(1 sR3C3 ) 1 sC4 R R
5
4
3
C2 * C3
For this design we have:
Vin=12V
H (s)
sR (C C ) 1 sR
(1 sR C )
5
2
3
4
4
C2 C3
Vo=1.2V
(27)
31
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
Vosc=1.8V (This is a function of Vin, pls. see
feedforward section)
Vref=0.5V
2 *F *Lo *Co *V
o
R3
osc ;R3 1.57 kΩ
C4 *V
in
Lo=0.51uH
Co=6x22uF, ESR≈3mΩ each
Select R3 = 1.43 kΩ:
1
C3
; C3 10.2 nF, Select: C3 10 nF
; C2 360 pF, Select: C2 270 pF
It must be noted here that the value of the capacitance
used in the compensator design must be the small signal
value. For instance, the small signal capacitance of the
22uF capacitor used in this design is 10uF at 1.2 V DC
bias and 600 kHz frequency. It is this value that must be
used for all computations related to the compensation.
The small signal value may be obtained from the
manufacturer’s datasheets, design tools or SPICE
models. Alternatively, they may also be inferred from
measuring the power stage transfer function of the
converter and measuring the double pole frequency FLC
and using equation (17) to compute the small signal Co.
2*FZ1 * R3
1
C2
2 *FP3 *R3
Calculate R4, R5 and R6:
1
R4
; R4 106 Ω, Select: R4 100 Ω
2 *C4 * FP2
1
R5
- R4 ; R5 3.41 kΩ,
2 *C4 * FZ 2
These result in:
FLC=28.7 kHz
FESR=5.3 MHz
Select R5 = 3.32 kΩ:
Fs/2=300 kHz
Select crossover frequency F0=120 kHz
Vref
R6
*R5; R6 2.37 kΩ Select: R6 2.37 kΩ
Vo -Vref
Since FLC<F0<Fs/2<FESR, Type III is selected to place the
pole and zeros.
Setting the Power Good Threshold
Detailed calculation of compensation Type III:
In this design IR3899 is used in normal (non‐tracking,
non‐sequencing) mode, therefore the PGood thresholds are
internally set at 90% and 120% of Vref. At startup as soon as
Vsns voltage reaches 0.9*0.5V=0.45V (Fig. 15), and after
1.28ms delay, PGood signal is asserted. As long as the Vsns
voltage is between the threshold range, Enable is high, and no
fault happens, the PGood remains high.
Desired Phase Boost Θ = 70°
1sin
1sin
FZ 2 F
21.2 kHz
o
The following formula can be used to set the PGood
1sin
1sin
FP2 F
680.6 kHz
o
threshold. Vout (PGood_TH can be taken as 90% of Vout. Choose
)
R8=2.37KΩ.
Select:
Vout(PGood _TH )
R7 (
1)*R8
(34)
0.9*Vref
R7 3.32K
FZ1 0.5*FZ 2 10.6 kHzand
FP3 0.5*F 300 kHz
s
The PGood is an open drain output. Hence, it is necessary to
use a pull up resistor, RPG, from PGood pin to Vcc. The value
of the pull‐up resistor must be chosen such as to limit the
current flowing into the PGood pin to be less than 5mA when
the output voltage is not in regulation. A typical value used
is 49.9kΩ.
Select C4 = 2.2nF.
Calculate R3, C3 and C2:
32
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
OVP comparator also uses Vsns signal for over Voltage
dectection.With above values for R7 and R8, OVP trip
point (Vout_OVP) is
Vout _OVP Vref *1.2*(R7 R8) / R8 1.44V
(35)
Vref Bypass Capacitor
A 100pF bypass capacitor is recommended to be placed
between Vref and Gnd pins.This capacitor should be
placed as close as possible to Vref pin.
33
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
APPLICATION DIAGRAM
Figure 28: Application Circuit for a 12V to 1.2V, 9A Point of Load Converter
Suggested bill of materials for the application circuit: 12V to 1.2V
Part Reference
Qty
Value
Description
Manufacturer
Part Number
Cin
1206, 21V, X5R, 20%
4
10uF
TDK
C3216X5R1E106M
C1 C5 C6
Cref
C4
3
0.1uF
100pF
2200pF
270pF
22uF
0603, 25V, X7R, 10%
0603,50V,NP0, 5%
Murata
GRM188R71E104KA01B
GRM1885C1H101JA01D
1
Murata
1
0603,50V,X7R
Murata
Murata
GRM188R71H222KA01B
GRM1885C1H271JA01D
0603, 50V, NP0, 5%
C2
1
0805, 6.3V, X5R, 20%
0603, 16V, X5R, 20%
0603, 25V, X7R, 10%
0603, 25V, X5R, 10%
Co
6
TDK
TDK
C2012X5R0J226M
C1608X5R1C225M
GRM188R71E103KA01J
GRM188R61E105KA12D
59PR9876N
CVcc
C3
1
2.2uF
10nF
1
Murata
Cvin
Lo
1
1.0uF
0.51uH
1.43K
3.32K
2.37K
Murata
1
SMD 11.0x7.2x7.5mm,0.29mΩ
Vitec
Thick Film, 0603,1/10W,1%
R3
1
Panasonic
Panasonic
Panasonic
ERJ-3EKF1431V
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
R5 R7
R6 R8
2
ERJ-3EKF3321V
2
ERJ-3EKF2371V
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
R4
Rt
1
1
100
39.2K
Panasonic
Panasonic
ERJ-3EKF1000V
ERJ-3EKF3922V
R1 Rpg
R2
2
1
1
49.9K
7.5K
Panasonic
Panasonic
IR
ERJ-3EKF4992V
ERJ-3EKF7551V
IR3899MPBF
Thick Film, 0603,1/10W,1%
PQFN 4x5mm
U1
IR3899
34
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
Figure 29: Application Circuit for a 5V to 1V, 9A Point of Load Converter
Suggested bill of materials for the application circuit: 5V input to 1V output
Part Reference
Qty
Value
Description
Manufacturer
Part Number
Cin
1206, 21V, X5R, 20%
5
10uF
TDK
C3216X5R1E106M
C1 C5 C6
Cref
C4
3
0.1uF
100pF
2200pF
270pF
22uF
0603, 25V, X7R, 10%
0603,50V,NP0, 5%
Murata
GRM188R71E104KA01B
GRM1885C1H101JA01D
1
Murata
1
0603,50V,X7R
Murata
Murata
GRM188R71H222KA01B
GRM1885C1H271JA01D
0603, 50V, NP0, 5%
C2
1
0805, 6.3V, X5R, 20%
0603, 16V, X5R, 20%
0603, 50V, X7R, 10%
Co
6
TDK
TDK
TDK
Vitec
C2012X5R0J226M
C1608X5R1C225M
C1608X7R1H333K
59PR9875N
CVcc
C3
1
2.2uF
33nF
1
Lo
1
0.4uH
SMD 11.0x7.2x7.5mm,0.29mΩ
Thick Film, 0603,1/10W,1%
R3
1
4
1.1K
Panasonic
Panasonic
ERJ-3GEYJ112V
ERJ-3EKF3321V
Thick Film, 0603,1/10W,1%
R5 R6 R7 R8
3.32K
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
R4
Rt
1
1
100
39.2K
Panasonic
Panasonic
ERJ-3EKF1000V
ERJ-3EKF3922V
Rpg
U1
1
1
49.9K
Panasonic
IR
ERJ-3EKF4992V
IR3899MPBF
IR3899
PQFN 4x5mm
35
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
TYPICAL OPERATING WAVEFORMS
Vin = 12V, Vo = 1.2V, Iout = 0‐9A, Room Temperature, No Air Flow
Figure 30: Start up at 9A Load,
Ch1:Vin, Ch2:Vo, Ch3:PGood Ch4:Enable
Figure 31: Start up at 9A Load,
Ch1:Vin, Ch2:Vo, Ch3:Vcc, Ch4:PGood
Figure 32: Start up with 1V Pre Bias,
0A Load, Ch2:Vo
Figure 33: Output Voltage Ripple,
9A Load, Ch2:Vout
Figure 34: Inductor node at 9A load, Ch2:LX
Figure 35: Short Circuit Recovery,
Ch2‐Vout, Ch4:Iout (5A/Div)
36
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
TYPICAL OPERATING WAVEFORMS
Vin = 12V, Vo = 1.2V, Iout = 0‐9A, Room Temperature, No Air Flow
Figure 36: Turn on at No Load showing Vcc level
Ch1:Vin, Ch2:Vout, Ch3:Vcc, Ch4:Inductor current
Figure 37: Turn on at Full Load showing Vcc level
Ch1:Vin, Ch2:Vout, Ch3:Vcc, Ch4:Inductor current
38: Transient Response, 4.5A to 9A step at 2.5A/uSec slew rate,
Ch2:Vout, Ch4‐Iout (5A/Div)
37
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
TYPICAL OPERATING WAVEFORMS
Vin = 12V, Vo = 1.2V, Iout = 0‐9A, Room Temperature, No Air Flow
Figure 39: Bode Plot at 9A load shows a bandwidth of 115.6KHz and phase margin of 50.3 degrees
Figure 40: Thermal Image of the Board at 9A Load,
Test Point 1 is IR3899,
Test Point 2 is inductor
38
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
TYPICAL OPERATING WAVEFORMS
Vin = 12V, Vo = 1.2V, Iout = 0‐9A, Room Temperature, No Air Flow
Figure 41: Feed Forward for Vin change from 7 to 16V
Figure 42: Start/Stop using S‐Ctrl Pin, Ch1‐PGood,
Ch2‐Vout, Ch3‐S_Ctrl, Ch4‐EN
and back to 7V, Ch2‐Vout, Ch3‐Vin
Figure 43: External Frequency Synchronization to
800KHz from free running 600KHz, Ch1‐LX, Ch2‐Vout,
Ch4‐Rt/Sync Voltage
Figure 44: Over Voltage protection,
Ch2‐Vout, Ch3‐PGood
Figure 45: Voltage Margining using Vref Pin,
Figure 46: Voltage Tracking using Vp Pin,
Ch2‐Vout, Ch3‐Vref, Ch4‐PGood
Ch2‐Vout, Ch3‐Vp, Ch4‐PGood
39
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
The critical bypass components such as capacitors for Vin,
Vcc and Vref should be close to their respective pins. It is
important to place the feedback components including
feedback resistors and compensation components close to
Fb and Comp pins.
LAYOUT RECOMMENDATIONS
The layout is very important when designing high
frequency switching converters. Layout will affect noise
pickup and can cause a good design to perform with less
than expected results.
In a multilayer PCB use one layer as a power ground plane
and have a control circuit ground (analog ground), to which
all signals are referenced. The goal is to localize the high
current path to a separate loop that does not interfere
with the more sensitive analog control function. These two
grounds must be connected together on the PC board
layout at a single point. It is recommended to place all
the compensation parts over the analog ground plane in
top layer.
Make the connections for the power components in the
top layer with wide, copper filled areas or polygons. In
general, it is desirable to make proper use of power planes
and polygons for power distribution and heat dissipation.
The inductor, output capacitors and the IR3899 should be
as close to each other as possible. This helps to reduce the
EMI radiated by the power traces due to the high switching
currents through them. Place the input capacitor directly
at the PVin pin of IR3899.
The Power QFN is a thermally enhanced package. Based on
thermal performance it is recommended to use at least a
4‐layers PCB. To effectively remove heat from the device
the exposed pad should be connected to the ground plane
using vias. Figures 46a‐d illustrates the implementation of
the layout guidelines outlined above, on the IRDC3899 4‐
layer demo board.
The feedback part of the system should be kept away from
the inductor and other noise sources.
Enough copper &
minimum ground length
path between Input and
Output
All bypass caps
should be placed
as close as possible
to their connecting pins
Compensation parts
should be placed
as close as possible
to the Comp pin
Resistor Rt and Vref
decoupling cap should
be placed as close as
possible to their pins
SW node copper is
kept only at the top
layer to minimize
the switching noise
Figure 47a: IRDC3899 Demo board Layout Considerations – Top Layer
40
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
Single point connection
between AGND & PGND,
should be close to the
SupIRBuck kept away from
noise sources
Feedback and Vsns trace
routing should be kept away
from noise sources
Figure 47b: IRDC3899 Demo board Layout Considerations – Bottom Layer
Analog Ground Plane
Power Ground Plane
Figure 47c: IRDC3899 Demo board Layout Considerations – Mid Layer 1
Figure 47d: IRDC3899 Demo board Layout Considerations – Mid Layer 2
41
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
PCB METAL AND COMPONENT PLACEMENT
and processes, and experiments should be run to confirm
the limits of self‐centering on specific processes.
For further information, please refer to “SupIRBuck™
Multi‐Chip Module (MCM) Power Quad Flat No‐Lead
(PQFN) Board Mounting Application Note.” (AN1132)
Evaluations have shown that the best overall
performance is achieved using the substrate/PCB layout
as shown in following figures. PQFN devices should be
placed to an accuracy of 0.050mm on both X and Y axes.
Self‐centering behavior is highly dependent on solders
Figure 48: PCB Metal Pad Spacing (all dimensions in mm)
* Contact International Rectifier to receive an electronic PCB Library file in your preferred format
42
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
SOLDER RESIST
However, for the smaller Signal type leads around
the edge of the device, IR recommends that these
are Non Solder Mask Defined or Copper Defined.
IR recommends that the larger Power or Land
Area pads are Solder Mask Defined (SMD.)
This allows the underlying Copper traces to be as
large as possible, which helps in terms of current
carrying capability and device cooling capability.
When using NSMD pads, the Solder Resist
Window should be larger than the Copper Pad
by at least 0.025mm on each edge, (i.e. 0.05mm
in X&Y,) in order to accommodate any layer to
layer misalignment.
When using SMD pads, the underlying copper
traces should be at least 0.05mm larger (on each
edge) than the Solder Mask window, in order to
accommodate any layer to layer misalignment.
(i.e. 0.1mm in X & Y.)
Ensure that the solder resist in‐between the
smaller signal lead areas are at least 0.15mm
wide, due to the high x/y aspect ratio of the
solder mask strip.
Figure 49: Solder resist
* Contact International Rectifier to receive an electronic PCB Library file in your preferred format
43
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
STENCIL DESIGN
Evaluations have shown that the best overall
performance is achieved using the stencil design
shown in following figure. This design is for
Stencils for PQFN can be used with thicknesses
of 0.100‐0.250mm (0.004‐0.010"). Stencils thinner
than 0.100mm are unsuitable because they
deposit insufficient solder paste to make good
solder joints with the ground pad; high reductions
sometimes create similar problems. Stencils in
the range of 0.125mm‐0.200mm (0.005‐0.008"),
with suitable reductions, give the best results.
a
stencil thickness of 0.127mm (0.005").
The reduction should be adjusted for stencils
of other thicknesses.
Figure 50: Stencil Pad Spacing (all dimensions in mm)
* Contact International Rectifier to receive an electronic PCB Library file in your preferred format
44
JANUARY 18, 2013 |DATA SHEET | 3.6
‐
9A Highly Integrated SupIRBuckTM
Single‐Input Voltage, Synchronous Buck Regulator
IR3899
MARKING INFORMATION
Figure 51: Marking Information
Figure 52: Package Dimensions
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been designed and qualified for the Industrial market
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 12/11
45
JANUARY 18, 2013 |DATA SHEET | 3.6
相关型号：
©2020 ICPDF网 联系我们和版权申明