IRDC3840W [INFINEON]
USER GUIDE FOR IR3840W EVALUATION BOARD; 用户指南IR3840W评估板
| 型号： | IRDC3840W |
| 厂家： | 
Infineon |
| 描述： | USER GUIDE FOR IR3840W EVALUATION BOARD |
| 文件： | 总17页 (文件大小：853K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IRDC3840W
TM
SupIRBuck
USER GUIDE FOR IR3840W EVALUATION BOARD
DESCRIPTION
An output over-current protection function is
implemented by sensing the voltage developed
across the on-resistance of the synchronous
rectifier MOSFET for optimum cost and
performance.
The IR3840W is a synchronous buck
converter, providing compact, high
performance and flexible solution in a small
5mmx6mm Power QFN package.
a
Key features offered by the IR3840W
include programmable soft-start ramp,
precision 0.7V reference voltage, Power
This user guide contains the schematic and bill
of materials for the IR3840W evaluation board.
The guide describes operation and use of the
evaluation board itself. Detailed application
information for IR3840W is available in the
IR3840W data sheet.
Good, thermal protection, programmable
switching frequency, Sequence input,
Enable input, input under-voltage lockout for
proper start-up, and pre-bias start-up.
BOARD FEATURES
• Vin = +12V (13.2V Max)
• Vcc=+5V (5.5V Max)
• Vout = +1.8V @ 0- 12A
• Fs=600kHz
• L= 0.6uH
• Cin= 4x10uF (ceramic 1206) + 330uF (electrolytic)
• Cout= 6x22uF (ceramic 0805)
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IRDC3840W
CONNECTIONS and OPERATING INSTRUCTIONS
A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum 12A load should be
connected to VOUT+ and VOUT-. The connection diagram is shown in Fig. 1 and inputs and outputs of the
board are listed in Table I.
IR3840W has two input supplies, one for biasing (Vcc) and the other as input voltage (Vin). Separate
supplies should be applied to these inputs. Vcc input should be a well regulated 4.5V-5.5V supply and it
would be connected to Vcc+ and Vcc-.
If single 12V application is required connect R7 (zero Ohm resistor) which enables the on board bias
regulator (see schematic). In this case there is no need of external Vcc supply.
The output can track a sequencing input at the start-up. For sequencing application, R16 should be
removed and the external sequencing source should be applied between Seq. and Agnd. The value of R14
and R28 can be selected to provide the desired ratio between the output voltage and the tracking input. For
proper operation of IR3840W, the voltage at Seq. pin should not exceed Vcc.
Table I. Connections
Connection
VIN+
Signal Name
Vin (+12V)
VIN-
Ground of Vin
Vcc input
Vcc+
Vcc-
Ground for Vcc input
Ground of Vout
Vout (+1.8V)
VOUT-
VOUT+
Enable
Seq.
Enable
Sequence Input
Power Good Signal
P_Good
LAYOUT
The PCB is a 4-layer board. All of layers are 2 Oz. copper. The IR3840W SupIRBuck and all of the
passive components are mounted on the top side of the board.
Power supply decoupling capacitors, the Bootstrap capacitor and feedback components are located
close to IR3840W. The feedback resistors are connected to the output voltage at the point of regulation
and are located close to the SupIRBuck. To improve efficiency, the circuit board is designed to
minimize the length of the on-board power ground current path.
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IRDC3840W
Connection Diagram
Vin
GND
Enable
GND
Vo
Seq
AGND
Vcc GND
SS
PGood
Fig. 1: Connection diagram of IR384xW evaluation boards
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IRDC3840W
Fig. 2: Board layout, top overlay
Fig. 3: Board layout, bottom overlay (rear view)
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IRDC3840W
PGND
Plane
Single point
connection
between AGND
and PGND.
AGND
Plane
Fig. 4: Board layout, mid-layer I.
Fig. 5: Board layout, mid-layer II.
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IRDC3840W
2
1
1
1
1
n d G 1 A
1 5
t o B o
E n
c
V c
1 3
1 4
9
8
o o G d P
1
1
1
1
1
1
1
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IRDC3840W
Bill of Materials
Item Quantity Part Reference
Value
Description
Manufacturer
Part Number
1
1 C1
330uF
SMD Elecrolytic, Fsize, 25V, 20% Panasonic
EEV-FK1E331P
2
3
1 C34
4 C3 C4 C5 C2
10uF
10uF
0805, 10V, X5R, 20%
1206, 16V, X5R, 20%
Panasonic - ECG
Panasonic - ECG
ECJ-GVB1A106M
ECJ-3YB1C106M
4
5
6
6 C7 C10 C13 C14 C24 C32 0.1uF
0603, 25V, X7R, 10%
0603, 50V, NP0, 5%
0603, 50V, NP0, 5%
Panasonic - ECG
Murata
Panasonic- ECG
ECJ-1VB1E104K
GRM1885C1H222JA01D
ECJ-1VC1H221J
1 C8
2200pF
220pF
1 C11
C15 C16 C17 C18 C19 C20
7
8
9
6
22uF
0805, 6.3V, X5R, 20%
0603, 50V, X7R, 10%
MM3Z5V6B,Zener, 5.6V
11.5x10x4mm, 20%, 1.7mOhm
Panasonic- ECG
Panasonic - ECG
Fairchild
Delta
ECJ-2FB0J226M
ECJ-1VB1H103K
MM3Z5V6B
1 C26
1 D1
1 L1
10000pF
MM3Z5V6B
0.6uH
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
MPL104-0R6IR
1 Q1
1 R5
1 R18
1 R4
1 R6
1 R9
1 R16
1 R12
1 R17
1 R19
1 R1
1 R2
1 R3
1 U1
MMBT3904/SOT NPN, 40V, 200mA, SOT-23
Fairchild
Rohm
Rohm
Panasonic - ECG
Vishey/Dale
Rohm
Vishay/Dale
Rohm
Rohm
Rohm
Rohm
Rohm
MMBT3904/SOT
3.3k
49.9k
130
20
23.7k
0
2.15k
10.0k
7.50k
1.87k
3.92k
2.49k
IR3840W
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10 W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10 W,5%
Thick Film, 0603,1/10 W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
MCR03EZPFX3301
MCR03EZPFX4992
ERJ-3EKF1300V
CRCW060320R0FKEA
MCR03EZPFX2372
CRCW06030000Z0EA
MCR03EZPFX2151
MCR03EZPFX1002
MCR03EZPFX7501
MCR03EZPFX1871
MCR03EZPFX3921
MCR03EZPFX2491
Rohm
PQFN, 6mmx5mm, 12A SupIRBuck International Rectifier IR3840WMPbF
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IRDC3840W
TYPICAL OPERATING WAVEFORMS
Vin=12.0V, Vcc=5V, Vo=1.8V, Io=0-12A, Room Temperature, No Air Flow
Fig. 7: Start up at 12A Load
Ch1:Vin, Ch2:Vo, Ch3:Vss, Ch4:Enable
Fig. 8: Start up at 12A Load,
Ch1:Vin, Ch2:Vo, Ch3:Vss, Ch4:VPGood
Fig. 10: Output Voltage Ripple, 12A load
Ch2: Vout
Fig. 9: Start up with 1.62V Pre Bias, 0A
Load, Ch2:Vo, Ch3:VSS
Fig. 12: Short (Hiccup) Recovery
Ch1:Vout , Ch3:Vss
Fig. 11: Inductor node at 12A load
Ch2:LX
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IRDC3840W
TYPICAL OPERATING WAVEFORMS
Vin=12V, Vcc=5V, Vo=1.8V, Io=0-12A, Room Temperature, No Air Flow
Fig. 13: Transient Response, 6A to 12A step 2.5A/s
Ch2:Vout, Ch4:Iout
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IRDC3840W
TYPICAL OPERATING WAVEFORMS
Vin=12V, Vcc=5V, Vo=1.8V, Io=12A, Room Temperature, No Air Flow
Fig. 14: Bode Plot at 12A load shows a bandwidth of 99kHz and phase margin of 54 degrees
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IRDC3840W
TYPICAL OPERATING WAVEFORMS
Vin=12V, Vo=1.8V, Io=0- 12A, Room Temperature, No Air Flow
93.0
92.5
92.0
91.5
91.0
90.5
90.0
89.5
89.0
88.5
88.0
87.5
10
20
30
40
50
60
70
80
90
100
Load Percentage (%)
Fig.15: Efficiency versus load current
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
10
20
30
40
50
60
70
80
90
100
Load Percentage(%)
Fig.16: Power loss versus load current
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IRDC3840W
THERMAL IMAGES
Vin=12V, Vo=1.8V, Io=12A, Room Temperature, No Air Flow
Fig. 17: Thermal Image at 12A load
Test points 1 and 2 are IR3840W and inductor, respectively.
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IRDC3840W
Simultaneous Tracking at Power Up and Power Down
Vin=12V, Vo=1.8V, Io=12A, Room Temperature, No Air Flow
In order to run the IR3840W in the simultaneous tracking mode, following steps should be
taken:
- Remove R16 from the board.
- Set the value of R14 and R28 as R2 (3.92K) and R3 (2.49K), respectively.
- Connect the controlling input across SEQ and AGND test points on the board. This voltage
should be at least 1.15 time greater than Vo. For the following test results a 0-3.3V source is
applied to SEQ input.
- The controlling input should be applied after the SS pin is clamped to 3.0V.
Fig. 18: Simultaneous Tracking a 3.3V input at power-up and shut-down
Ch2: SS (1.8V) Ch3:Vo Ch4: SEQ
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IRDC3840W
PCB Metal and Components Placement
The lead lands (the 11 IC pins) width should be equal to the nominal part lead width. The minimum
lead to lead spacing should be ≥ 0.2mm to minimize shorting.
Lead land length should be equal to the maximum part lead length + 0.3 mm outboard extension. The
outboard extension ensures a large and inspectable toe fillet.
The pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal to
maximum part pad length and width. However, the minimum metal to metal spacing should be no less
than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper and no less than 0.23mm for 3 oz.
Copper.
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IRDC3840W
Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist
should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD
pads.
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist
onto the copper of 0.05mm to accommodate solder resist mis-alignment.
Ensure that the solder resist in between the lead lands and the pad land is ≥ 0.15mm due to the
high aspect ratio of the solder resist strip separating the lead lands from the pad land.
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IRDC3840W
Stencil Design
•
The Stencil apertures for the lead lands should be approximately 80% of the area of the
lead lads. Reducing the amount of solder deposited will minimize the occurrences of lead
shorts. If too much solder is deposited on the center pad the part will float and the lead
lands will be open.
•
The maximum length and width of the land pad stencil aperture should be equal to the
solder resist opening minus an annular 0.2mm pull back to decrease the incidence of
shorting the center land to the lead lands when the part is pushed into the solder paste.
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IRDC3840W
BOTTOM VIEW
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been designed and qualified for the Consumer market.
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 11/07
10/09/2009
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