IRF1018ES [INFINEON]
60V 单个 N 通道 HEXFET Power MOSFET, 采用 D2-Pak 封装;
| 型号： | IRF1018ES |
| 厂家： | 
Infineon |
| 描述： | 60V 单个 N 通道 HEXFET Power MOSFET, 采用 D2-Pak 封装 |
| 文件： | 总12页 (文件大小：438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 97125
IRF1018EPbF
IRF1018ESPbF
IRF1018ESLPbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in
D
S
SMPS
VDSS
RDS(on) typ.
max.
60V
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
7.1m
8.4m
:
:
G
ID
79A
Benefits
l Improved Gate, Avalanche and Dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche SOA
D
D
D
l Enhanced body diode dV/dt and dI/dt
Capability
S
S
S
D
D
D
G
G
G
D2Pak
IRF1018ESPbF
TO-262
IRF1018ESLPbF
TO-220AB
IRF1018EPbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Parameter
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current c
Max.
79
Units
56
A
315
110
0.76
± 20
21
PD @TC = 25°C
Maximum Power Dissipation
Linear Derating Factor
W
W/°C
V
VGS
Gate-to-Source Voltage
Peak Diode Recovery e
dv/dt
TJ
V/ns
°C
-55 to + 175
Operating Junction and
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
300
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw k
Avalanche Characteristics
Single Pulse Avalanche Energy d
EAS (Thermally limited)
88
47
11
mJ
A
Avalanche Current c
IAR
Repetitive Avalanche Energy f
EAR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
Units
RθJC
RθCS
RθJA
RθJA
Junction-to-Case j
1.32
–––
62
Case-to-Sink, Flat Greased Surface , TO-220
Junction-to-Ambient, TO-220 j
Junction-to-Ambient (PCB Mount) , D2Pak ij
0.50
–––
°C/W
–––
40
www.irf.com
1
2/28/08
IRF1018E/S/SLPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max. Units
60 ––– –––
––– 0.073 ––– V/°C Reference to 25°C, ID = 5mAc
Conditions
VGS = 0V, ID = 250μA
V
ΔV(BR)DSS/ΔTJ
RDS(on)
–––
2.0
7.1
8.4
4.0
20
VGS = 10V, ID = 47A f
VDS = VGS, ID = 100μA
mΩ
V
VGS(th)
–––
IDSS
Drain-to-Source Leakage Current
––– –––
μA VDS = 60V, VGS = 0V
––– ––– 250
––– ––– 100
––– ––– -100
VDS = 48V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
nA
VGS = 20V
VGS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
110 ––– –––
Conditions
VDS = 50V, ID = 47A
S
Qg
–––
–––
–––
–––
–––
46
10
12
34
69
nC ID = 47A
VDS = 30V
Qgs
Gate-to-Source Charge
–––
–––
–––
Qgd
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Internal Gate Resistance
Turn-On Delay Time
VGS = 10V f
Qsync
ID = 47A, VDS =0V, VGS = 10V
RG(int)
0.73 –––
Ω
td(on)
–––
–––
–––
–––
13
35
55
46
–––
–––
–––
–––
ns VDD = 39V
ID = 47A
tr
Rise Time
td(off)
Turn-Off Delay Time
RG = 10Ω
VGS = 10V f
VGS = 0V
tf
Fall Time
Ciss
Input Capacitance
––– 2290 –––
––– 270 –––
––– 130 –––
––– 390 –––
––– 630 –––
Coss
Output Capacitance
VDS = 50V
pF ƒ = 1.0MHz
Crss
Reverse Transfer Capacitance
Effective Output Capacitance (Energy Related)h
Effective Output Capacitance (Time Related)g
Coss eff. (ER)
Coss eff. (TR)
VGS = 0V, VDS = 0V to 60V h
VGS = 0V, VDS = 0V to 60V g
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
––– –––
A
MOSFET symbol
79
D
S
(Body Diode)
Pulsed Source Current
showing the
integral reverse
G
ISM
––– ––– 315
(Body Diode)ꢁc
p-n junction diode.
VSD
trr
Diode Forward Voltage
––– –––
1.3
39
V
TJ = 25°C, IS = 47A, VGS = 0V f
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 51V,
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
–––
–––
–––
26
31
24
35
1.8
ns
IF = 47A
di/dt = 100A/μs f
47
Qrr
36
nC
53
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
–––
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.08mH
RG = 25Ω, IAS = 47A, VGS =10V. Part not recommended for
use above this value.
ISD ≤ 47A, di/dt ≤ 1668A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
ꢀ Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
.
.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
This is only applied to TO-220
2
www.irf.com
IRF1018E/S/SLPbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
4.5V
≤60μs PULSE WIDTH
Tj = 25°C
≤60μs PULSE WIDTH
Tj = 175°C
1
1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
2.5
2.0
1.5
1.0
0.5
I
= 47A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
V
J
1
= 25V
DS
≤60μs PULSE WIDTH
0.1
2
3
4
5
6
7
8
9
-60 -40 -20 0 20 40 60 80 100120140160180
, Junction Temperature (°C)
T
V
, Gate-to-Source Voltage (V)
GS
J
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
4000
3000
2000
1000
0
V
C
= 0V,
f = 1 MHZ
GS
16
= C + C , C SHORTED
I = 47A
D
iss
gs
gd ds
C
= C
rss
gd
V
V
V
= 48V
= 30V
= 12V
DS
DS
DS
C
= C + C
oss
ds
gd
12
8
C
iss
4
C
oss
C
rss
0
1
10
100
0
10
20
30
40
50
60
V
, Drain-to-Source Voltage (V)
Q
Total Gate Charge (nC)
DS
G
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
www.irf.com
3
IRF1018E/S/SLPbF
1000
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100
T
= 175°C
J
1msec
100μsec
10
1
T
= 25°C
J
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
DC
10
GS
0.1
0.1
0.1
1
100
0.0
0.5
1.0
1.5
2.0
V
, Drain-toSource Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode Forward Voltage
80
80
Id = 5mA
60
40
20
0
75
70
65
60
25
50
75
100
125
150
175
-60 -40 -20 0 20 40 60 80 100120140160180
T
, CaseTemperature (°C)
C
T
, Temperature ( °C )
J
Fig 10. Drain-to-Source Breakdown Voltage
Fig 9. Maximum Drain Current vs. Case Temperature
0.8
400
I
D
350
300
250
200
150
100
50
TOP
5.3A
11A
47A
0.6
0.4
0.2
0.0
BOTTOM
0
0
10
V
20
30
40
50
60
25
50
75
100
125
150
175
Drain-to-Source Voltage (V)
Starting T , Junction Temperature (°C)
DS,
J
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
Fig 11. Typical COSS Stored Energy
4
www.irf.com
IRF1018E/S/SLPbF
10
1
D = 0.50
0.20
0.10
0.05
R1
R1
R2
R2
R3
R3
R4
R4
τι (sec)
Ri (°C/W)
0.1
τJ
0.026741 0.000007
0.28078 0.000091
0.606685 0.000843
0.406128 0.005884
τC
τJ
τ1
τ
τ
τ
3τ3
τ4
2 τ2
0.02
0.01
τ1
τ4
Ci= τi/Ri
0.01
0.001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
10
1
Allowed avalanche Current vs avalanche
Duty Cycle = Single Pulse
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
100
80
60
40
20
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
TOP
BOTTOM 10% Duty Cycle
= 47A
Single Pulse
I
D
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Starting T , Junction Temperature (°C)
J
Fig 15. Maximum Avalanche Energy vs. Temperature
www.irf.com
5
IRF1018E/S/SLPbF
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
14
12
10
8
I
I
I
I
= 1.0A
D
D
D
D
I
= 32A
= 51V
F
= 1.0mA
= 250μA
= 100μA
V
R
T = 25°C
J
T = 125°C
J
6
4
2
0
-75 -50 -25
0
25 50 75 100 125 150 175
, Temperature ( °C )
0
200
400
600
800
1000
T
J
di /dt (A/μs)
F
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
14
12
10
8
320
280
240
200
160
120
80
I
= 47A
= 51V
I
= 32A
V = 51V
R
F
F
V
R
T = 25°C
T = 25°C
J
J
T = 125°C
J
T = 125°C
J
6
4
2
40
0
0
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt (A/μs)
di /dt (A/μs)
F
F
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
320
I
= 47A
= 51V
F
280
240
200
160
120
80
V
R
T = 25°C
J
T = 125°C
J
40
0
0
200
400
600
800
1000
di /dt (A/μs)
F
Fig. 20 - Typical Stored Charge vs. dif/dt
6
www.irf.com
IRF1018E/S/SLPbF
Driver Gate Drive
P.W.
P.W.
D =
Period
D.U.T
Period
+
V***
=10V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
-
+
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
*
VDD
**
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Curent
I
SD
Ripple ≤ 5%
* Use P-Channel Driver for P-Channel Measurements
** Reverse Polarity for P-Channel
*** VGS = 5V for Logic Level Devices
Fig 21. Diode Reverse Recovery Test Circuit for HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
GS
0.01
Ω
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
VDS
90%
VGS
D.U.T.
RG
+VDD
-
10%
VGS
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
td(off)
tr
tf
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
0
Vgs(th)
20K
Qgs1
Qgs2
Qgodr
Qgd
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
www.irf.com
7
IRF1018E/S/SLPbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
EXAMPLE: THIS IS AN IRF1010
LOT CODE 1789
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLED ON WW 19, 2000
IN THE ASSEMBLY LINE "C"
DATE CODE
YEAR 0 = 2000
WEEK 19
Note: "P" in assembly line position
indicates "L ead - F ree"
ASSEMBLY
LOT CODE
LINE C
TO-220AB packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
8
www.irf.com
IRF1018E/S/SLPbF
TO-262 Package Outline (Dimensions are shown in millimeters (inches))
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
PART NUMBER
INTERNATIONAL
ASSEMBLED ON WW 19, 1997
RECTIFIER
IN THE ASSEMBLY LINE "C"
LOGO
DATE CODE
YEAR 7 = 1997
WEEK 19
ASSEMBLY
LOT CODE
LINE C
OR
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
DATE CODE
P = DE S IGNAT E S L E AD-F R E E
PRODUCT (OPTIONAL)
YEAR 7 = 1997
ASSEMBLY
LOT CODE
WEE K 19
A = AS S E MB L Y S IT E CODE
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
www.irf.com
9
IRF1018E/S/SLPbF
D2Pak Package Outline (Dimensions are shown in millimeters (inches))
D2Pak Part Marking Information
THIS IS AN IRF530S WITH
PART NUMBER
LOT CODE 8024
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
F530S
DATE CODE
YEAR 0 = 2000
WEEK 02
ASSEMBLY
LOT CODE
LINE L
THIS IS AN IRF530S WITH
LOT CODE 8024
PART NUMBER
DATE CODE
INTERNATIONAL
RECTIFIER
LOGO
For GB Production
ASSEMBLED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
F530S
LOT CODE
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
10
www.irf.com
IRF1018E/S/SLPbF
D2Pak Tape & Reel Information
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
TRL
11.60 (.457)
11.40 (.449)
1.85 (.073)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.2/08
www.irf.com
11
IMPORTANT NOTICE
The information given in this document shall in no For further information on the product, technology,
event be regarded as a guarantee of conditions or delivery terms and conditions and prices please
characteristics (“Beschaffenheitsgarantie”) .
contact your nearest Infineon Technologies office
(www.infineon.com).
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
Infineon Technologies office.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of
the product or any consequences of the use thereof
can reasonably be expected to result in personal
injury.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
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