IRF3515STRL [INFINEON]
Power Field-Effect Transistor, 41A I(D), 150V, 0.045ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, PLASTIC, D2PAK-3;型号: | IRF3515STRL |
厂家: | Infineon |
描述: | Power Field-Effect Transistor, 41A I(D), 150V, 0.045ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, PLASTIC, D2PAK-3 开关 脉冲 晶体管 |
文件: | 总10页 (文件大小:133K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PD- 91899B
IRF3515S
IRF3515L
HEXFET® Power MOSFET
SMPS MOSFET
Applications
VDSS
150V
RDS(on) max
ID
41A
l Switch Mode Power Supply (SMPS)
l Uninterruptible Power Supply
l High speed power switching
0.045Ω
Benefits
l Low Gate Charge Qg results in Simple
Drive Requirement
l Improved Gate, Avalanche and dynamic
dv/dt Ruggedness
l Fully Characterized Capacitance and
Avalanche Voltage and Current
l Effective Coss Specified (See AN 1001)
D2Pak
IRF3515S
TO-262
IRF3515L
Absolute Maximum Ratings
Parameter
Max.
Units
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
41
29
A
164
PD @TC = 25°C
Power Dissipation
200
W
W/°C
V
Linear Derating Factor
1.3
VGS
dv/dt
TJ
Gate-to-Source Voltage
± 30
Peak Diode Recovery dv/dt
Operating Junction and
4.3
V/ns
-55 to + 175
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
°C
300 (1.6mm from case )
Applicable Off Line SMPS Topologies
l Telcom 48V input DC/DC Active Clamp Reset Forward Converter
Notes through ꢀ are on page 10
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1
10/28/99
IRF3515S/L
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
150 ––– –––
Conditions
VGS = 0V, ID = 250µA
V(BR)DSS
Drain-to-Source Breakdown Voltage
V
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.21 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on)
VGS(th)
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
––– ––– 0.045
3.0 ––– 4.5
Ω
VGS = 10V, ID = 25A
VDS = VGS, ID = 250µA
VDS = 150V, VGS = 0V
VDS = 120V, VGS = 0V, TJ = 150°C
VGS = 30V
V
––– ––– 25
––– ––– 250
––– ––– 100
––– ––– -100
µA
nA
IDSS
IGSS
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 50V, ID = 25A
ID = 25A
gfs
15 ––– –––
S
Qg
––– ––– 107
––– ––– 23
––– ––– 65
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
nC VDS = 120V
VGS = 10V, See Fig. 6 and 13
–––
17 –––
VDD = 75V
––– 120 –––
ID = 25A
ns
td(off)
tf
Turn-Off Delay Time
Fall Time
–––
–––
34 –––
63 –––
RG = 2.5Ω
RD = 3.0Ω,See Fig. 10
VGS = 0V
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
––– 2260 –––
––– 530 –––
––– 170 –––
––– 3330 –––
––– 230 –––
––– 280 –––
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
VDS = 25V
pF
ƒ = 1.0MHz, See Fig. 5
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 120V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 120V ꢀ
Avalanche Characteristics
Parameter
Single Pulse Avalanche Energy
Typ.
Max.
670
25
Units
mJ
EAS
IAR
–––
–––
–––
Avalanche Current
A
EAR
Repetitive Avalanche Energy
20
mJ
Thermal Resistance
Parameter
Junction-to-Case
Typ.
–––
Max.
0.75
40
Units
°C/W
RθJC
RθJA
Junction-to-Ambient ( PCB Mounted, steady-state)*
–––
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
D
IS
Continuous Source Current
(Body Diode)
MOSFET symbol
41
––– –––
showing the
A
G
ISM
Pulsed Source Current
(Body Diode)
integral reverse
p-n junction diode.
––– ––– 164
S
VSD
trr
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
––– ––– 1.3
––– 200 300
––– 1.6 2.4
V
TJ = 25°C, IS = 25A, VGS = 0V
ns
TJ = 25°C, IF = 25A
Qrr
ton
µC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
2
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IRF3515S/L
1000
100
10
1000
100
10
VGS
15V
12V
10V
9.0V
8.0V
7.0V
6.0V
VGS
15V
12V
10V
9.0V
8.0V
7.0V
6.0V
TOP
TOP
BOTTOM 5.0V
BOTTOM 5.0V
1
5.0V
20µs PULSE WIDTH
T = 175 C
J
20µs PULSE WIDTH
°
5.0V
°
T = 25 C
J
1
0.1
0.1
0.1
1
10
100
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
3.0
41A
=
I
D
2.5
2.0
1.5
1.0
0.5
0.0
100
10
1
°
T = 175 C
J
°
T = 25 C
J
V
= 50V
DS
20µs PULSE WIDTH
V
= 10V
GS
4
6
8
10 12
14
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
°
V
, Gate-to-Source Voltage (V)
T , Junction Temperature ( C)
J
GS
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRF3515S/L
20
16
12
8
100000
I
D
= 25A
V
= 0V,
f = 1 MHZ
GS
V
V
V
= 120V
= 75V
= 30V
DS
DS
DS
C
= C + C
,
C
SHORTED
iss
gs
gd
ds
C
= C
rss
gd
C
= C + C
oss
ds
gd
10000
1000
100
Ciss
Coss
Crss
4
FOR TEST CIRCUIT
SEE FIGURE 13
0
1
10
, Drain-to-Source Voltage (V)
100
0
20
40
60
80
100
120
Q
, Total Gate Charge (nC)
V
G
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000
100
10
1000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
100
10
1
10us
°
T = 175 C
J
100us
°
T = 25 C
J
1ms
10ms
°
T = 25 C
C
°
T = 175 C
Single Pulse
J
V
= 0 V
GS
0.1
0.2
1
0.6
1.0
1.4
1.8
1
10
100
1000
V
,Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRF3515S/L
RD
50
40
30
20
10
0
VDS
VGS
10V
D.U.T.
RG
+VDD
-
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 10a. Switching Time Test Circuit
V
DS
90%
25
50
75
100
125
150
175
°
, Case Temperature ( C)
T
C
10%
V
GS
t
t
r
t
t
f
Fig 9. Maximum Drain Current Vs.
d(on)
d(off)
Case Temperature
Fig 10b. Switching Time Waveforms
1
D = 0.50
0.20
0.1
0.10
0.05
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
P
DM
0.01
t
1
t
2
Notes:
1. Duty factor D =
t
/ t
1
2
2. Peak T
= P
x
Z
+ T
J
DM
thJC
C
0.001
0.00001
0.0001
0.001
0.01
0.1
1
t , Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF3515S/L
1600
1200
800
400
0
1 5V
I
D
TOP
10A
17A
25A
BOTTOM
DRIVER
L
V
G
DS
D.U.T
R
+
V
D D
-
I
A
AS
20V
0.01
t
Ω
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
175
°
Starting T , Junction Temperature ( C)
J
I
AS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
10 V
Q
Q
GD
GS
V
G
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
V
GS
3mA
I
I
D
G
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
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IRF3515S/L
Peak Diode Recovery dv/dt Test Circuit
+
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T
-
+
-
-
+
RG
• dv/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VDD
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
V
=10V
*
GS
D.U.T. I Waveform
SD
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETS
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7
IRF3515S/L
D2Pak Package Outline
10.54 (.415)
10.29 (.405)
10.16 (.400)
REF.
- B -
1.32 (.052)
4.69 (.185)
4.20 (.165)
1.40 (.055)
- A -
M AX.
1.22 (.048)
2
6.47 (.255)
6.18 (.243)
1.78 (.070)
1.27 (.050)
15.49 (.610)
14.73 (.580)
2.79 (.110)
2.29 (.090)
1
3
2.61 (.103)
2.32 (.091)
5.28 (.208)
4.78 (.188)
8.89 (.350)
REF.
1.40 (.055)
1.14 (.045)
1.39 (.055)
1.14 (.045)
3X
0.55 (.022)
0.46 (.018)
0.93 (.037)
0.69 (.027)
3X
5.08 (.200)
0.25 (.010)
M
B A M
MINIMUM RECOM MENDED FOOTPRINT
11.43 (.450)
8.89 (.350)
LEAD ASSIGNMENTS
1 - GATE
NO TES:
1
2
3
4
DIM ENSIONS AFTER SO LDER DIP.
17.78 (.700)
2 - DRAIN
3 - SOURCE
DIM ENSIONING & TOLERANCING PER ANSI Y14.5M , 1982.
CONTROLLING DIM ENSION : INCH.
HEATSINK & LEAD DIM ENSIONS DO NOT INCLUDE BURRS.
3.81 (.150)
2.54 (.100)
2.08 (.082)
2X
2X
D2Pak Part Marking Information
A
INTERNATIONAL
RECTIFIER
PART NUM BER
F530S
LOGO
9246
1M
DATE CODE
(YYW W )
9B
ASSEM BLY
YY
=
YEAR
= W EEK
LOT CODE
W W
8
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IRF3515S/L
TO-262 Package Outline
TO-262 Part Marking Information
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9
IRF3515S/L
D2Pak Tape & Reel Information
TR R
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
F EE D D IRE C TIO N
TR L
11.60 (.457)
11.40 (.449)
1.85 (.073)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
F E ED D IRE C T IO N
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
M AX.
60.00 (2.362)
M IN.
30.40 (1.197)
MAX.
NOTES
:
1. COMFORMS TO EIA-418.
2. CONTROLLING DIM ENSION: M ILLIM ETER.
3. DIM ENSION M EASURED
4. INCLUDES FLANGE DISTORTION
26.40 (1.039)
24.40 (.961)
4
@ HUB.
3
@
OUTER EDGE.
Notes:
Repetitive rating; pulse width limited by
Pulse width ≤ 300µs; duty cycle ≤ 2%.
max. junction temperature. (See fig. 11)
ꢀCoss eff. is a fixed capacitance that gives the same charging time
Starting TJ = 25°C, L = 2.2mH
as Coss while VDS is rising from 0 to 80% VDSS
RG = 25Ω, IAS = 25A. (See Figure 12)
ISD ≤ 5.0A, di/dt ≤ 330A/µs, VDD ≤ V(BR)DSS
,
TJ ≤ 175°C
* When mounted on FR-4 board using minimum recommended footprint.
For recommended footprint and soldering techniques refer to application note #AN-994.
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IR GREAT BRITAIN: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
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IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673, Taiwan Tel: 886-2-2377-9936
Data and specifications subject to change without notice. 10/99
10
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相关型号:
IRF3515STRLPBF
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Power Field-Effect Transistor, 41A I(D), 150V, 0.045ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, LEAD FREE, PLASTIC, D2PAK-3
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