IRF3546MTRPBF_技术文档

60A Dual Integrated Power Block

IRF3546

The IRF3546 dual integrated Power Block co-

packages two pairs of high performance control and

synchronous MOSFETs and is ideal for use in high-

density two-phase synchronous buck converters. It is

optimized internally for PCB layout, heat transfer and

package inductance. Coupled with the latest

generation of IR MOSFET technology, the IRF3546

provides higher efficiency at low output voltages

required by cutting edge CPU, GPU and DDR

memory designs.

FEATURES

• Peak efficiency up to 94% at 1.2V

• Two pairs of control and synchronous

MOSFETs in a single PQFN package

• Proprietary package minimizes package

parasitic and simplifies PCB layout

• Input voltage (VIN) range of 4.5V to 21V

• Output current capability of 30A/phase

High switching frequency enables high performance

transient response, allowing miniaturization of output

inductors, as well as input and output capacitors while

maintaining industry leading efficiency. Integrating two

phases in one package while still providing superior

efficiency and thermal performance, the IRF3546

enables smallest size solutions.

• Ultra-low Rg MOSFET technology minimizes

switching losses for optimized high frequency

performance

• Synchronous MOSFET with monolithic

integrated Schottky diode reduces dead-time

and diode reverse recovery losses

• Efficient dual side cooling

The IRF3546 uses IR’s latest generation of low

voltage MOSFET technology characterized by ultra-

low gate resistance (Rg, <0.5Ω) and charge that result

in minimized switching losses. The synchronous

MOSFET optimizes conduction losses and features a

monolithic integrated Schottky to significantly reduce

dead-time and diode conduction and reverse recovery

losses.

• Small 6mm x 8 mm x 0.9mm PQFN package

• Lead-free RoHS compliant package

APPLICATIONS

• High frequency, low profile DC-DC converters

• Voltage Regulators for CPUs, GPUs, and DDR

memory arrays

The IRF3546 is optimized specifically for CPU core

power delivery in 12V input applications like servers,

certain notebooks, GPU and DDR memory designs.

DESCRIPTION

ORDERING INFORMATION

Standard Pack

Base Part Number Package Type

Orderable Part Number

Form

Tape and Reel

Quantity

3000

IRF3546

PQFN 6 mm x 8 mm

IRF3546MTRPBF

May 29, 2013 | Final

1

60A Dual Integrated Power Block

IRF3546

PINOUT DIAGRAM

Figure 1: IRF3546 Top View

FUNCTIONAL BLOCK DIAGRAM

VIN2

16

VIN1

41

VIN2

17

VIN1 VIN1

40

GATEH2 VIN2

GATEH1

7

1

15

9

29

30

31

32

SW1

21

22

23

24

SW2

Q1

Q2

Q3

SW1 33

25 SW2

IRF3546

SW1

34

35

36

SW2

26

27

28

Q4

38

PGND

39

PGND

37

GATEL1

18

GATEL2

19

20

PGND

8

42

PGND

Figure 2: Block Diagram

May 29, 2013 | Final

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60A Dual Integrated Power Block

IRF3546

TYPICAL APPLICATION

VIN1

IRF3546

1, 40, 41

C2

0.1uF

C1

10uF x2

Q1

GATEH1

7

L1

150nH

SW1

VOUT1

C3

22uF x5

29‐36

Q2

GATEL1

37

PGND

38, 39

PGND

8, 42

VIN2

15‐17

C5

0.1uF

C4

10uF x2

Q3

Q4

GATEH2

9

L2

150nH

SW2

21‐28

VOUT2

C6

22uF x5

GATEL2

18

PGND

19, 20

Figure 3: High Density Two Phase Voltage Regulator

May 29, 2013 | Final

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60A Dual Integrated Power Block

IRF3546

PIN DESCRIPTIONS

PIN #

PIN NAME

PIN DESCRIPTION

High current input supply pads. Connected to Drains of Q1. Recommended operating

range is 4.5V to 21V. Connect at least two 10uF 1206 ceramic capacitors and a 0.1uF

0402 ceramic capacitor. Place the capacitors as close as possible to VIN1 pins (40 and 41)

and PGND pins (38 and 39). The 0.1uF 0402 capacitor should be on the same side of the

PCB as the IRF3546.

1, 40, 41

VIN1

No connects. These pins can be connected to the VIN planes to reduce PCB trace

resistances.

2-6, 10-14

7

No Connect

GATEH1

Gate connection of the Channel 1 control MOSFET Q1.

High current Power Ground. Connected to Sources of Q2 and Q4. Note all pads are

internally connected in the package. Provide low resistance connections to the ground

plane and respective output capacitors.

8, 19, 20,

38, 39, 42

PGND

9

GATEH2

Gate connection of the Channel 2 control MOSFET Q3.

High current input supply pads. Connected to Drains of Q3. Recommended operating

range is 4.5V to 21V. Connect at least two 10uF 1206 ceramic capacitors and a 0.1uF

0402 ceramic capacitor. Place the capacitors as close as possible to VIN2 pins (16 and 17)

and PGND pins (19 and 20). The 0.1uF 0402 capacitor should be on the same side of the

PCB as the IRF3546.

15-17

VIN2

18

GATEL2

SW2

Gate connection of the Channel 2 synchronous MOSFET Q4.

High Current Switch Node output for Channel 2. Connected to Source of Q3 and Drain of

Q4.

21-28

High Current Switch Node output for Channel 1. Connected to Source of Q1 and Drain of

Q2.

29-36

37

SW1

GATEL1

Gate connection of the Channel 1 synchronous MOSFET Q2.

May 29, 2013 | Final

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60A Dual Integrated Power Block

IRF3546

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

These are stress ratings only and functional operation of the device at these or any other conditions beyond those

indicated in the operational sections of the specifications are not implied.

Parameter

Drain-to-Source Voltage

Q1 and Q3 Max.

Q2 and Q4 Max.

Units

V_DS

25

V

A

V_GS

Gate-to-Source Voltage

±20

I_D@T_C= 25°C

Continuous Drain Current, V_GS@ 10V

16

20

I_D@T_C= 70°C

Continuous Drain Current, V_GS@ 10V

Pulse Drain Current

13

130

16

160

A

I_DM

E_AS

Single Pulse Avalanche Energy

50 ^{NOTE 1}

200 ^{NOTE 2}

mJ

THERMAL INFORMATION

Thermal Resistance, Junction to Top (θ_{JC_TOP}

)

11.3 °C/W

Thermal Resistance, Junction to PCB (pin 28) (θ_JB)

Thermal Resistance (θ_JA) ^{NOTE 3}

Maximum Operating Junction Temperature

Maximum Storage Temperature Range

MSL Rating

1.6 °C/W

18.4 °C/W

-40°C to 150°C

-55°C to 150°C

MSL3

Reflow Temperature

260°C

Notes

1. T_J=25°C, L =100uH, R_G=50Ω, I_AS=32A.

2. T_J=25°C, L =100uH, R_G=50Ω, I_AS=63A.

3. Thermal Resistance (θ_JA) is measured with the component mounted on a high effective thermal conductivity test board in free air.

Refer to International Rectifier Application Note AN-994 for details.

May 29, 2013 | Final

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60A Dual Integrated Power Block

IRF3546

ELECTRICAL SPECIFICATIONS

The electrical characteristics involve the spread of values guaranteed within the recommended operating

conditions. Typical values represent the median values, which are related to 25°C.

ELECTRICAL CHARACTERISTICS

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

Efficiency

Note 2

Note 3

94

93

%

Power Block per-channel Peak Efficiency

η

Control MOSFETs (Q1 and Q3)

Drain-to-Source On-Resistance

R_{DS(ON)_4.5V_25°C}

R_{DS(ON)_10V_25°C}

V_GS=4.5V, I_D=13A, T_J=25°C

V_GS=10V, I_D=27A, T_J=25°C

4.1

3.2

4.8

3.9

mꢀ

Drain-to-Source On-Resistance

Drain-to-Source Breakdown Voltage

BV_DSS

V_GS=0V, I_D=250uA, T_J=25°C

T_J=25°C -125°C, Note 1

25

V

Breakdown Voltage Temperature

Coefficient

∆BV_DSS/ ∆T_J

0.02

V/°C

Drain-to-Source Leakage Current

Gate-to-Source Forward Leakage Current

Gate-to-Source Reverse Leakage Current

Gate Threshold Voltage

I_DSS

V_DS=20V, V_GS=0V, T_J=25°C

V_GS=16V

1

μA

nA

I_GSS

100

-100

2.1

I_GSS

V_GS=-16V

nA

V_GS(th)

∆V_GS(th)

V_DS= V_GS, I_D=35uA

1.1

1.6

V

Gate Threshold Voltage Coefficient

Total Gate Charge

-5.7

mV/°C

V_DS= 13V, V_GS=4.5V, I_D=13A,

Note 1

Q_g

9.7

15

nC

Pre-Vth Gate-to-Source Charge

Post-Vth Gate-to-Source Charge

Gate-to-Drain Charge

Q_gs1

Q_gs2

Q_gd

V_DS= 13V, V_GS=4.5V, I_D=13A

V_DS= 16V, V_GS=0V

2.3

1.8

3.1

2.9

4.9

13

nC

ꢀ

Gate Charge Overdrive

Q_godr

Q_SW

Q_oss

R_g

Switch Charge (Q_gs2+Q_gd

Output Charge

)

Gate Resistance

0.6

Turn-On Delay Time

V_DD= 13V, V_GS=4.5V, I_D=13A,

R_G=1.8 ꢀ

t_d(on)

t_r

7.5

12

ns

Rise Time

V_DD= 13V, V_GS=4.5V, I_D=13A,

R_G=1.8 ꢀ

Turn-Off Delay Time

Fall Time

V_DD= 13V, V_GS=4.5V, I_D=13A,

R_G=1.8 ꢀ

t_d

6.7

4.2

V_DD= 13V, V_GS=4.5V, I_D=13A,

R_G=1.8 ꢀ

t_f

Input Capacitance

Output Capacitance

C_iss

C_oss

C_rss

V_SD

V_GS= 0V, V_DS=13V, f=1.0MHz

V_GS=0V, I_S=13A, T_J=25°C

1310

380

90

pF

V

Reverse Transfer Capacitance

Diode Forward Voltage

0.72

0.80

0.88

23

Reverse Recovery Time

T_J=25°C, I_F=30A, V_DD=13V,

di/dt=200A/us, Note 1

t_rr

15

10

ns

Reverse Recovery Charge

T_J=25°C, I_F=30A, V_DD=13V,

di/dt=200A/us, Note 1

Q_rr

15

nC

May 29, 2013 | Final

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60A Dual Integrated Power Block

IRF3546

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNIT

Synchronous MOSFETs (Q2 and Q4)

Drain-to-Source On-Resistance

R_{DS(ON)_4.5V_25°C}

R_{DS(ON)_10V_25°C}

V_GS=4.5V, I_D=16A, T_J=25°C

V_GS=10V, I_D=30A, T_J=25°C

1.8

2.2

1.8

mꢀ

Drain-to-Source On-Resistance

1.35

Drain-to-Source Breakdown Voltage

BV_DSS

V_GS=0V, I_D=1mA, T_J=25°C

T_J=25°C -125°C, Note 1

V_DS=20V, V_GS=0V, T_J=25°C

25

V

Breakdown Voltage Temperature

Coefficient

∆BV_DSS/ ∆T_J

I_DSS

0.02

V/°C

uA

Drain-to-Source Leakage Current

250

Gate-to-Source Forward Leakage Current

Gate-to-Source Reverse Leakage Current

Gate Threshold Voltage

I_GSS

V_GS=16V

100

-100

2.1

nA

I_GSS

V_GS=-16V

V_GS(th)

∆V_GS(th)

V_DS= V_GS, I_D=100uA

V_DS= V_GS, I_D=1mA

1.1

1.6

V

Gate Threshold Voltage Coefficient

Total Gate Charge

-5.4

mV/°C

V_DS= 13V, V_GS,=4.5V, I_D=30A,

Note 1

Q_g

22

33

nC

Pre-Vth Gate-to-Source Charge

Post-Vth Gate-to-Source Charge

Gate-to-Drain Charge

Q_gs1

Q_gs2

Q_gd

V_DS= 13V, V_GS=4.5V, I_D=30A

V_DS= 16V, V_GS=0V

5.1

3.1

6.0

6.7

9.1

23

nC

ꢀ

Gate Charge Overdrive

Q_godr

Q_SW

Q_oss

R_g

Switch Charge (Q_gs2+Q_gd

Output Charge

)

Gate Resistance

0.4

Turn-On Delay Time

V_DD= 13V, V_GS=4.5V, I_D=16A,

R_G=1.3 ꢀ

t_d(on)

t_r

13

15

16

6.6

ns

Rise Time

V_DD= 13V, V_GS=4.5V, I_D=16A,

R_G=1.3 ꢀ

Turn-Off Delay Time

Fall Time

V_DD= 13V, V_GS=4.5V, I_D=16A,

R_G=1.3 ꢀ

t_d

V_DD= 13V, V_GS=4.5V, I_D=16A,

R_G=1.3 ꢀ

t_f

Input Capacitance

Output Capacitance

C_iss

C_oss

C_rss

V_SD

V_GS= 0V, V_DS=13V, f=1.0MHz

V_GS=0V, I_S=30A, T_J=25°C

V_GS=0V, I_S=13A, T_J=25°C

2880

950

pF

V

Reverse Transfer Capacitance

Diode Forward Voltage

Reverse Recovery Time

180

0.63

0.54

0.70

0.60

0.77

0.66

V

T_J=25°C, I_F=30A, V_DD=13V,

di/dt=200A/us, Note 1

t_rr

23

30

35

45

ns

Reverse Recovery Charge

T_J=25°C, I_F=30A, V_DD=13V,

di/dt=200A/us, Note 1

Q_rr

nC

Notes

1. Guaranteed by design but not tested in production

2. V_IN=12V, V_OUT=1.2V, ƒ_SW= 300kHz, L=210nH (0.29mꢀ), VCC=6.8V, C_IN=47uF x 4, C_OUT=470uF x3, 400LFM airflow, no heat sink, 25°C

ambient temperature, and 8-layer PCB of 3.7” (L) x 2.6” (W). PWM controller loss and inductor loss are not included.

3. V_IN=12V, V_OUT=1.2V, ƒ_SW= 400kHz, L=150nH (0.29mꢀ), VCC=6.8V, C_IN=47uF x 4, C_OUT=470uF x3, no airflow, no heat sink, 25°C

ambient temperature, and 8-layer PCB of 3.7” (L) x 2.6” (W). PWM controller loss and inductor loss are not included.

May 29, 2013 | Final

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60A Dual Integrated Power Block

IRF3546

TYPICAL OPERATING CHARACTERISTICS

T_A= 25°C, no heat sink, no air flow, 8-layer PCB board of 3.7” (L) x 2.6” (W), unless specified otherwise.

1000

100

VGS

10V

5V

4.5V

3.5V

3.3V

3V

VGS

10V

5V

4.5V

3.5V

3.3V

3V

TOP

10

1

10

1

TOP

2.8V

BOTTOM 2.5V

0.1

1

10

100

0.1

1

10

100

V_DS, Drain-to-Source Voltage (V)

Figure 4: Q1 & Q3 Typical Output Characteristics

Figure 7: Q2 & Q4 Typical Output Characteristics

1000

100

VGS

TOP

10V

5V

4.5V

3.5V

3.3V

3V

TOP

10V

5V

4.5V

3.5V

3.3V

3V

10

1

10

1

2.8V

<=60us PULSE WIDTH

1

<=60us PULSE WIDTH

1

BOTTOM 2.5V

0.1

10

100

0.1

10

100

V_DS, Drain-to-Source Voltage (V)

Figure 8: Q2 & Q4 Typical Output Characteristics @150^oC

Figure 5: Q1 & Q3 Typical Output Characteristics @150^oC

1000

V_DS=15V, <=60us PULSE WIDTH

100

T_J=150^oC

TJ=25^oC

TJ=-40^oC

T_J=150^oC

TJ=25^oC

TJ=-40^oC

10

1

0.1

1

1.5

2

2.5

3

3.5

4

1

1.5

2

2.5

3

3.5

4

V_GS, Gate-to-Source Voltage (V)

Figure 9: Q2 and Q4 Typical Transfer Characteristics

May 29, 2013 | Final

Figure 6: Q1 and Q3 Typical Transfer Characteristics

8

60A Dual Integrated Power Block

IRF3546

TYPICAL OPERATING CHARACTERISTICS (CONTINUE)

T_A= 25°C, no heat sink, no air flow, 8-layer PCB board of 3.7” (L) x 2.6” (W), unless specified otherwise.

6

12

I_D= 30A

I_D= 27A

5

4

3

2

1

0

10

8

6

T_J=125^oC

4

T_J=25^oC

2

T_J=25^oC

0

2

4

6

8

10

12

14

16

0

2

4

6

8

10

12

14

16

V_GS, Gate-to-Source Voltage (V)

Figure 10: Q1 & Q3 Typical On-Resistance

Figure 13: Q2 & Q4 Typical On-Resistance

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

I_D= 27A

_GS= 10V

I_D= 30A

V_GS= 10V

V

-40

-20

0

20

40

60

80

100 120

140

160

-40

-20

0

20

40

60

80

100

120

140

160

T_J, Junction Temperature (^oC)

Figure 14: Q2 & Q4 On-Resistance vs. Temperature

Figure 11: Q1 & Q3 On-Resistance vs. Temperature

10000

V_GS= 0V

f =1MHz

C_iss

1000

C_oss

1000

C_rss

100

C_rss

10

100

1

10

100

1

10

100

V_GS, Drain-to-Source Voltage (V)

Figure 15: Q2 & Q4 Typical Capacitance vs.

Drain-Source Voltage

Figure 12: Q1 & Q3 Typical Capacitance vs.

Drain-Source Voltage

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60A Dual Integrated Power Block

IRF3546

TYPICAL OPERATING CHARACTERISTICS (CONTINUE)

T_A= 25°C, no heat sink, no air flow, 4-layer PCB board of 3.7” (L) x 2.6” (W), unless specified otherwise.

4.0

10

9

8

7

6

5

4

3

2

1

0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

V_GS= 4.5V

V_GS= 6V

V_GS= 4.5V

V_GS= 6V

V

_GS= 7V

_GS= 8V

_GS= 10V

V

_GS= 7V

_GS= 8V

_GS= 10V

V

0

20

40

60

80

100 120

140

160

180

200

0

20

40

60

80

100

120

140

160

I_D, Drain Current (A)

Figure 19: Q2 & Q4 Typical On-Resistance

Figure 16: Q1 & Q3 Typical On-Resistance

1000

100

10

1

1000

100

10

1

T_J= 150^oC

T_J= 25^oC

T

_J= 25^oC

T_J= -40^oC

T

_J= -40^oC

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

1.1 1.2

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

1.1 1.2

V_SD, Source-Drain Forward Voltage (V)

Figure 20: Q2 & Q4 Drain-Source Diode Characteristics

Figure 17: Q1 & Q3 Drain-Source Diode Characteristics

2.5

2.0

2.5

2.0

I_D= 100mA

1.5

I_D= 10mA

I_D= 1mA

1.0

0.5

0.0

I_D= 0.25mA

_D= 0.1mA

I_D= 0.035mA

I

0.5

0.0

-40

-20

0

20

40

60

80

100

120

140

160

-40

-20

0

20

40

60

80

100

120

140

160

T_J, Junction Temperature (^oC)

Figure 21: Q2 & Q4 Typical Threshold Voltage vs.

Junction Temperature

Figure 18: Q1 & Q3 Typical Threshold Voltage vs.

Junction Temperature

May 29, 2013 | Final

10

60A Dual Integrated Power Block

IRF3546

TYPICAL OPERATING CHARACTERISTICS (CONTINUE)

T_A= 25°C, no heat sink, no air flow, 8-layer PCB board of 3.7” (L) x 2.6” (W), unless specified otherwise.

400

350

300

250

200

150

100

50

3000

2500

2000

1500

1000

500

I_D= 5A

I_D= 6.5A

I_D= 11A

I_D= 30A

I_D= 8.7A

I_D= 30A

0

25

50

75

100

125

150

25

50

75

100

125

150

T_J, Starting Junction Temperature (^oC)

Figure 22: Q1 & Q3 Single Pulse Avalanche Energy

Figure 25: Q2 & Q4 Single Pulse Avalanche Energy

30

25

20

15

10

5

45

40

35

30

25

20

15

10

5

0

25

50

75

100

125

150

25

50

75

100

125

150

T_A, Ambient Temperature (^oC)

Figure 23: Q1 & Q3 Maximum Drain Current vs. Temperature

Figure 26: Q2 & Q4 Maximum Drain Current vs. Temperature

1000

OPERATION IN THIS AREA LIMITED BY R_DS(on)

100

100us

1ms

100

10

1

100us

1ms

10

10ms

1

DC

T_A= 25^oC

0

T_A= 25^oC

T_J= 150^oC

0

T_J= 150^oC

Single Pulse

0

0.01

0.1

1

10

100

0.01

0.1

1

10

100

V_DS, Drain-to-Source Voltage (V)

Figure 24: Q1 & Q3 Maximum Safe Operating Area

Figure 27: Q2 & Q4 Maximum Safe Operating Area

May 29, 2013 | Final

11

60A Dual Integrated Power Block

IRF3546

GENERAL DESCRIPTION

PCB LAYOUT CONSIDERATION

The IRF3546 contains two pairs of integrated high

and low side N-channel MOSFETs. It is suitable for

high switching frequency operation.

PCB layout and design is important to driver

performance in voltage regulator circuits due to the

high current slew rate (di/dt) during MOSFET

switching.

The IRF3546 can be driven as two independent

power stages or as one power stage in a two-phase

interleaved converter .

Locate all power components in each phase as

close to each other as practically possible in order to

minimize parasitics and losses, allowing for

reasonable airflow.

APPLICATION INFORMATION

Input supply decoupling capacitors should be

physically located close to their respective pins.

Figure 3 shows a typical two phase, high density

application circuit for the IRF3546.

High current paths like the gate driver traces should

be as wide and short as practically possible.

GATEL1 and GATEL2 interconnect trace inductances

should be minimized to prevent Cdv/dt turn-on of the low

side MOSFET.

SUPPLY DECOUPLING CAPACITOR

At least two 10uF 1206 ceramic capacitors and one

0.1uF 0402 ceramic capacitor are recommended for

decoupling the VIN to PGND connection of each

MOSFET pair. The 0.1uF 0402 capacitor should be

on the same side of the PCB as the IRF3546 and

next to the VIN and PGND pins. Adding additional

capacitance and use of capacitors with lower ESR

and mounted with low inductance routing will

improve efficiency and reduce overall system noise,

especially in high current applications.

The ground connection should be as close as

possible to the low-side MOSFET source.

Use of a copper plane under and around the device

and thermal vias to connect to buried copper layers

improves the thermal performance substantially.

May 29, 2013 | Final

12

60A Dual Integrated Power Block

IRF3546

METAL AND COMPONENT PLACEMENT

• Center pad land length and width should be

• Lead land width should be equal to nominal

part lead width. The minimum lead to lead

spacing should be ≥ 0.2mm to prevent

shorting.

equal to maximum part pad length and width.

• Only 0.30mm diameter via shall be placed in

the area of the power pad lands and

connected to power planes to minimize the

noise effect and to improve thermal

performance.

• Lead land length should be equal to

maximum part lead length +0.15 - 0.3 mm

outboard extension and 0 to + 0.05mm

inboard extension. The outboard extension

ensures a large and visible toe fillet, and the

inboard extension will accommodate any part

misalignment and

ensure a fillet.

Figure 28: Metal and Component Placement

May 29, 2013 | Final

13

60A Dual Integrated Power Block

IRF3546

SOLDER RESIST

• At the inside corner of the solder resist

• The solder resist should be pulled away

from the metal lead lands by a minimum

of 0.06mm. The solder resist miss-alignment

is a maximum of 0.05mm and it is

where the lead land groups meet, it is

recommended to provide a fillet so a solder

resist width of ≥ 0.17mm remains.

recommended that the low power signal lead

lands are all Non Solder Mask Defined

(NSMD). Therefore pulling the S/R 0.06mm

will always ensure NSMD pads.

• The power land pads VIN1, VIN2, PGND,

SW1 and SW2 should be Solder Mask

Defined (SMD).

• Ensure that the solder resist in-between the

lead lands and the pad land is ≥ 0.15mm due

to the high aspect ratio of the solder resist

strip separating the lead lands from the pad

land.

• The minimum solder resist width is 0.13mm

typical.

Figure 29: Solder Resist

May 29, 2013 | Final

14

60A Dual Integrated Power Block

IRF3546

STENCIL DESIGN

• The power pads VIN1, VIN2, PGND, SW1

and SW2, land pad apertures should be

approximately 65% to 75% area of solder on

the center pad. If too much solder is

deposited on the center pad the part will float

and the lead lands will be open. Solder paste

on large pads is broken down into small

sections with a minimum gap of 0.2mm

between allowing for out-gassing during

solder reflow.

• The stencil apertures for the lead lands

should be approximately 65% to 75% of the

area of the lead lands depending on stencil

thickness. Reducing the amount of solder

deposited will minimize the occurrence of

lead shorts. Since for 0.5mm pitch devices

the leads are only 0.25mm wide, the stencil

apertures should not be made narrower;

openings in stencils < 0.25mm wide are

difficult to maintain repeatable solder release.

• The maximum length and width of the land

pad stencil aperture should be equal to the

solder resist opening minus an annular

0.2mm pull back to decrease the incidence of

shorting the center land to the lead lands

when the part is pushed into the solder paste.

• The low power signal stencil lead land

apertures should therefore be shortened in

length to keep area ratio of 65% to 75% while

centered on lead land.

Figure 30: Stencil Design

May 29, 2013 | Final

15

60A Dual Integrated Power Block

IRF3546

MARKING INFORMATION

F3546M

?YWW?

xxxx

Assembly Site(?)/Date(YWW)/M/arking Code(?)

Lot Code

Figure 31: PQFN 6mm x 8mm

May 29, 2013 | Final

16

60A Dual Integrated Power Block

IRF3546

PACKAGE INFORMATION

Figure 32: PQFN 6mm x 8mm

May 29, 2013 | Final

17

60A Dual Integrated PowIRblock^TM

IRF3546

Data and specifications subject to change without notice.

This product will be designed and qualified for the Consumer market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information.

www.irf.com

May 29, 2013 | Final

18


型号：	IRF3546MTRPBF
厂家：	Infineon
描述：	60A Dual Integrated Power Block 60A双集成电源模块电源电路
文件：	总18页 (文件大小：358K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRF3546MTRPBF [INFINEON]

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