IRF3709ZCL [INFINEON]

HEXFET Power MOSFET; HEXFET功率MOSFET


型号：	IRF3709ZCL
厂家：	Infineon
描述：	HEXFET Power MOSFET HEXFET功率MOSFET 晶体晶体管功率场效应晶体管开关脉冲
文件：	总11页 (文件大小：310K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PD - 95836

IRF3709ZCS

IRF3709ZCL

HEXFET^®Power MOSFET

Applications

l High Frequency Synchronous Buck

Converters for Computer Processor Power

V_DSSR_DS(on)max

6.3m:

30V

17nC

Benefits

l Low R_DS(on)at 4.5V V_GS

l Low Gate Charge

l Fully Characterized Avalanche Voltage

and Current

D²Pak

TO-262

IRF3709ZCS

IRF3709ZCL

Absolute Maximum Ratings

Parameter

Drain-to-Source Voltage

Max.

Units

V_DS

Gate-to-Source Voltage

± 20

Continuous Drain Current, V_GS@ 10V

Pulsed Drain Current

@ T_C= 25°C

@ T_C= 100°C

350

@T_C= 25°C

Maximum Power Dissipation

@T_C= 100°C

Linear Derating Factor

Operating Junction and

0.53

W/°C

°C

-55 to + 175

Storage Temperature Range

STG

Soldering Temperature, for 10 seconds

300 (1.6mm from case)

Thermal Resistance

Parameter

Typ.

–––

Max.

1.89

Units

°C/W

R_θJC

Junction-to-Case

R_θJA

–––

Junction-to-Ambient (PCB Mount)

Notes through are on page 11

www.irf.com

1/16/04

IRF3709ZCS/L

Static @ T_J= 25°C (unless otherwise specified)

Parameter

Drain-to-Source Breakdown Voltage

Min. Typ. Max. Units

30 ––– –––

Conditions

V_GS= 0V, I_D= 250µA

BV_DSS

∆ΒV_DSS/∆T_J

R_DS(on)

Breakdown Voltage Temp. Coefficient ––– 0.021 ––– mV/°C Reference to 25°C, I_D= 1mA

mΩ

Static Drain-to-Source On-Resistance

–––

1.35

–––

5.0

6.2

6.3

7.8

V_GS= 10V, I_D= 21A

V_GS= 4.5V, I_D= 17A

V_DS= V_GS, I_D= 250µA

V_GS(th)

Gate Threshold Voltage

–––

-5.5

–––

2.25

∆V_GS(th)/∆T_J

I_DSS

Gate Threshold Voltage Coefficient

Drain-to-Source Leakage Current

––– mV/°C

1.0

150

100

µA

_DS= 24V, V_GS= 0V

_DS= 24V, V_GS= 0V, T_J= 125°C

I_GSS

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Forward Transconductance

Total Gate Charge

nA V_GS= 20V

_GS= -20V

––– -100

gfs

–––

V_DS= 15V, I_D= 17A

Q_g

–––

Q_gs1

Q_gs2

Q_gd

Q_godr

Q_sw

Q_oss

t_d(on)

t_r

Pre-Vth Gate-to-Source Charge

Post-Vth Gate-to-Source Charge

Gate-to-Drain Charge

4.4

1.7

6.0

4.9

7.7

–––

V_DS= 15V

V_GS= 4.5V

I_D= 17A

Gate Charge Overdrive

See Fig. 14a&b

Switch Charge (Q_gs2+ Q_gd)

Output Charge

nC V_DS= 16V, V_GS= 0V

_DD= 15V, V_GS= 4.5V

Turn-On Delay Time

Rise Time

I_D= 17A

t_d(off)

t_f

Turn-Off Delay Time

Fall Time

ns Clamped Inductive Load

4.7

C_iss

C_oss

C_rss

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

––– 2130 –––

_GS= 0V

–––

450

220

–––

_DS= 15V

ƒ = 1.0MHz

Avalanche Characteristics

Parameter

Single Pulse Avalanche Energy

Typ.

–––

Max.

Units

E_AS

I_AR

Avalanche Current

Repetitive Avalanche Energy

E_AR

7.9

Diode Characteristics

Parameter

Continuous Source Current

Min. Typ. Max. Units

Conditions

MOSFET symbol

I_S

–––

(Body Diode)

Pulsed Source Current

showing the

integral reverse

I_SM

–––

350

(Body Diode)

p-n junction diode.

V_SD

t_rr

Diode Forward Voltage

–––

1.0

T = 25°C, I = 17A, V = 0V

J S GS

Reverse Recovery Time

Reverse Recovery Charge

ns T = 25°C, I = 17A, V_DD= 15V

J F

Q_rr

di/dt = 100A/µs

6.2

9.3

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IRF3709ZCS/L

1000

100

1000

100

VGS

10V

VGS

10V

TOP

9.0V

7.0V

5.0V

4.5V

4.0V

3.5V

3.0V

9.0V

7.0V

5.0V

4.5V

4.0V

3.5V

3.0V

BOTTOM

3.0V

60µs PULSE WIDTH

Tj = 175°C

≤

60µs PULSE WIDTH

≤

Tj = 25°C

0.1

100

0.1

100

, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics

Fig 2. Typical Output Characteristics

1000

100

2.0

1.5

1.0

0.5

= 42A

= 10V

= 175°C

= 25°C

= 15V

≤

60µs PULSE WIDTH

0.1

-60 -40 -20

20 40 60 80 100 120 140 160 180

, Junction Temperature (°C)

, Gate-to-Source Voltage (V)

Fig 3. Typical Transfer Characteristics

Fig 4. Normalized On-Resistance

vs. Temperature

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IRF3709ZCS/L

10000

6.0

5.0

4.0

3.0

2.0

1.0

0.0

= 0V,

= C

f = 1 MHZ

I = 17A

+ C , C

SHORTED

iss

= C

rss

oss

= C + C

= 24V

= 15V

iss

1000

oss

rss

100

Total Gate Charge (nC)

, Drain-to-Source Voltage (V)

Fig 6. Typical Gate Charge vs.

Fig 5. Typical Capacitance vs.

Gate-to-Source Voltage

Drain-to-Source Voltage

1000.00

100.00

10.00

10000

1000

100

OPERATION IN THIS AREA

LIMITED BY R (on)

= 175°C

100µsec

1msec

= 25°C

Tc = 25°C

Tj = 175°C

Single Pulse

10msec

= 0V

1.00

0.1

0.0

0.5

1.0

1.5

2.0

2.5

100

1000

, Source-to-Drain Voltage (V)

, Drain-to-Source Voltage (V)

Fig 8. Maximum Safe Operating Area

Fig 7. Typical Source-Drain Diode

Forward Voltage

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IRF3709ZCS/L

2.5

2.0

1.5

1.0

0.5

Limited By Package

= 250µA

-75 -50 -25

25 50 75 100 125 150 175 200

100

125

150

175

, Temperature ( °C )

, Case Temperature (°C)

Fig 9. Maximum Drain Current vs.

Fig 10. Threshold Voltage vs. Temperature

Case Temperature

D = 0.50

0.20

0.10

0.05

R₁

R₂

Ri (°C/W) τi (sec)

0.1

0.01

^Jτ_J

0.832

0.000221

^Cτ

0.02

0.01

¹τ₁

Ci= τi/Ri

²τ₂

1.058

0.001171

SINGLE PULSE

( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

0.001

1E-006

1E-005

0.0001

0.001

0.01

0.1

, Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRF3709ZCS/L

9.00

Vgs = 10V

= 21A

8.00

= 125°C

7.00

6.00

5.00

4.00

= 125°C

= 25°C

10.0

20.0

30.0

40.0

50.0

60.0

70.0

I , Drain Current (A)

Gate -to -Source Voltage (V)

GS,

Fig 12. On-Resistance vs. Drain Current

Fig 13. On-Resistance vs. Gate Voltage

Current Regulator

Same Type as D.U.T.

Vds

50KΩ

.2µF

Vgs

12V

.3µF

250

D.U.T.

TOP

5.4A

8.0A

Vgs(th)

200

150

100

3mA

BOTTOM 17A

Qgs1

Qgs2

Qgd

Qgodr

Current Sampling Resistors

Fig 14a&b. Basic Gate Charge Test Circuit

and Waveform

15V

(BR)DSS

DRIVER

D.U.T

100

125

150

175

20V

0.01

Ω

Starting T , Junction Temperature (°C)

Fig 16. Maximum Avalanche Energy

Fig 15a&b. Unclamped Inductive Test circuit

vs. Drain Current

and Waveforms

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IRF3709ZCS/L

Driver Gate Drive

P.W.

Period

D =

D.U.T

=10V

Circuit Layout Considerations

• Low Stray Inductance

• Ground Plane

• Low Leakage Inductance

Current Transformer

D.U.T. I Waveform

Reverse

Recovery

Current

Body Diode Forward

Current

di/dt

D.U.T. V Waveform

Diode Recovery

dv/dt

V_DD

Re-Applied

Voltage

•

dv/dt controlled by R_G

• Driver same type as D.U.T.

R_G

Body Diode

Forward Drop

• I_SDcontrolled by Duty Factor "D"

• D.U.T. - Device Under Test

Inductor Curent

Ripple ≤ 5%

* V_GS= 5V for Logic Level Devices

Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel

HEXFET^®Power MOSFETs

L_D

V_DS

V_DD

D.U.T

V_GS

Pulse Width < 1µs

Duty Factor < 0.1%

Fig 18a. Switching Time Test Circuit

V_DS

90%

10%

V_GS

t_d(on)

t_d(off)

t_r

t_f

Fig 18b. Switching Time Waveforms

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IRF3709ZCS/L

Power MOSFET Selection for Non-Isolated DC/DC Converters

Synchronous FET

Control FET

The power loss equation for Q2 is approximated

by;

Special attention has been given to the power losses

in the switching elements of the circuit - Q1 and Q2.

Power losses in the high side switch Q1, also called

the Control FET, are impacted by the R_ds(on)of the

MOSFET, but these conduction losses are only about

one half of the total losses.

P = P

+ P + P^*

loss

conduction

drive

output

P = I_rms²× R_ds(on)

loss ( )

Power losses in the control switch Q1 are given

by;

+ Q × V × f

(

)

⎛

⎜

Q_oss

⎞

⎠

P_loss= P_conduction+ P_switching+ P_drive+ P_output

×V × f + Q × V × f

(

)

⎝ 2

This can be expanded and approximated by;

*dissipated primarily in Q1.

= I ²× R_ds(on)

(

)

loss

rms

For the synchronous MOSFET Q2, R_ds(on)is an im-

portant characteristic; however, once again the im-

portance of gate charge must not be overlooked since

it impacts three critical areas. Under light load the

MOSFET must still be turned on and off by the con-

trol IC so the gate drive losses become much more

significant. Secondly, the output charge Q_ossand re-

verse recovery charge Q_rrboth generate losses that

are transfered to Q1 and increase the dissipation in

that device. Thirdly, gate charge will impact the

MOSFETs’ susceptibility to Cdv/dt turn on.

⎛

Q_gd

i_g

⎞

Q_gs2

i_g

⎞

⎟

⎜

⎟

⎜

+ I ×

× V × f + I ×

× V × f

⎝

⎠

⎝

⎠

+ Q × V × f

(

)

⎛ Q_oss

⎞

⎠

×V × f

⎝

This simplified loss equation includes the terms Q_gs2

The drain of Q2 is connected to the switching node

of the converter and therefore sees transitions be-

tween ground and V_in. As Q1 turns on and off there is

a rate of change of drain voltage dV/dt which is ca-

pacitively coupled to the gate of Q2 and can induce

a voltage spike on the gate that is sufficient to turn

the MOSFET on, resulting in shoot-through current .

The ratio of Q_gd/Q_gs1must be minimized to reduce the

potential for Cdv/dt turn on.

and Q_osswhich are new to Power MOSFET data sheets.

Q_gs2is a sub element of traditional gate-source

charge that is included in all MOSFET data sheets.

The importance of splitting this gate-source charge

into two sub elements, Q_gs1and Q_gs2, can be seen from

Fig 16.

Q_gs2indicates the charge that must be supplied by

the gate driver between the time that the threshold

voltage has been reached and the time the drain cur-

rent rises to I_dmaxat which time the drain voltage be-

gins to change. Minimizing Q_gs2is a critical factor in

reducing switching losses in Q1.

Q_ossis the charge that must be supplied to the out-

put capacitance of the MOSFET during every switch-

ing cycle. Figure A shows how Q_ossis formed by the

parallel combination of the voltage dependant (non-

linear) capacitances C_dsand C_dgwhen multiplied by

the power supply input buss voltage.

Figure A: Q_ossCharacteristic

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IRF3709ZCS/L

D²Pak Package Outline

Dimensions are shown in millimeters (inches)

D²Pak Part Marking Information

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IRF3709ZCS/L

TO-262 Package Outline

Dimensions are shown in millimeters (inches)

IGBT

1- GATE

2- COLLEC-

TOR

TO-262 Part Marking Information

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IRF3709ZCS/L

D²Pak Tape & Reel Information

Dimensions are shown in millimeters (inches)

TRR

1.60 (.063)

1.50 (.059)

1.60 (.063)

1.50 (.059)

4.10 (.161)

3.90 (.153)

0.368 (.0145)

0.342 (.0135)

FEED DIRECTION

TRL

11.60 (.457)

11.40 (.449)

1.85 (.073)

1.65 (.065)

24.30 (.957)

23.90 (.941)

15.42 (.609)

15.22 (.601)

1.75 (.069)

1.25 (.049)

10.90 (.429)

10.70 (.421)

4.72 (.136)

4.52 (.178)

16.10 (.634)

15.90 (.626)

FEED DIRECTION

13.50 (.532)

12.80 (.504)

27.40 (1.079)

23.90 (.941)

330.00

(14.173)

MAX.

60.00 (2.362)

MIN.

30.40 (1.197)

MAX.

NOTES :

1. COMFORMS TO EIA-418.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION MEASURED @ HUB.

4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.

26.40 (1.039)

24.40 (.961)

Notes:

Repetitive rating; pulse width limited by

max. junction temperature.

Starting T_J= 25°C, L = 0.42mH, R_G= 25Ω,

I_AS= 17A.

Pulse width ≤ 400µs; duty cycle ≤ 2%.

C_osseff. is a fixed capacitance that gives the same

ꢀ This is applied to D²Pak, when mounted on 1" square PCB (FR-

4 or G-10 Material). For recommended footprint and soldering

techniques refer to application note #AN-994.

Calculated continuous current based on maximum allowable

junction temperature. Package limitation current is 42A.

R is measured at T_Jof approximately 90°C.

charging time as C_osswhile V_DSis rising from 0 to

80% V_DSS

Data and specifications subject to change without notice.

This product has been designed and qualified for the Consumer market.

Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105

TAC Fax: (310) 252-7903

Visit us at www.irf.com for sales contact information. 01/04

www.irf.com

IRF3709ZCL [INFINEON]

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