IRF4905LPBF [INFINEON]
HEXFET Power MOSFET; HEXFET功率MOSFET
| 型号： | IRF4905LPBF |
| 厂家： | 
Infineon |
| 描述： | HEXFET Power MOSFET |
| 文件： | 总11页 (文件大小：358K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 97034
IRF4905SPbF
IRF4905LPbF
HEXFET® Power MOSFET
Features
O
Advanced Process Technology
Ultra Low On-Resistance
150°C Operating Temperature
Fast Switching
D
O
O
O
O
O
VDSS = -55V
RDS(on) = 20mΩ
Repetitive Avalanche Allowed up to Tjmax
Some Parameters Are Differrent from
IRF4905S
G
ID = -42A
S
O
Lead-Free
D
D
Description
Features of this design are a 150°C junction oper-
ating temperature, fast switching speed and im-
proved repetitive avalanche rating . These features
combine to make this design an extremely efficient
and reliable device for use in a wide variety of other
applications.
S
S
D
D
G
G
D2Pak
TO-262
IRF4905LPbF
IRF4905SPbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Parameter
Max.
Units
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Package Limited)
Pulsed Drain Current
-70
I
I
I
I
@ T = 25°C
C
D
D
D
-44
@ T = 100°C
C
A
-42
@ T = 25°C
C
-280
DM
170
P
@T = 25°C Power Dissipation
C
W
W/°C
V
D
1.3
Linear Derating Factor
± 20
V
Gate-to-Source Voltage
GS
EAS (Thermally limited)
140
790
Single Pulse Avalanche Energy
Single Pulse Avalanche Energy Tested Value
Avalanche Current
mJ
EAS (Tested )
IAR
See Fig.12a, 12b, 15, 16
A
EAR
Repetitive Avalanche Energy
Operating Junction and
mJ
-55 to + 150
T
T
J
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
°C
STG
300 (1.6mm from case )
10 lbf in (1.1N m)
Thermal Resistance
Parameter
Typ.
–––
Max.
0.75
40
Units
RθJC
RθJA
Junction-to-Case
Junction-to-Ambient (PCB Mount, steady state)
–––
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1
8/5/05
IRF4905S/L
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
Conditions
VGS = 0V, ID = -250µA
V(BR)DSS
∆V(BR)DSS/∆TJ
RDS(on)
VGS(th)
Drain-to-Source Breakdown Voltage
-55
–––
–––
V
Reference to 25°C, ID = -1mA
Breakdown Voltage Temp. Coefficient ––– -0.054 ––– V/°C
V
GS = -10V, ID = -42A
mΩ
V
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
–––
-2.0
19
–––
–––
–––
–––
20
VDS = VGS, ID = -250µA
VDS = -25V, ID = -42A
-4.0
–––
-25
gfs
Forward Transconductance
S
V
V
DS = -55V, VGS = 0V
IDSS
Drain-to-Source Leakage Current
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
µA
DS = -44V, VGS = 0V, TJ = 125°C
––– -200
––– 100
––– -100
VGS = -20V
GS = 20V
ID = -42A
DS = -44V
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
nA
nC
V
Qg
Qgs
Qgd
td(on)
tr
120
32
53
20
99
51
64
7.5
180
–––
–––
–––
–––
–––
–––
–––
V
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
VGS = -10V
VDD = -28V
ID = -42A
Rise Time
R
G = 2.6 Ω
VGS = -10V
nH Between lead,
and center of die contact
VGS = 0V
DS = -25V
td(off)
tf
Turn-Off Delay Time
ns
Fall Time
LS
Internal Source Inductance
Ciss
Coss
Crss
Coss
Coss
Input Capacitance
––– 3500 –––
––– 1250 –––
V
Output Capacitance
ƒ = 1.0MHz
Reverse Transfer Capacitance
Output Capacitance
–––
––– 4620 –––
––– 940 –––
––– 1530 –––
450
–––
pF
VGS = 0V, VDS = -1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = -44V, ƒ = 1.0MHz
Output Capacitance
V
GS = 0V, VDS = 0V to -44V
Coss eff.
Effective Output Capacitance
Source-Drain Ratings and Characteristics
Parameter
Min. Typ. Max. Units
Conditions
MOSFET symbol
I
Continuous Source Current
–––
–––
-42
S
showing the
(Body Diode)
A
integral reverse
I
Pulsed Source Current
(Body Diode)
–––
––– -280
SM
p-n junction diode.
T = 25°C, I = -42A, V = 0V
V
t
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
–––
–––
–––
–––
61
-1.3
92
V
J
S
GS
SD
T = 25°C, I = -42A, VDD = -28V
ns
nC
J
F
rr
di/dt = -100A/µs
Q
150
220
rr
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
t
on
2
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IRF4905S/L
1000
100
10
1000
100
10
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
-4.5V
VGS
TOP
TOP
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
-4.5V
BOTTOM
BOTTOM
-4.5V
-4.5V
≤ 60µs PULSE WIDTH
Tj = 25°C
≤ 60µs PULSE WIDTH
Tj = 150°C
1
1
0.1
1
10
100
1000
0.1
1
10
100
1000
-V , Drain-to-Source Voltage (V)
-V , Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.0
100.0
10.0
1.0
40
T
= 25°C
T
= 25°C
J
J
T
= 150°C
J
30
20
10
0
T
= 150°C
J
V
= -25V
DS
≤ 60µs PULSE WIDTH
V
= -10V
DS
380µs PULSE WIDTH
0.1
3
4
5
6
7
8
9
10 11 12 13 14
0
20
40
60
80
-V , Gate-to-Source Voltage (V)
GS
-I Drain-to-Source Current (A)
D,
Fig 3. Typical Transfer Characteristics
Fig 4. Typical Forward Transconductance
Vs. Drain Current
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3
IRF4905S/L
7000
20
16
12
8
V
C
= 0V,
f = 1 MHZ
GS
I = -42A
D
= C + C , C SHORTED
iss
gs
gd ds
6000
5000
4000
3000
2000
1000
0
V
= -44V
C
= C
DS
rss
gd
VDS= -28V
VDS= -11V
C
= C + C
oss
ds
gd
Ciss
Coss
Crss
4
0
0
40
80
120
160
200
1
10
100
Q
Total Gate Charge (nC)
G
-V , Drain-to-Source Voltage (V)
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000.0
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100.0
10.0
1.0
T
= 150°C
100µsec
10msec
J
1msec
LIMITED BY PACKAGE
T
= 25°C
J
DC
Tc = 25°C
Tj = 150°C
Single Pulse
V
= 0V
GS
1.6
1
0.1
0
1
10
100
0.0
0.4
0.8
1.2
2.0
-V
DS
, Drain-toSource Voltage (V)
-V , Source-to-Drain Voltage (V)
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRF4905S/L
2.0
1.5
1.0
0.5
80
60
40
20
0
I
= -42A
LIMITED BY PACKAGE
D
V
= -10V
GS
25
50
T
75
100
125
150
-60 -40 -20
T
0
20 40 60 80 100 120 140 160
, Case Temperature (°C)
C
, Junction Temperature (°C)
J
Fig 10. Normalized On-Resistance
Fig 9. Maximum Drain Current Vs.
Vs. Temperature
Case Temperature
1
D = 0.50
0.20
0.1
0.10
0.05
R1
R2
R2
R3
R3
Ri (°C/W) τi (sec)
0.1165 0.000068
R1
τ
JτJ
τ
Cτ
τ
0.02
0.01
τ
1τ1
τ
2 τ2
3τ3
0.3734 0.002347
0.2608 0.014811
0.01
Ci= τi/Ri
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF4905S/L
L
V
DS
600
500
400
300
200
100
0
I
D.U.T
AS
R
D
G
V
DD
A
TOP
-17A
-30A
-42A
I
DRIVER
-20V
BOTTOM
0.01
t
Ω
p
15V
Fig 12a. Unclamped Inductive Test Circuit
I
AS
25
50
75
100
125
150
Starting T , Junction Temperature (°C)
J
t
p
V
(BR)DSS
Fig 12c. Maximum Avalanche Energy
Fig 12b. Unclamped Inductive Waveforms
Vs. Drain Current
Q
G
3.6
10V
Q
Q
GD
GS
V
G
3.2
2.8
2.4
2.0
Charge
I
= -250µA
D
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
.2µF
12V
.3µF
-
V
+
DS
D.U.T.
V
GS
-75 -50 -25
0
25
50
75 100 125 150
-3mA
T
, Temperature ( °C )
J
I
I
D
G
Current Sampling Resistors
Fig 14. Threshold Voltage Vs. Temperature
Fig 13b. Gate Charge Test Circuit
6
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IRF4905S/L
1000
100
10
Duty Cycle = Single Pulse
0.01
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses. Note: In no
case should Tj be allowed to
exceed Tjmax
0.05
0.10
1
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
160
120
80
40
0
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
TOP
BOTTOM 1% Duty Cycle
= -42A
Single Pulse
I
D
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
25
50
75
100
125
150
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
Starting T , Junction Temperature (°C)
J
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
Fig 16. Maximum Avalanche Energy
EAS (AR) = PD (ave)·tav
Vs. Temperature
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7
IRF4905S/L
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
D.U.T**
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Curent
I
SD
Ripple ≤ 5%
** Reverse Polarity of D.U.T for P-Channel
* VGS = 5V for Logic Level Devices
Fig 17. Peak Diode Recovery dv/dt Test Circuit for P-Channel
HEXFET® Power MOSFETs
RD
VDS
VGS
D.U.T.
RG
-
+
VDD
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 18a. Switching Time Test Circuit
t
t
r
t
t
f
d(on)
d(off)
V
GS
10%
90%
V
DS
Fig 18b. Switching Time Waveforms
8
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IRF4905S/L
D2Pak Package Outline (Dimensions are shown in millimeters (inches))
D2Pak Part Marking Information
THIS IS AN IRF530S WITH
PART NUMBER
LOT CODE 8024
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLED ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
F530S
DATE CODE
YEAR 0 = 2000
WEEK 02
Note: "P" in assembly line
position indicates "Lead-Free"
ASSEMBLY
LOT CODE
LINE L
OR
PART NUMBER
DATE CODE
INTERNATIONAL
RECTIFIER
LOGO
F530S
P = DE S I GNAT E S L E AD-F RE E
PRODUCT (OPTIONAL)
YEAR 0 = 2000
ASSEMBLY
LOT CODE
WEEK 02
A= ASSEMBLY SITE CODE
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9
IRF4905S/L
TO-262 Package Outline (Dimensions are shown in millimeters (inches))
IGBT
1- GATE
2- COLLECTOR
3- EMITTER
4- COLLECTOR
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L
LOT CODE 1789
ASSEMBLED ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
DATE CODE
YEAR 7 = 1997
WE EK 19
Note: "P" in assembly line
pos ition indicates "L ead-F ree"
AS S E MB LY
LOT CODE
LINE C
OR
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
DATE CODE
P = DE S IGNAT E S L E AD-F RE E
PRODUCT (OPTIONAL)
YEAR 7 = 1997
AS S E MBL Y
LOT CODE
WEEK 19
A = AS S E MB L Y S IT E CODE
10
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IRF4905S/L
D2Pak Tape & Reel Information
TRR
1.60 (.063)
1.50 (.059)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
0.368 (.0145)
0.342 (.0135)
FEED DIRECTION
1.85 (.073)
11.60 (.457)
11.40 (.449)
1.65 (.065)
24.30 (.957)
23.90 (.941)
15.42 (.609)
15.22 (.601)
TRL
1.75 (.069)
1.25 (.049)
10.90 (.429)
10.70 (.421)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039)
24.40 (.961)
4
3
Notes:
ꢀ
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C, L = 0.16mH
RG = 25Ω, IAS = -42A, VGS =-10V. Part not
recommended for use above this value.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the
same charging time as Coss while VDS is rising
This value determined from sample failure population. 100%
tested to this value in production.
This is applied to D2Pak, when mounted on 1" square PCB (FR-
4 or G-10 Material). For recommended footprint and soldering
techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C
from 0 to 80% VDSS
.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 08/05
www.irf.com
11
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