IRF7811APBF [INFINEON]

HEXFET Power MOSFET; HEXFET功率MOSFET
IRF7811APBF
型号: IRF7811APBF
厂家: Infineon    Infineon
描述:

HEXFET Power MOSFET
HEXFET功率MOSFET

晶体 晶体管 功率场效应晶体管 开关 脉冲 光电二极管
文件: 总10页 (文件大小:196K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
PD - 95264A  
IRF7811APbF  
HEXFET® Power MOSFET  
Applications  
l High Frequency Synchronous Buck  
Converters for Computer Processor Power  
VDSS  
28V  
RDS(on) max  
Qg  
17nC  
l High Frequency Isolated DC-DC  
Converters with Synchronous Rectification  
for Telecom and Industrial Use  
l 100% RG Tested  
12mΩ  
A
A
D
l Lead-Free  
1
2
3
4
8
7
S
S
S
G
D
6
5
D
D
Benefits  
l Very Low RDS(on) at 4.5V VGS  
l Ultra-Low Gate Impedance  
l Fully Characterized Avalanche Voltage  
and Current  
SO-8  
Top View  
Absolute Maximum Ratings  
Symbol  
@ TA = 25°C  
@ TA = 70°C  
Parameter  
Continuous Drain Current, VGS @ 10V  
Max  
11  
Units  
I
I
I
D
D
Continuous Drain Current, VGS @ 10V  
Pulsed Drain Current  
9.1  
A
91  
DM  
Power Dissipation  
P
P
@TA = 25°C  
@TA = 70°C  
2.5  
1.6  
D
D
W
Power Dissipation  
Linear Derating Factor  
Gate-to-Source Voltage  
0.02  
±12  
W/°C  
V
VGS  
T
J
Operating Junction and  
-55 to + 150  
T
Storage Temperature Range  
°C  
STG  
Smoldering Temperature, for 10 seconds  
300 (1.6mm from case)  
Thermal Resistance  
Symbol  
Parameter  
Junction-to-Drain Lead  
Junction-to-Ambient  
Typ  
–––  
–––  
Max  
20  
Units  
Rθ  
Rθ  
JL  
°C/W  
50  
JA  
Notes  through are on page 10  
www.irf.com  
1
1/11/05  
IRF7811APbF  
Static @ TJ = 25°C (unless otherwise specified)  
Symbol  
BVDSS  
Parameter  
Min. Typ. Max. Units  
28 ––– –––  
––– 0.025 –––  
Conditions  
VGS = 0V, ID = 250µA  
Drain-to-Source Breakdown Voltage  
Breakdown Voltage Temp. Coefficient  
V
V
/ T  
V/°C Reference to 25°C, ID = 1mA  
VGS = 10V, ID = 11A  
∆Β  
DSS  
J
–––  
–––  
1.0  
8.7  
10  
10  
12  
RDS(on)  
m
Static Drain-to-Source On-Resistance  
V
GS = 4.5V, ID = 9.0A  
VGS(th)  
Gate Threshold Voltage  
–––  
-4.0  
3.0  
V
V
DS = VGS, ID = 250µA  
V
Gate Threshold Voltage Coefficient  
–––  
––– mV/°C  
GS(th)  
VDS = 28V, VGS = 0V  
–––  
–––  
–––  
–––  
28  
–––  
–––  
–––  
–––  
–––  
17  
1.0  
µA  
IDSS  
Drain-to-Source Leakage Current  
150  
VDS = 24V, VGS = 0V, TJ = 100°C  
VGS = 12V  
Gate-to-Source Forward Leakage  
Gate-to-Source Reverse Leakage  
Forward Transconductance  
Total Gate Charge  
100  
nA  
-100  
IGSS  
VGS = -12V  
gfs  
–––  
26  
S
V
DS = 15V, ID = 9.0A  
Qg  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
0.9  
Qgs1  
Qgs2  
Qgd  
Qgodr  
Qsw  
Qoss  
RG  
Pre-Vth Gate-Source Charge  
Post-Vth Gate-Source Charge  
Gate-to-Drain Charge  
3.3  
1.3  
4.7  
7.2  
6.0  
24  
–––  
–––  
–––  
–––  
–––  
–––  
3.7  
V
DS = 15V  
VGS = 4.5V  
D = 9.0A  
See Fig. 16  
nC  
I
Gate Charge Overdrive  
Switch Charge (Qgs2 + Qgd  
Output Charge  
)
nC VDS = 16V, VGS = 0V  
Gate Resistance  
Turn-On Delay Time  
Rise Time  
–––  
7.5  
4.1  
19  
td(on)  
tr  
td(off)  
tf  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
–––  
V
DD = 15V, VGS = 4.5V  
I
D = 9.0A  
ns  
Turn-Off Delay Time  
Fall Time  
Clamped Inductive Load  
6.5  
Ciss  
Coss  
Crss  
Input Capacitance  
Output Capacitance  
––– 1760 –––  
VGS = 0V  
pF  
–––  
–––  
960  
54  
–––  
–––  
VDS = 15V  
ƒ = 1.0MHz  
Reverse Transfer Capacitance  
Avalanche Characteristics  
Parameter  
Typ.  
–––  
–––  
Max.  
58  
Units  
mJ  
Symbol  
EAS  
IAR  
Single Pulse Avalanche Energy  
Avalanche Current  
9.0  
A
Diode Characteristics  
Symbol  
Parameter  
Continuous Source Current  
(Body Diode)  
Min. Typ. Max. Units  
Conditions  
MOSFET symbol  
showing the  
IS  
–––  
–––  
11  
A
Pulsed Source Current  
(Body Diode)  
integral reverse  
ISM  
–––  
–––  
91  
p-n junction diode.  
–––  
–––  
–––  
0.8  
0.66  
72  
1.0  
–––  
110  
T
T
T
= 25°C, I = 9.0A, V  
= 0V  
GS  
J
J
J
S
VSD  
trr  
Diode Forward Voltage  
V
= 125°C, I = 9.0A, VGS = 0V  
S
Reverse Recovery Time  
ns  
= 25°C, I = 9.0A, VR = 15V  
F
Qrr  
trr  
Reverse Recovery Charge  
Reverse Recovery Time  
–––  
–––  
93  
73  
140  
110  
nC di/dt = 100A/µs  
ns = 125°C, I = 9.0A, VR = 15V  
nC di/dt = 100A/µs  
T
J
F
Qrr  
Reverse Recovery Charge  
–––  
100  
150  
2
www.irf.com  
IRF7811APbF  
100  
10  
1
100  
10  
VGS  
VGS  
TOP  
10V  
4.5V  
3.5V  
2.7V  
2.5V  
2.0V  
1.8V  
TOP  
10V  
4.5V  
3.5V  
2.7V  
2.5V  
2.0V  
1.8V  
BOTTOM 1.5V  
BOTTOM 1.5V  
1
1.5V  
0.1  
0.01  
20µs PULSE WIDTH  
Tj = 150°C  
20µs PULSE WIDTH  
Tj = 25°C  
1.5V  
0.1  
0.1  
1
10  
100  
0.1  
1
10  
100  
V
, Drain-to-Source Voltage (V)  
V
, Drain-to-Source Voltage (V)  
DS  
DS  
Fig 1. Typical Output Characteristics  
Fig 2. Typical Output Characteristics  
100.00  
10.00  
1.00  
2.0  
I
= 11A  
D
V
= 10V  
GS  
T
= 150°C  
J
1.5  
1.0  
0.5  
T
= 25°C  
J
0.10  
V
= 15V  
DS  
20µs PULSE WIDTH  
0.01  
1.4  
1.8  
2.2  
2.6  
3.0  
3.4  
-60 -40 -20  
T
0
20 40 60 80 100 120 140 160  
V
, Gate-to-Source Voltage (V)  
, Junction Temperature (°C)  
GS  
J
Fig 3. Typical Transfer Characteristics  
Fig 4. Normalized On-Resistance  
Vs. Temperature  
www.irf.com  
3
IRF7811APbF  
12  
10  
8
100000  
V
= 0V,  
f = 1 MHZ  
GS  
I = 9.0A  
D
V
=1 5V  
C
= C + C  
,
C
SHORTED  
DS  
iss  
gs  
gd  
ds  
C
= C  
rss  
gd  
C
= C + C  
10000  
1000  
100  
oss  
ds  
gd  
Ciss  
6
Coss  
4
2
Crss  
0
10  
0
10  
20  
30  
40  
1
10  
100  
Q
Total Gate Charge (nC)  
G
V
, Drain-to-Source Voltage (V)  
DS  
Fig 6. Typical Gate Charge Vs.  
Fig 5. Typical Capacitance Vs.  
Gate-to-Source Voltage  
Drain-to-Source Voltage  
100.0  
1000  
100  
10  
OPERATION IN THIS AREA  
LIMITED BY R (on)  
DS  
10.0  
1.0  
T
= 150°C  
J
100µsec  
1msec  
T
= 25°C  
J
1
10msec  
Tc = 25°C  
Tj = 150°C  
Single Pulse  
V
= 0V  
GS  
0.1  
0.1  
0
1
10  
100  
1000  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
V
, Drain-toSource Voltage (V)  
V
, Source-toDrain Voltage (V)  
DS  
SD  
Fig 7. Typical Source-Drain Diode  
Fig 8. Maximum Safe Operating Area  
Forward Voltage  
4
www.irf.com  
IRF7811APbF  
12  
10  
8
RD  
VDS  
VGS  
10V  
D.U.T.  
RG  
+VDD  
-
6
Pulse Width ≤ 1 µs  
Duty Factor ≤ 0.1 %  
4
Fig 10a. Switching Time Test Circuit  
2
V
DS  
90%  
0
25  
50  
75  
100  
125  
150  
T
, Junction Temperature (°C)  
J
10%  
Fig 9. Maximum Drain Current Vs.  
V
GS  
Ambient Temperature  
t
t
r
t
t
f
d(on)  
d(off)  
Fig 10b. Switching Time Waveforms  
100  
D = 0.50  
0.20  
0.10  
0.05  
10  
P
2
DM  
0.02  
0.01  
1
t
1
t
2
Notes:  
SINGLE PULSE  
1. Duty factor D =  
2. Peak T = P  
J
t / t  
1
x Z  
(THERMAL RESPONSE)  
+ T  
10  
DM  
thJA  
A
0.1  
0.00001  
0.0001  
0.001  
0.01  
0.1  
1
100  
t , Rectangular Pulse Duration (sec)  
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient  
www.irf.com  
5
IRF7811APbF  
0.013  
0.011  
0.009  
0.007  
0.005  
0.03  
0.02  
0.01  
0.00  
V
V
= 4.5V  
= 10V  
GS  
I
= 9.0A  
D
GS  
2.0  
3.0  
V
4.0  
5.0  
6.0  
7.0  
8.0  
9.0 10.0  
0
10  
20  
30  
40  
50  
60  
Gate -to -Source Voltage (V)  
I
, Drain Current (A)  
GS,  
D
Fig 12. On-Resistance Vs. Drain Current  
Fig 13. On-Resistance Vs. Gate Voltage  
Current Regulator  
Same Type as D.U.T.  
50KΩ  
.2µF  
12V  
.3µF  
140  
+
ID  
V
DS  
D.U.T.  
-
TOP  
4.0A  
7.2A  
120  
100  
80  
60  
40  
20  
0
V
GS  
BOTTOM 9.0A  
3mA  
I
I
D
G
Current Sampling Resistors  
Fig 14. Basic Gate Charge Test Circuit  
15V  
V
(BR)DSS  
DRIVER  
+
L
t
p
V
DS  
D.U.T  
AS  
R
G
V
25  
50  
75  
100  
125  
150  
DD  
-
I
A
20V  
Starting T , Junction Temperature (°C)  
0.01  
t
p
J
I
AS  
Fig 15c. Maximum Avalanche Energy  
Fig 15a&b. Unclamped Inductive Test circuit  
Vs. Drain Current  
and Waveforms  
6
www.irf.com  
IRF7811APbF  
Driver Gate Drive  
P.W.  
P.W.  
Period  
D.U.T  
Period  
D =  
+
ƒ
-
*
=10V  
V
GS  
Circuit Layout Considerations  
Low Stray Inductance  
Ground Plane  
Low Leakage Inductance  
Current Transformer  
D.U.T. I Waveform  
SD  
+
‚
-
Reverse  
Recovery  
Current  
Body Diode Forward  
„
Current  
-
+
di/dt  
D.U.T. V Waveform  
DS  
Diode Recovery  
dv/dt  

V
DD  
VDD  
Re-Applied  
Voltage  
dv/dt controlled by RG  
RG  
+
-
Body Diode  
Forward Drop  
Driver same type as D.U.T.  
ISD controlled by Duty Factor "D"  
D.U.T. - Device Under Test  
Inductor Curent  
I
SD  
Ripple 5%  
* VGS = 5V for Logic Level Devices  
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel  
HEXFET® Power MOSFETs  
Id  
Vds  
Vgs  
Vgs(th)  
Qgs1  
Qgs2  
Qgd  
Qgodr  
Fig 16. Gate Charge Waveform  
www.irf.com  
7
IRF7811APbF  
Power MOSFET Selection for Non-Isolated DC/DC Converters  
Synchronous FET  
Control FET  
The power loss equation for Q2 is approximated  
by;  
Special attention has been given to the power losses  
in the switching elements of the circuit - Q1 and Q2.  
Power losses in the high side switch Q1, also called  
the Control FET, are impacted by the Rds(on) of the  
MOSFET, but these conduction losses are only about  
one half of the total losses.  
P = P  
+ P + P*  
loss  
conduction  
drive  
output  
P = Irms 2 × Rds(on)  
loss ( )  
Power losses in the control switch Q1 are given  
by;  
+ Q × V × f  
(
)
g
g
Qoss  
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput  
+
×V × f + Q × V × f  
(
)
in  
rr  
in  
2  
This can be expanded and approximated by;  
*dissipated primarily in Q1.  
P
= I 2 × Rds(on )  
(
)
loss  
rms  
For the synchronous MOSFET Q2, Rds(on) is an im-  
portant characteristic; however, once again the im-  
portance of gate charge must not be overlooked since  
it impacts three critical areas. Under light load the  
MOSFET must still be turned on and off by the con-  
trol IC so the gate drive losses become much more  
significant. Secondly, the output charge Qoss and re-  
verse recovery charge Qrr both generate losses that  
are transfered to Q1 and increase the dissipation in  
that device. Thirdly, gate charge will impact the  
MOSFETs’ susceptibility to Cdv/dt turn on.  
Qgd  
ig  
Qgs2  
ig  
+ I ×  
× V × f + I ×  
× V × f  
in  
in  
+ Q × V × f  
(
)
g
g
Qoss  
+
×V × f  
in  
2
This simplified loss equation includes the terms Qgs2  
The drain of Q2 is connected to the switching node  
of the converter and therefore sees transitions be-  
tween ground and Vin. As Q1 turns on and off there is  
a rate of change of drain voltage dV/dt which is ca-  
pacitively coupled to the gate of Q2 and can induce  
a voltage spike on the gate that is sufficient to turn  
the MOSFET on, resulting in shoot-through current .  
The ratio of Qgd/Qgs1 must be minimized to reduce the  
potential for Cdv/dt turn on.  
and Qoss which are new to Power MOSFET data sheets.  
Qgs2 is a sub element of traditional gate-source  
charge that is included in all MOSFET data sheets.  
The importance of splitting this gate-source charge  
into two sub elements, Qgs1 and Qgs2, can be seen from  
Fig 16.  
Qgs2 indicates the charge that must be supplied by  
the gate driver between the time that the threshold  
voltage has been reached and the time the drain cur-  
rent rises to Idmax at which time the drain voltage be-  
gins to change. Minimizing Qgs2 is a critical factor in  
reducing switching losses in Q1.  
Qoss is the charge that must be supplied to the out-  
put capacitance of the MOSFET during every switch-  
ing cycle. Figure A shows how Qoss is formed by the  
parallel combination of the voltage dependant (non-  
linear) capacitance’s Cds and Cdg when multiplied by  
the power supply input buss voltage.  
Figure A: Qoss Characteristic  
8
www.irf.com  
IRF7811APbF  
SO-8 Package Outline  
Dimensions are shown in millimeters (inches)  
INCHES  
MILLIMET ER S  
DIM  
A
D
B
MIN  
.0532  
MAX  
.0688  
.0098  
.020  
MIN  
1.35  
0.10  
0.33  
0.19  
4.80  
3.80  
MAX  
1.75  
0.25  
0.51  
0.25  
5.00  
4.00  
5
A
E
A1 .0040  
b
c
.013  
8
1
7
2
6
3
5
.0075  
.189  
.0098  
.1968  
.1574  
6
H
D
E
e
0.25 [.010]  
A
.1497  
4
.050 BASIC  
1.27 BASIC  
e 1 .025 BASIC  
0.635 BASIC  
H
K
L
y
.2284  
.0099  
.016  
0°  
.2440  
.0196  
.050  
8°  
5.80  
0.25  
0.40  
0°  
6.20  
0.50  
1.27  
8°  
e
6X  
e1  
K x 45°  
A
C
y
0.10 [.004]  
8X c  
A1  
B
8X L  
8X b  
0.25 [.010]  
7
C
A
F OOT PRINT  
8X 0.72 [.028]  
NOT ES :  
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.  
2. CONT ROLLING DIMENS ION: MILLIMET ER  
3. DIMENS IONS ARE SHOWN IN MILLIMETERS [INCHES].  
4. OUT L INE CONF OR MS T O JE DE C OU T L INE MS -012AA.  
5
6
7
DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS .  
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].  
6.46 [.255]  
DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS .  
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].  
DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO  
ASUBSTRATE.  
3X 1.27 [.050]  
8X 1.78 [.070]  
SO-8 Part Marking  
EXAMPLE: THIS IS AN IRF7101 (MOSFET)  
DATE CODE (YWW)  
P = DE S I GNAT E S L E AD-F R E E  
PRODUCT (OPTIONAL)  
Y= LAST DIGIT OF THE YEAR  
XXXX  
F7101  
WW = WEEK  
INTERNATIONAL  
RECTIFIER  
LOGO  
A = ASSEMBLYSITE CODE  
LOT CODE  
PART NUMBER  
www.irf.com  
9
IRF7811APbF  
SO-8 Tape and Reel  
Dimensions are shown in millimeters (inches)  
TERMINAL NUMBER 1  
12.3 ( .484 )  
11.7 ( .461 )  
8.1 ( .318 )  
7.9 ( .312 )  
FEED DIRECTION  
NOTES:  
1. CONTROLLING DIMENSION : MILLIMETER.  
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).  
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.  
330.00  
(12.992)  
MAX.  
14.40 ( .566 )  
12.40 ( .488 )  
NOTES :  
1. CONTROLLING DIMENSION : MILLIMETER.  
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.  
Notes:  
 Repetitive rating; pulse width limited by  
ƒ Pulse width 300µs; duty cycle 2%.  
max. junction temperature.  
„ When mounted on 1 inch square copper board  
Rθ is measured at TJ approximately at 90°C  
‚ Starting TJ = 25°C, L = 1.4mH  
RG = 25, IAS = 9.0A.  
Data and specifications subject to change without notice.  
This product has been designed and qualified for the Consumer market.  
Qualification Standards can be found on IR’s Web site.  
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105  
TAC Fax: (310) 252-7903  
Visit us at www.irf.com for sales contact information. 01/05  
10  
www.irf.com  

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