IRF7831UPBF [INFINEON]
HEXFET Power MOSFET; HEXFET功率MOSFET
| 型号： | IRF7831UPBF |
| 厂家： | 
Infineon |
| 描述： | HEXFET Power MOSFET |
| 文件： | 总10页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 96083A
IRF7831UPbF
HEXFET® Power MOSFET
Applications
VDSS
30V
RDS(on) max
Qg (typ.)
40nC
l High Frequency Point-of-Load
Synchronous Buck Converter for
Applications in Networking &
Computing Systems.
3.6m @VGS = 10V
A
A
D
1
8
S
Benefits
2
7
S
D
l Very Low RDS(on) at 4.5V VGS
l Ultra-Low Gate Impedance
l Fully Characterized Avalanche Voltage
and Current
l 100%TestedforRG
l Lead-Free
3
6
S
D
4
5
G
D
SO-8
Top View
Absolute Maximum Ratings
Parameter
Max.
30
Units
V
VDS
Drain-to-Source Voltage
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
V
± 12
21
GS
I
I
I
@ TA = 25°C
D
D
@ TA = 70°C
17
A
170
2.5
1.6
DM
Power Dissipation
P
P
@TA = 25°C
@TA = 70°C
W
D
D
Power Dissipation
Linear Derating Factor
Operating Junction and
0.02
-55 to + 150
W/°C
°C
T
J
T
Storage Temperature Range
STG
Thermal Resistance
Parameter
Junction-to-Drain Lead
Junction-to-Ambient
Typ.
–––
Max.
20
Units
°C/W
Rθ
Rθ
JL
–––
50
JA
Notes through are on page 10
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1
09/19/06
IRF7831UPbF
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Min. Typ. Max. Units
30 ––– –––
––– 0.025 –––
Conditions
VGS = 0V, ID = 250µA
BVDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
V
∆ΒVDSS/∆TJ
RDS(on)
V/°C Reference to 25°C, ID = 1mA
mΩ
2.5
3.0
3.1
3.7
–––
- 5.7
–––
–––
–––
–––
–––
40
3.6
4.4
VGS = 10V, ID = 20A
VGS = 4.5V, ID = 16A
VDS = VGS, ID = 250µA
VGS(th)
∆VGS(th)
IDSS
Gate Threshold Voltage
1.35
–––
–––
–––
–––
–––
97
2.35
V
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
––– mV/°C
1.0
150
100
-100
–––
60
µA
V
V
DS = 24V, VGS = 0V
DS = 24V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Forward Transconductance
Total Gate Charge
nA VGS = 12V
GS = -12V
V
gfs
S
VDS = 15V, ID = 16A
Qg
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Qgs1
Qgs2
Qgd
Qgodr
Qsw
Qoss
RG
Pre-Vth Gate-to-Source Charge
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
12
–––
–––
–––
–––
–––
–––
2.5
VDS = 15V
3.1
11
nC VGS = 4.5V
ID = 16A
Gate Charge Overdrive
14
See Fig. 16
Switch Charge (Qgs2 + Qgd
Output Charge
)
14
22
nC VDS = 16V, VGS = 0V
Ω
Gate Resistance
Turn-On Delay Time
Rise Time
1.4
18
td(on)
tr
td(off)
tf
–––
–––
–––
–––
VDD = 15V, VGS = 4.5V
10
ID = 16A
Turn-Off Delay Time
Fall Time
17
ns Clamped Inductive Load
5.3
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
––– 6240 –––
V
V
GS = 0V
–––
–––
980
390
–––
–––
pF
DS = 15V
Reverse Transfer Capacitance
ƒ = 1.0MHz
Avalanche Characteristics
Parameter
Typ.
–––
–––
Max.
Units
mJ
Single Pulse Avalanche Energy
Avalanche Current
EAS
IAR
100
16
A
Diode Characteristics
Parameter
Min. Typ. Max. Units
Conditions
IS
Continuous Source Current
–––
–––
2.5
MOSFET symbol
(Body Diode)
A
showing the
ISM
Pulsed Source Current
–––
–––
170
integral reverse
(Body Diode)
p-n junction diode.
VSD
trr
Diode Forward Voltage
–––
–––
–––
–––
42
1.2
62
47
V
T = 25°C, I = 16A, V = 0V
GS
J
S
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
ns T = 25°C, I = 16A, VDD = 25V
J F
Qrr
ton
2
31
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRF7831UPbF
1000
100
10
1000
100
10
VGS
10V
VGS
10V
TOP
TOP
5.0V
4.5V
3.5V
3.0V
2.7V
2.5V
5.0V
4.5V
3.5V
3.0V
2.7V
2.5V
BOTTOM 2.25V
BOTTOM 2.25V
1
2.25V
1
0.1
0.01
20µs PULSE WIDTH
Tj = 25°C
20µs PULSE WIDTH
Tj = 150°C
2.25V
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.0
2.0
I
= 20A
D
V
= 10V
GS
100.0
10.0
1.0
1.5
1.0
0.5
T
= 150°C
J
T
= 25°C
V
J
= 15V
DS
20µs PULSE WIDTH
0.1
2.0
2.5
3.0
3.5
4.0
-60 -40 -20
T
0
20 40 60 80 100 120 140 160
V
, Gate-to-Source Voltage (V)
, Junction Temperature (°C)
GS
J
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
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3
IRF7831UPbF
100000
12
10
8
V
= 0V,
= C
f = 1 MHZ
GS
I = 12A
D
C
C
C
+ C , C
SHORTED
ds
V
= 24V
iss
gs
gd
DS
VDS= 15V
= C
rss
oss
gd
= C + C
ds
gd
10000
1000
100
Ciss
6
Coss
Crss
4
2
0
0
20
Q
40
60
80
100
1
10
100
Total Gate Charge (nC)
V
, Drain-to-Source Voltage (V)
G
DS
Fig 6. Typical Gate Charge Vs.
Fig 5. Typical Capacitance Vs.
Gate-to-Source Voltage
Drain-to-Source Voltage
1000.0
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R
(on)
DS
100.0
10.0
1.0
T
= 150°C
J
100µsec
1msec
T
= 25°C
J
Tc = 25°C
Tj = 150°C
Single Pulse
V
= 0V
GS
10msec
100.0
1
0.1
0.1
1.0
10.0
1000.0
0.2
0.4
0.6
0.8
1.0
1.2
V
, Drain-toSource Voltage (V)
V
, Source-toDrain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
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IRF7831UPbF
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
24
20
16
12
8
I
= 250µA
D
4
0
-75 -50 -25
0
25
50
75 100 125 150
25
50
75
100
125
150
T
, Temperature ( °C )
T
J
, Junction Temperature (°C)
J
Fig 10. Threshold Voltage Vs. Temperature
Fig 9. Maximum Drain Current Vs.
Case Temperature
100
D = 0.50
0.20
10
1
0.10
0.05
0.02
0.01
Ri (°C/W) τi (sec)
R1
R1
R2
R2
R3
R3
R4
R4
R5
R5
0.514
2.445
20.64
17.80
8.604
0.000182
τ
τC
J τJ
τ
0.030949
0.36354
6.99
0.1
τ
1 τ1
τ
τ
τ
2 τ2
3 τ3
4 τ4
5 τ5
Ci= τi/Ri
109
0.01
0.001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthja + Tc
SINGLE PULSE
( THERMAL RESPONSE )
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t
, Rectangular Pulse Duration (sec)
1
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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5
IRF7831UPbF
500
400
300
200
100
0
15V
I
D
TOP
11A
13A
16A
DRIVER
+
L
BOTTOM
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
GS
Ω
0.01
t
p
Fig 12a. Unclamped Inductive Test Circuit
V
(BR)DSS
t
p
25
50
75
100
125
150
Starting T , Junction Temperature (°C)
J
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
LD
I
AS
VDS
Fig 12b. Unclamped Inductive Waveforms
+
-
VDD
D.U.T
VGS
Current Regulator
Same Type as D.U.T.
Pulse Width < 1µs
Duty Factor < 0.1%
50KΩ
.2µF
12V
Fig 14a. Switching Time Test Circuit
VDS
.3µF
+
V
DS
D.U.T.
-
90%
V
GS
3mA
10%
VGS
I
I
D
G
Current Sampling Resistors
td(on)
td(off)
tr
tf
Fig 13. Gate Charge Test Circuit
Fig 14b. Switching Time Waveforms
6
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IRF7831UPbF
Driver Gate Drive
P.W.
P.W.
Period
D.U.T
Period
D =
+
-
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Curent
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Id
Vds
Vgs
Vgs(th)
Qgs1
Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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7
IRF7831UPbF
Power MOSFET Selection for Non-Isolated DC/DC Converters
Synchronous FET
Control FET
The power loss equation for Q2 is approximated
by;
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
P = P
+ P + P*
loss
conduction
drive
output
P = Irms 2 × Rds(on)
loss ( )
Power losses in the control switch Q1 are given
by;
+ Q × V × f
(
)
g
g
⎛
⎜
Qoss
⎞
⎠
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
+
×V × f + Q × V × f
(
)
in
rr
in
⎝ 2
This can be expanded and approximated by;
*dissipated primarily in Q1.
P
= I 2 × Rds(on )
(
)
loss
rms
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
⎛
⎛
Qgd
ig
⎞
Qgs2
ig
⎞
⎟
⎜
⎟
⎜
+ I ×
× V × f + I ×
× V × f
in
in
⎝
⎠
⎝
⎠
+ Q × V × f
(
)
g
g
⎛ Qoss
⎞
⎠
+
×V × f
in
⎝
2
This simplified loss equation includes the terms Qgs2
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and off there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Figure A: Qoss Characteristic
8
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IRF7831UPbF
SO-8 Package Outline
Dimensions are shown in millimeters (inches)
INCHES
MILLIMETERS
DIM
A
D
B
MIN
.0532
MAX
.0688
.0098
.020
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
5
A
E
A1 .0040
b
c
D
E
.013
8
1
7
2
6
3
5
.0075
.189
.0098
.1968
.1574
6
H
0.25 [.010]
A
.1497
4
e
.050 BASIC
1.27 BASIC
0.635 BASIC
e1 .025 BASIC
H
K
L
.2284
.0099
.016
0°
.2440
.0196
.050
8°
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
e
6X
y
e1
A
K x 45°
A
C
y
0.10 [.004]
8X c
A1
B
8X L
8X b
0.25 [.010]
7
C
F OOT PRINT
8X 0.72 [.028]
NOT ES :
1. DIMENSIONING& TOLERANCINGPER ASME Y14.5M-1994.
2. CONT ROLLING DIMENS ION: MILLIMET ER
3. DIMENS IONS ARE SHOWN IN MILLIMETERS [INCHES].
4. OUT LINE CONF ORMS T O JE DEC OU T LINE MS -012AA.
5
6
7
DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS .
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
6.46 [.255]
DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS .
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
DIMENSION IS THE LENGTH OF LEAD FOR SOLDERINGTO
ASUBSTRATE.
3X 1.27 [.050]
8X 1.78 [.070]
SO-8 Part Marking
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9
IRF7831UPbF
SO-8 Tape and Reel
Dimensions are shown in milimeters (inches)
TERMINAL NUMBER 1
12.3 ( .484 )
11.7 ( .461 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS(INCHES).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
330.00
(12.992)
MAX.
14.40 ( .566 )
12.40 ( .488 )
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 0.76mH
RG = 25Ω, IAS = 16A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
When mounted on 1 inch square copper board
Data and specifications subject to change without notice.
This product has been designed and qualified for the Consumer market.
Qualifications Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 09/2006
10
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