IRFB4110PBF [INFINEON]
High Efficiency Synchronous Rectification in SMPS; 高效率同步整流开关电源
| 型号： | IRFB4110PBF |
| 厂家： | 
Infineon |
| 描述： | High Efficiency Synchronous Rectification in SMPS |
| 文件： | 总8页 (文件大小：709K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 97061A
IRFB4110PbF
Applications
HEXFET® Power MOSFET
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
VDSS
RDS(on) typ.
max
ID
100V
3.7m
4.5m
:
:
180A
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
D
Ruggedness
D
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
G
S
D
G
TO-220AB
S
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
Parameter
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current d
Max.
180c
130c
670
Units
A
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
370
W
Maximum Power Dissipation
Linear Derating Factor
2.5
W/°C
V
VGS
± 20
5.3
Gate-to-Source Voltage
Peak Diode Recovery f
dv/dt
TJ
V/ns
°C
-55 to + 175
Operating Junction and
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
300
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
Single Pulse Avalanche Energy e
EAS (Thermally limited)
210
75
mJ
A
Avalanche Currentꢀc
IAR
Repetitive Avalanche Energy g
EAR
37
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
Units
RθJC
0.402
–––
62
Junction-to-Case k
RθCS
RθJA
0.50
–––
°C/W
Case-to-Sink, Flat Greased Surface
Junction-to-Ambient j
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1
11/3/05
IRFB4110PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Min. Typ. Max. Units
100 ––– –––
––– 0.108 ––– V/°C Reference to 25°C, ID = 5mAd
Conditions
VGS = 0V, ID = 250µA
V
∆V(BR)DSS/∆TJ
RDS(on)
–––
2.0
3.7
4.5
4.0
20
VGS = 10V, ID = 75A g
mΩ
V
VGS(th)
–––
VDS = VGS, ID = 250µA
IDSS
Drain-to-Source Leakage Current
––– –––
µA
VDS = 100V, VGS = 0V
VDS = 100V, VGS = 0V, TJ = 125°C
VGS = 20V
V
––– ––– 250
––– ––– 100
––– ––– -100
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
nA
GS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
Conditions
VDS = 50V, ID = 75A
160 ––– –––
S
––– 150 210
nC ID = 75A
VDS = 50V
Qgs
Qgd
Gate-to-Source Charge
–––
–––
–––
35
43
–––
–––
Gate-to-Drain ("Miller") Charge
VGS = 10V g
RG
td(on)
Gate Resistance
Turn-On Delay Time
Rise Time
1.3
25
67
78
88
–––
–––
–––
–––
–––
Ω
–––
–––
–––
–––
ns VDD = 65V
ID = 75A
tr
td(off)
Turn-Off Delay Time
Fall Time
RG = 2.6Ω
VGS = 10V g
pF VGS = 0V
tf
Ciss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
––– 9620 –––
––– 670 –––
––– 250 –––
––– 820 –––
––– 950 –––
Coss
V
DS = 50V
ƒ = 1.0MHz
GS = 0V, VDS = 0V to 80V j
Crss
Coss eff. (ER)
Coss eff. (TR)
V
Effective Output Capacitance (Energy Related)
i
VGS = 0V, VDS = 0V to 80V h
Effective Output Capacitance (Time Related)
h
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IS
D
S
Continuous Source Current
––– –––
A
MOSFET symbol
170
c
(Body Diode)
showing the
integral reverse
G
ISM
Pulsed Source Current
(Body Diode)ꢀdi
Diode Forward Voltage
Reverse Recovery Time
––– ––– 670
p-n junction diode.
TJ = 25°C, IS = 75A, VGS = 0V g
VSD
trr
––– –––
1.3
75
V
TJ = 25°C
TJ = 125°C
TJ = 25°C
TJ = 125°C
TJ = 25°C
VR = 85V,
–––
–––
–––
50
60
94
ns
IF = 75A
90
di/dt = 100A/µs g
Qrr
Reverse Recovery Charge
140
nC
––– 140 210
––– 3.5 –––
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 75A.
Repetitive rating; pulse width limited by max. junction
temperature.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
.
.
Limited by TJmax, starting TJ = 25°C, L = 0.074mH
RG = 25Ω, IAS = 75A, VGS =10V. Part not recommended for use
above this value.
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
ISD ≤ 75A, di/dt ≤ 630A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
ꢁ Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
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IRFB4110PbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
4.5V
TOP
TOP
BOTTOM
BOTTOM
4.5V
4.5V
60µs PULSE WIDTH
Tj = 25°C
60µs PULSE WIDTH
Tj = 175°C
≤
≤
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
3.0
2.5
2.0
1.5
1.0
0.5
I
= 75A
D
V
= 10V
GS
T
= 25°C
J
T
= 175°C
J
1
V
= 25V
DS
≤
60µs PULSE WIDTH
0.1
1
2
3
4
5
6
7
-60 -40 -20 0 20 40 60 80 100120140160180
, Junction Temperature (°C)
T
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
100000
10000
1000
12.0
V
= 0V,
= C
f = 1 MHZ
GS
I = 75A
D
C
C
C
+ C , C
SHORTED
iss
gs
gd
ds
= C
10.0
rss
oss
gd
= C + C
V
V
= 80V
= 50V
ds
gd
DS
DS
C
8.0
6.0
4.0
2.0
0.0
iss
C
oss
C
rss
100
1
10
, Drain-to-Source Voltage (V)
100
0
50
100
150
200
V
Q , Total Gate Charge (nC)
DS
G
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB4110PbF
10000
1000
100
10
1000
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
T
= 175°C
J
100
10
1
100µsec
T
= 25°C
J
10msec
1msec
DC
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
GS
1
0.1
0
1
10
100
1000
0.0
0.5
1.0
1.5
2.0
V
, Drain-to-Source Voltage (V)
V
, Source-to-Drain Voltage (V)
DS
SD
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode Forward Voltage
180
125
120
115
110
105
100
95
Id = 5mA
160
Limited By Package
140
120
100
80
60
40
20
90
0
25
50
75
100
125
150
175
-60 -40 -20 0 20 40 60 80 100120140160180
T
, Temperature ( °C )
T
, Case Temperature (°C)
J
C
Fig 10. Drain-to-Source Breakdown Voltage
Fig 9. Maximum Drain Current vs. Case Temperature
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
900
I
D
800
700
600
500
400
300
200
100
0
TOP
17A
26A
BOTTOM 75A
0
20
V
40
60
80
100
120
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
Drain-to-Source Voltage (V)
DS,
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
Fig 11. Typical COSS Stored Energy
4
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IRFB4110PbF
1
0.1
D = 0.50
0.20
0.10
0.05
R1
R1
R2
R2
R3
R3
τi (sec)
0.09876251 0.000111
0.2066697 0.001743
0.09510464 0.012269
0.02
0.01
Ri (°C/W)
0.01
τ
J τJ
τ
τ
CτC
τ
1 τ1
τ
2 τ2
3 τ3
Ci= τi/Ri
Ci= τi/Ri
0.001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Duty Cycle = Single Pulse
1000
100
10
Allowed avalanche Current vs
avalanche pulsewidth, tav
0.01
∆
assuming
Tj = 25°C due to
0.05
0.10
avalanche losses
1
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
250
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
= 75A
I
D
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
Starting T , Junction Temperature (°C)
EAS (AR) = PD (ave)·tav
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB4110PbF
25
20
15
10
5
4.0
3.5
3.0
2.5
I = 30A
F
V
= 85V
R
T = 25°C
J
T = 125°C
J
I
I
I
= 250µA
= 1.0mA
= 1.0A
D
D
D
2.0
1.5
1.0
0.5
0
0
200
400
600
800
1000
-75 -50 -25
0
25 50 75 100 125 150 175 200
, Temperature ( °C )
di /dt (A/µs)
T
F
J
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
25
560
I = 45A
I = 30A
F
F
V
= 85V
V
= 85V
R
R
480
400
320
240
160
80
20
15
10
5
T = 25°C
T = 25°C
J
J
T = 125°C
J
T = 125°C
J
0
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt (A/µs)
di /dt (A/µs)
F
F
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
560
I = 45A
F
V
= 85V
R
480
400
320
240
160
80
T = 25°C
J
T = 125°C
J
0
200
400
600
800
1000
di /dt (A/µs)
F
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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IRFB4110PbF
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
D.U.T
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
0.01Ω
t
p
I
AS
Fig 21b. Unclamped Inductive Waveforms
Fig 21a. Unclamped Inductive Test Circuit
LD
VDS
VDS
90%
+
-
VDD
10%
VGS
D.U.T
VGS
Pulse Width < 1µs
Duty Factor < 0.1%
td(on)
td(off)
tr
tf
Fig 22a. Switching Time Test Circuit
Fig 22b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
Vgs(th)
0
1K
Qgs1
Qgs2
Qgd
Qgodr
Fig 23a. Gate Charge Test Circuit
Fig 23b. Gate Charge Waveform
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7
IRFB4110PbF
TO-220AB Package Outline (Dimensions are shown in millimeters (inches))
TO-220AB Part Marking Information
Note: "P" in assembly line
position indicates "Lead-Free"
TO-220AB packages are not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 11/05
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8
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