IRFB4321 [INFINEON]
The StrongIRFET™ power MOSFET family is optimized for low RDS(on) and high current capability. The devices are ideal for low frequency applications requiring performance and ruggedness. The comprehensive portfolio addresses a broad range of applications including DC motors, battery management systems, inverters, and DC-DC converters. ;
| 型号： | IRFB4321 |
| 厂家： | 
Infineon |
| 描述： | The StrongIRFET™ power MOSFET family is optimized for low RDS(on) and high current capability. The devices are ideal for low frequency applications requiring performance and ruggedness. The comprehensive portfolio addresses a broad range of applications including DC motors, battery management systems, inverters, and DC-DC converters. |
| 文件： | 总9页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PD - 97103B
IRFB4321PbF
HEXFET® Power MOSFET
Applications
l Motion Control Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l Hard Switched and High Frequency Circuits
VDSS
RDS(on) typ.
150V
12m
15m
:
:
max.
Benefits
ID
85A
l Low RDSON Reduces Losses
l Low Gate Charge Improves the Switching
Performance
l Improved Diode Recovery Improves Switching &
EMI Performance
D
S
D
l 30V Gate Voltage Rating Improves Robustness
l Fully Characterized Avalanche SOA
S
G
D
G
TO-220AB
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Parameter
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current d
Max.
85 c
60
Units
A
330
PD @TC = 25°C
350
Maximum Power Dissipation
Linear Derating Factor
W
2.3
W/°C
V
VGS
±30
Gate-to-Source Voltage
Single Pulse Avalanche Energy e
EAS (Thermally limited)
120
mJ
°C
TJ
-55 to + 175
Operating Junction and
TSTG
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
300
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw
Thermal Resistance
Parameter
Junction-to-Case g
Typ.
–––
0.50
–––
Max.
0.43
–––
62
Units
RθJC
RθCS
RθJA
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient g
°C/W
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1
12/9/10
IRFB4321PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Min. Typ. Max. Units
150 ––– –––
––– 150 ––– mV/°C Reference to 25°C, ID = 1mA
Conditions
VGS = 0V, ID = 250μA
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
V
ΔV(BR)DSS/ΔTJ
RDS(on)
–––
3.0
12
15
5.0
20
VGS = 10V, ID = 33A
mΩ
V
VGS(th)
–––
VDS = VGS, ID = 250μA
IDSS
Drain-to-Source Leakage Current
––– –––
––– –––
μA
VDS = 150V, VGS = 0V
1.0
mA VDS = 150V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
––– ––– 100
––– ––– -100
nA
V
GS = 20V
VGS = -20V
RG(int)
–––
0.8
–––
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Parameter
Forward Transconductance
Total Gate Charge
Min. Typ. Max. Units
130 ––– –––
Conditions
VDS = 25V, ID = 50A
S
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
71
24
110
–––
–––
–––
–––
–––
–––
–––
–––
–––
nC ID = 50A
VDS = 75V
Qgs
Qgd
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
21
VGS = 10V
18
ns VDD = 98V
ID = 50A
60
td(off)
tf
Turn-Off Delay Time
Fall Time
25
RG = 2.5Ω
VGS = 10V
35
Ciss
Coss
Crss
Input Capacitance
pF VGS = 0V
VDS = 50V
4460
390
82
Output Capacitance
Reverse Transfer Capacitance
ƒ = 1.0MHz
Diode Characteristics
Symbol
Parameter
Min. Typ. Max. Units
Conditions
MOSFET symbol
85
IS
Continuous Source Current
––– –––
A
D
S
(Body Diode)
Pulsed Source Current
showing the
integral reverse
ISM
––– ––– 330
A
G
(Body Diode)
Diode Forward Voltage
p-n junction diode.
TJ = 25°C, IS = 50A, VGS = 0V
ID = 50A
VSD
trr
––– –––
––– 89
1.3
V
ns
nC
A
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
Forward Turn-On Time
130
Qrr
IRRM
ton
VR = 128V,
di/dt = 100A/μs
––– 300 450
––– 6.5 –––
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Pulse width ≤ 400μs; duty cycle ≤ 2%.
ꢀ Rθ is measured at TJ approximately 90°C
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 75A
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.095mH
RG = 25Ω, IAS = 50A, VGS =10V. Part not recommended for use
above this value.
2
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IRFB4321PbF
1000
100
10
1000
100
10
VGS
15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
5.0V
VGS
15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
5.0V
TOP
TOP
BOTTOM
BOTTOM
5.0V
1
≤ 60μs PULSE WIDTH
Tj = 175°C
≤ 60μs PULSE WIDTH
Tj = 25°C
5.0V
1
0.1
0.1
1
10
100
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
DS
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
3.5
3.0
2.5
2.0
1.5
1.0
0.5
1000
100
10
I
= 50A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
= 25V
J
1
V
DS
≤ 60μs PULSE WIDTH
0.1
3.0
4.0
V
5.0
6.0
7.0
8.0
9.0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
, Gate-to-Source Voltage (V)
GS
T
, Junction Temperature (°C)
J
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
7000
6000
5000
4000
3000
2000
1000
0
20
V
C
= 0V,
f = 1 MHZ
GS
I = 50A
D
= C + C , C SHORTED
iss
gs
gd ds
V
= 120V
C
= C
DS
rss
gd
16
12
8
VDS= 75V
VDS= 30V
C
= C + C
ds
oss
gd
Ciss
Coss
4
Crss
V
0
0
20
40
60
80
100
120
1
10
100
Q
Total Gate Charge (nC)
G
, Drain-to-Source Voltage (V)
DS
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB4321PbF
1000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
100μsec
1msec
100
T
= 175°C
J
10
1
10msec
T
= 25°C
J
1
Tc = 25°C
Tj = 175°C
Single Pulse
DC
V
= 0V
GS
0.1
0.1
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1
10
100
1000
V
, Source-to-Drain Voltage (V)
V
, Drain-toSource Voltage (V)
SD
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
190
180
170
160
150
140
90
80
70
60
50
40
30
20
10
0
LIMITED BY PACKAGE
25
50
75
100
125
150
175
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
T
, Case Temperature (°C)
C
T
, Junction Temperature (°C)
J
Fig 9. Maximum Drain Current vs.
Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
5.0
4.0
3.0
2.0
1.0
0.0
500
I
D
TOP
13A
20A
50A
400
300
200
100
0
BOTTOM
0
20
40
60
80
100 120 140 160
25
50
75
100
125
150
175
V
Drain-to-Source Voltage (V)
Starting T , Junction Temperature (°C)
DS,
J
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
4
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IRFB4321PbF
1
D = 0.50
0.20
0.1
R1
R1
R2
R2
R3
R3
τι (sec)
0.10
Ri (°C/W)
τ
J τJ
τ
τ
Cτ
0.085239 0.000052
0.18817 0.00098
0.176912 0.008365
0.05
0.02
0.01
τ
1τ1
τ
2τ2
3τ3
Ci= τi/Ri
Ci= τi/Ri
0.01
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
10
1
Allowed avalanche Current vs avalanche
Duty Cycle = Single Pulse
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
120
100
80
60
40
20
0
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
TOP
BOTTOM 1% Duty Cycle
= 50A
Single Pulse
I
D
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Starting T , Junction Temperature (°C)
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB4321PbF
6.0
40
30
20
10
0
I
I
I
= 1.0A
D
D
D
= 1.0mA
= 250μA
5.0
4.0
3.0
2.0
I
= 33A
F
V
= 128V
R
T
= 125°C
= 25°C
J
T
J
1.0
100 200 300 400 500 600 700 800 900 1000
-75 -50 -25
0
25 50 75 100 125 150 175
, Temperature ( °C )
di / dt - (A / μs)
T
f
J
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
40
3200
2800
2400
2000
1600
1200
800
30
20
I
= 50A
I
= 33A
F
F
10
0
V
= 128V
V
= 128V
R
R
T
= 125°C
= 25°C
T
= 125°C
= 25°C
J
400
J
T
T
J
J
0
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
di / dt - (A / μs)
di / dt - (A / μs)
f
f
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
3200
2800
2400
2000
1600
1200
800
I
= 50A
F
V
= 128V
= 125°C
= 25°C
R
T
400
J
J
T
0
100 200 300 400 500 600 700 800 900 1000
di / dt - (A / μs)
f
Fig. 20 - Typical Stored Charge vs. dif/dt
6
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IRFB4321PbF
Driver Gate Drive
P.W.
P.W.
Period
Period
D =
D.U.T
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple
≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
0.01Ω
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
LD
VDS
VDS
90%
+
-
VDD
10%
VGS
D.U.T
VGS
Pulse Width < 1μs
Duty Factor < 0.1%
td(on)
td(off)
tr
tf
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Vds
Vgs
L
VCC
DUT
0
Vgs(th)
1K
Qgs1
Qgs2
Qgd
Qgodr
Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
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7
IRFB4321PbF
TO-220AB Package Outline (Dimensions are shown in millimeters (inches))
TO-220AB Part Marking Information
EXAMPLE: THIS IS AN IRF1010
PART NUMBER
LOT CODE 1789
ASSEMBLED ON WW 19, 2000
IN THE ASSEMBLY LINE "C"
INTERNATIONAL
RECTIFIER
LOGO
DATE CODE
YEAR 0 = 2000
WE EK 19
Note: "P" in assembly lineposition
indicates "Lead - F ree"
AS S E MB L Y
LOT CODE
LINE C
TO-220AB packages are not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 12/10
8
www.irf.com
IMPORTANT NOTICE
The information given in this document shall in no For further information on the product, technology,
event be regarded as a guarantee of conditions or delivery terms and conditions and prices please
characteristics (“Beschaffenheitsgarantie”) .
contact your nearest Infineon Technologies office
(www.infineon.com).
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement
of intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may
contain dangerous substances. For information on
the types in question please contact your nearest
Infineon Technologies office.
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and
standards concerning customer’s products and any
use of the product of Infineon Technologies in
customer’s applications.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
authorized
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of
the product or any consequences of the use thereof
can reasonably be expected to result in personal
injury.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
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