IRFHM8330PBF [INFINEON]

Compatible with Existing Surface Mount Techniques;


型号：	IRFHM8330PBF
厂家：	Infineon
描述：	Compatible with Existing Surface Mount Techniques
文件：	总10页 (文件大小：675K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IRFHM8330PbF

HEXFET^®Power MOSFET

V_DSS

V_GSmax

±20

R_DS(on)max

(@ V_GS= 10V)

6.6

m

(@ V_GS= 4.5V)

9.9

Qg _(typical)

9.3

I_D

25

(@T_{C (Bottom)}= 25°C)

PQFN 3.3X3.3 mm

Applications

Charge and Discharge Switch for Notebook PC Battery Application

System/Load Switch

Control MOSFET for synchronous buck converter

Features

Benefits

Low Thermal Resistance to PCB (<3.8°C/W)

Low Profile (<1.2mm)

Enable better Thermal Dissipation

Increased Power Density

Multi-Vendor Compatibility

Easier Manufacturing

Industry-Standard Pinout

results in

Compatible with Existing Surface Mount Techniques

RoHS Compliant, Halogen-Free

MSL1, Consumer Qualification



Environmentally Friendlier

Increased Reliability

Base part number

Package Type

Standard Pack

Orderable Part Number

Form

Quantity

IRFHM8330PbF

PQFN 3.3 mm x 3.3 mm

Tape and Reel

4000

IRFHM8330TRPbF

Absolute Maximum Ratings

Parameter

Gate-to-Source Voltage

Max.

± 20

Units

V_GS

I_D@ T_A= 25°C

I_D@ T_A= 70°C

I_D@ T_C(Bottom)= 25°C

I_D@ T_C(Bottom)= 100°C

I_D@ T_C= 25°C

Continuous Drain Current, V_GS@ 10V

55

35

25

Continuous Drain Current, V_GS@ 10V

(Source Bonding Technology Limited)

I_DM

Pulsed Drain Current

Power Dissipation 

Power Dissipation

210

2.7

P_D@T_A= 25°C

P_D@T_C(Bottom)= 25°C

Linear Derating Factor

Operating Junction and

Storage Temperature Range

0.021

W/°C

°C

T_J

-55 to + 150

T_STG

Notes  through  are on page 10

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IRFHM8330PbF

Static @ T_J= 25°C (unless otherwise specified)

Parameter

Min.

Typ.

–––

Max. Units

–––

––– mV/°C Reference to 25°C, I_D= 1.0mA

Conditions

V_GS= 0V, I_D= 250µA

BV_DSS

BV_DSS/T_J

R_DS(on)

Drain-to-Source Breakdown Voltage

Breakdown Voltage Temp. Coefficient

Static Drain-to-Source On-Resistance

–––

1.35

–––

5.3

7.7

1.8

-6.3

–––

9.3

2.7

1.6

2.5

4.1

7.1

1.8

9.2

6.6

9.9

V_GS= 10V, I_D= 20A 

_GS= 4.5V, I_D= 16A 

m

V_GS(th)

V_GS(th)

I_DSS

Gate Threshold Voltage

Gate Threshold Voltage Coefficient

Drain-to-Source Leakage Current

2.35

V_DS= V_GS, I_D= 25µA

––– mV/°C

1.0

150

100

-100

–––

µA V_DS= 24V, V_GS= 0V

V_DS= 24V, V_GS= 0V, T_J= 125°C

nA V_GS= 20V

I_GSS

Gate-to-Source Forward Leakage

Gate-to-Source Reverse Leakage

Forward Transconductance

Total Gate Charge

_GS= -20V

V_DS= 10V, I_D= 20A

nC V_GS= 10V, V_DS= 15V, I_D= 20A

gfs

Q_g

Total Gate Charge

_DS= 15V

_GS= 4.5V

Q_gs1

Q_gs2

Q_gd

Q_godr

Q_sw

Q_oss

R_G

Pre-Vth Gate-to-Source Charge

Post-Vth Gate-to-Source Charge

Gate-to-Drain Charge

Gate Charge Overdrive

Switch Charge (Q_gs2+ Q_gd)

Output Charge

–––

I_D= 20A

nC V_DS= 16V, V_GS= 0V



V_DD= 15V, V_GS= 4.5V

ns I_D= 20A

R_G=1.8

Gate Resistance

t_d(on)

t_r

t_d(off)

t_f

Turn-On Delay Time

Rise Time

Turn-Off Delay Time

Fall Time

5.7

1450

250

110

C_iss

C_oss

C_rss

Input Capacitance

Output Capacitance

Reverse Transfer Capacitance

V_GS= 0V

V_DS= 25V

ƒ = 1.0MHz

Avalanche Characteristics

Parameter

Single Pulse Avalanche Energy 

Typ.

–––

Max.

Units

E_AS

Diode Characteristics

Parameter

Min. Typ. Max. Units

Conditions

MOSFET symbol

showing the

I_S

Continuous Source Current

(Body Diode)

––– ––– 25

––– ––– 210

I_SM

Pulsed Source Current

(Body Diode) 

integral reverse

p-n junction diode.

V_SD

t_rr

Q_rr

Diode Forward Voltage

Reverse Recovery Time

Reverse Recovery Charge

––– ––– 1.0

T_J= 25°C, I_S= 20A, V_GS= 0V 

T_J= 25°C, I_F= 20A, V_DD= 15V

––– 14

––– 23

nC di/dt = 390A/µs 

Thermal Resistance

Parameter

Typ.

–––

Max.

3.8

Units

Junction-to-Case 

R_JC(Bottom)

R_JC(Top)

°C/W

Junction-to-Case 

Junction-to-Ambient 

Junction-to-Ambient 

–––

R_JA

R_JA(<10s)

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IRFHM8330PbF

1000

100

1000

100

VGS

10V

VGS

10V

TOP

7.0V

5.0V

4.5V

3.5V

3.0V

2.8V

2.5V

7.0V

5.0V

4.5V

3.5V

3.0V

2.8V

2.5V

BOTTOM

2.5V

60µs PULSE WIDTH

Tj = 150°C



60µs PULSE WIDTH

Tj = 25°C



0.1

100

1000

0.1

100

1000

, Drain-to-Source Voltage (V)

Fig 2. Typical Output Characteristics

Fig 1. Typical Output Characteristics

1.8

1.6

1.4

1.2

1.0

0.8

0.6

1000

= 20A

= 10V

T = 150°C

100

T = 25°C

= 15V



60µs PULSE WIDTH

1.0

-60 -40 -20

20 40 60 80 100 120 140 160

T , Junction Temperature (°C)

, Gate-to-Source Voltage (V)

Fig 4. Normalized On-Resistance vs. Temperature

Fig 3. Typical Transfer Characteristics

14.0

10000

1000

100

= 0V,

f = 1 MHZ

I = 20A

= C + C , C SHORTED

iss

12.0

= C

rss

oss

= 24V

= 15V

= 6.0V

= C + C

10.0

8.0

6.0

4.0

2.0

0.0

iss

oss

rss

, Drain-to-Source Voltage (V)

100

Q , Total Gate Charge (nC)

Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage

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IRFHM8330PbF

1000

100

1000

100

OPERATION IN THIS AREA

LIMITED BY R

(on)

100µsec

1msec

T = 150°C

Limited by package

10msec

T = 25°C

0.1

0.01

Tc = 25°C

Tj = 150°C

Single Pulse

= 0V

1.4

1.0

0.1

100

0.2

0.4

0.6

0.8

1.0

1.2

1.6

, Drain-to-Source Voltage (V)

, Source-to-Drain Voltage (V)

Fig 8. Maximum Safe Operating Area

Fig 7. Typical Source-Drain Diode Forward Voltage

2.6

2.4

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

Limited By Source

Bonding Technology



= 25µA

= 250µA

= 1.0mA

= 1.0A

100

125

150

-75 -50 -25

25 50 75 100 125 150

, Case Temperature (°C)

T , Temperature ( °C )

Fig 10. Drain-to–Source Breakdown Voltage

Fig 9. Maximum Drain Current vs. Case Temperature

D = 0.50

0.20

0.10

0.05

0.1

0.02

0.01

SINGLE PULSE

( THERMAL RESPONSE )

Notes:

1. Duty Factor D = t1/t2

2. Peak Tj = P dm x Zthjc + Tc

0.001

1E-006

1E-005

0.0001

0.001

0.01

0.1

, Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

June 30, 2014

IRFHM8330PbF

200

150

100

= 20A

TOP

4.0A

8.5A

BOTTOM 20A

T = 125°C

T = 25°C

100

125

150

Starting T , Junction Temperature (°C)

Gate -to -Source Voltage (V)

GS,

Fig 13. Maximum Avalanche Energy vs. Drain Current

Fig 12. On-Resistance vs. Gate Voltage

100

Allowed avalanche Current vs avalanche



pulsewidth, tav, assuming Tj = 125°C and

Tstart =25°C (Single Pulse)

Allowed avalanche Current vs avalanche

pulsewidth, tav, assuming  j = 25°C and

Tstart = 125°C.

0.1

1.0E-06

1.0E-05

1.0E-04

1.0E-03

1.0E-02

1.0E-01

tav (sec)

Fig 14. Single Avalanche Event: Pulse Current vs. Pulse Width

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IRFHM8330PbF

Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET^®Power MOSFETs

(BR)DSS

15V

DRIVER

D.U.T

20V

0.01



Fig 16a. Unclamped Inductive Test Circuit

Fig 16b. Unclamped Inductive Waveforms

Fig 17a. Switching Time Test Circuit

Fig 17b. Switching Time Waveforms

Vds

Vgs

VDD

Vgs(th)

Qgs1

Qgs2

Qgd

Qgodr

Fig 18b. Gate Charge Waveform

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Fig 18a. Gate Charge Test Circuit

IRFHM8330PbF

Placement and Layout Guidelines

The typical application topology for this product is the synchronous buck converter. These converters operate at high

frequencies (typically around 400 kHz). During turn-on and turn-off switching cycles, the high di/dt currents circulating in

the parasitic elements of the circuit induce high voltage ringing which may exceed the device rating and lead to

undesirable effects. One of the major contributors to the increase in parasitics is the PCB power circuit inductance.

This section introduces a simple guideline that mitigates the effect of these parasitics on the performance of the circuit

and provides reliable operation of the devices.

To reduce high frequency switching noise and the effects of Electromagnetic Interference (EMI) when the control

MOSFET (Q1) is turned on, the layout shown in Figure 19 is recommended. The input bypass capacitors, control

MOSFET and output capacitors are placed in a tight loop to minimize parasitic inductance which in turn lowers the

amplitude of the switch node ringing, and minimizes exposure of the MOSFETs to repetitive avalanche conditions.

When the synchronous MOSFET (Q2) is turned on, high average DC current flows through the path indicated in Figure

19. Therefore, the Q2 turn-on path should be laid out with a tight loop and wide traces at both ends of the inductor to

minimize loop resistance.

Fig 19. Placement and Layout Guidelines

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IRFHM8330PbF

PQFN 3.3mm x 3.3mm Outline Package Details

For more information on board mounting, including footprint and stencil recommendation, please refer to application note

AN-1136: http://www.irf.com/technical-info/appnotes/an-1136.pdf

For more information on package inspection techniques, please refer to application note AN-1154:

http://www.irf.com/technical-info/appnotes/an-1154.pdf

PQFN 3.3mm x 3.3mm Outline Part Marking

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

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IRFHM8330PbF

PQFN 3.3mm x 3.3mm Outline Tape and Reel

REEL DIMENSIONS

TAPE DIMENSIONS

DIMENSION (MM)

DIMENSION (INCH)

CODE

MIN

3.50

1.10

7.90

11.80

12.30

MAX

3.70

MIN

.138

.043

.311

.465

.484

MAX

.146

.051

.319

.480

.492

3.70

1.30

8.10

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

12.20

12.50

Qty

4000

13 Inches

Reel Diameter

CODE

DESCRIPTION

Dimension design to accommodate the component width

Dimension design to accommodate the component lenght

Dimension design to accommodate the component thickness

Overall width of the carrier tape

Pitch between successive cavity centers

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

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IRFHM8330PbF

Qualification Information^†

Qualification Level

Consumer

(per JEDEC JESD47F^††guidelines)

MSL1

PQFN 3.3mm x 3.3mm

Moisture Sensitivity Level

RoHS Compliant

(per JEDEC J-STD-020D^††)

Yes

†

Qualification standards can be found at International Rectifier’s web site: http://www.irf.com/product-info/reliability

†† Applicable version of JEDEC standard at the time of product release.

Notes:

 Starting T_J= 25°C, L = 0.21mH, R_G= 50, I_AS= 20A.

 Pulse width  400µs; duty cycle  2%.

 R_is measured at T_Jof approximately 90°C.

 When mounted on 1 inch square PCB (FR-4). Please refer to AN-994 for more details:

http://www.irf.com/technical-info/appnotes/an-994.pdf

 Calculated continuous current based on maximum allowable junction temperature.

 Current is limited to 25A by source bonding technology.

 Pulse drain current is limited by source bonding technology.

Revision History

Date

Comments

 Updated schematic on page 1

 Updated tape and reel on page 9

6/6/14

6/30/14

 Remove “SAWN” package outline on page 8.

IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA

To contact International Rectifier, please visit http://www.irf.com/whoto-call/

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IRFHM8330PBF [INFINEON]

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