IRFI7536GPBF [INFINEON]
Power Field-Effect Transistor;
| 型号： | IRFI7536GPBF |
| 厂家： | 
Infineon |
| 描述： | Power Field-Effect Transistor |
| 文件： | 总9页 (文件大小：344K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IRFI7536GPbF
HEXFET® Power MOSFET
D
S
VDSS
RDS(on) typ.
max.
60V
2.7m
3.4m
86A
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
G
ID (Silicon Limited)
l Hard Switched and High Frequency Circuits
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
D
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
S
D
G
TO-220
Full-Pak
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
IDM
Parameter
Max.
86
Units
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Pulsed Drain Current
73
820
A
75
PD @TC = 25°C
Maximum Power Dissipation
W
0.5
Linear Derating Factor
W/°C
V
± 20
VGS
TJ
Gate-to-Source Voltage
-55 to + 175
Operating Junction and
°C
TSTG
Storage Temperature Range
300 (1.6mm from case)
10lbf in (1.1N m)
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
EAS
Single Pulse Avalanche Energy (Thermally Limited)
738
mJ
A
Avalanche Current
IAR
See Fig. 14, 15, 22a, 22b
Repetitive Avalanche Energy
EAR
mJ
Thermal Resistance
Symbol
Parameter
Typ.
–––
Max.
2.87
65
Units
°C/W
Rθ
JC
Junction-to-Case
Rθ
Junction-to-Ambient (PCB Mount)
–––
JA
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1
IRFI7536GPbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
Parameter
Drain-to-Source Breakdown Voltage
Min. Typ. Max. Units
Conditions
VGS = 0V, ID = 250µA
60
–––
–––
2.0
88
––– –––
V
V
/ T Breakdown Voltage Temp. Coefficient
∆
29
2.7
–––
––– mV/°C Reference to 25°C, ID = 1.0mA
∆
(BR)DSS
J
RDS(on)
VGS(th)
gfs
Static Drain-to-Source On-Resistance
3.4
4.0
m
VGS = 10V, ID = 75A
VDS = VGS, ID = 150µA
VDS = 25V, ID = 75A
Ω
Gate Threshold Voltage
V
Forward Transconductance
Internal Gate Resistance
––– –––
S
RG
––– 0.79 –––
––– ––– 20
Ω
IDSS
Drain-to-Source Leakage Current
µA VDS = 60V, VGS = 0V
––– ––– 250
––– ––– 100
––– ––– -100
V
DS = 60V, VGS = 0V, TJ = 125°C
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
nA VGS = 20V
VGS = -20V
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter
Total Gate Charge
Min. Typ. Max. Units
––– 130 195 nC ID = 75A
VDS = 30V
GS = 10V
ID = 75A, VDS =0V, VGS = 10V
ns VDD = 39V
Conditions
Qg
Qgs
Qgd
Qsync
td(on)
tr
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
Turn-On Delay Time
Rise Time
–––
–––
–––
–––
–––
–––
–––
31
42
88
22
77
55
64
–––
–––
–––
–––
–––
–––
–––
V
ID = 75A
td(off)
tf
Turn-Off Delay Time
Fall Time
R = 2.7
Ω
G
VGS = 10V
Ciss
Coss
Crss
Input Capacitance
––– 6600 –––
––– 720 –––
––– 400 –––
––– 1080 –––
––– 1400 –––
pF VGS = 0V
Output Capacitance
Reverse Transfer Capacitance
VDS = 48V
ƒ = 1.0 MHz, See Fig. 5
Coss eff. (ER) Effective Output Capacitance (Energy Related)
oss eff. (TR) Effective Output Capacitance (Time Related)
VGS = 0V, VDS = 0V to 48V , See Fig. 11
C
V
GS = 0V, VDS = 0V to 48V
Diode Characteristics
Symbol Parameter
Min. Typ. Max. Units
Conditions
MOSFET symbol
D
S
IS
Continuous Source Current
––– –––
––– ––– 820
––– ––– 1.3
86
A
A
V
(Body Diode)
showing the
G
ISM
Pulsed Source Current
integral reverse
(Body Diode)
p-n junction diode.
TJ = 25°C, IS = 75A, VGS = 0V
VSD
dv/dt
trr
Diode Forward Voltage
Peak Diode Recovery
–––
–––
–––
–––
–––
–––
3.3
43
53
58
65
2.4
––– V/ns TJ = 25°C, IS = 75A, VDS = 60V
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
–––
–––
–––
–––
–––
ns TJ = 25°C
TJ = 125°C
VR = 51V,
IF = 75A
di/dt = 100A/µs
Qrr
nC TJ = 25°C
TJ = 125°C
IRRM
A
TJ = 25°C
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.26mH,
RG = 50Ω, IAS = 75A, VGS =10V. Part not recommended for use
above this value.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS
Rθ is measured at TJ approximately 90°C.
RθJC value shown is at time zero.
.
ISD ≤ 75A, di/dt ≤ 890A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
ꢀ Coss eff. (TR) is a fixed capacitance that gives the same charging
time as Coss while VDS is rising from 0 to 80% VDSS
.
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October 16, 2013
2
IRFI7536GPbF
1000
100
10
1000
100
10
VGS
15V
12V
VGS
15V
12V
TOP
TOP
10V
10V
6.0V
5.0V
4.75V
4.50V
4.25V
6.0V
5.0V
4.75V
4.50V
4.25V
BOTTOM
BOTTOM
4.25V
4.25V
60µs PULSE WIDTH
≤
Tj = 175°C
60µs PULSE WIDTH
Tj = 25°C
≤
1
1
0.01
0.1
1
10
100
0.01
0.1
1
10
100
V
, Drain-to-Source Voltage (V)
DS
V
, Drain-to-Source Voltage (V)
DS
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000
100
10
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
I
= 75A
D
V
= 10V
GS
T
= 175°C
J
T
= 25°C
= 25V
J
V
DS
≤
60µs PULSE WIDTH
1.0
2
3
4
5
6
7
-60 -40 -20 0 20 40 60 80 100120140160180
, Junction Temperature (°C)
T
J
V
, Gate-to-Source Voltage (V)
GS
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
14.0
100000
10000
1000
V
= 0V,
= C
f = 1 MHZ
GS
I = 75A
D
C
C
C
+ C , C
SHORTED
ds
iss
gs
gd
12.0
= C
rss
oss
gd
= C + C
V
V
V
= 48V
= 30V
= 12V
DS
DS
DS
ds
gd
10.0
8.0
6.0
4.0
2.0
0.0
C
C
iss
oss
rss
C
100
0
20 40 60 80 100 120 140 160 180
, Total Gate Charge (nC)
1
10
, Drain-to-Source Voltage (V)
100
Q
V
G
DS
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFI7536GPbF
1000
100
10
10000
1000
100
10
OPERATION IN THIS AREA
LIMITED BY R (on)
DS
100µsec
T
= 175°C
J
1msec
10msec
DC
T
= 25°C
J
1
Tc = 25°C
Tj = 175°C
Single Pulse
V
= 0V
2.5
GS
1.0
0.1
0.0
0.5
1.0
1.5
2.0
3.0
175
70
0.1
1
10
100
V
, Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
100
80
60
40
20
0
72
70
68
66
64
62
60
I
= 1.0mA
D
25
50
75
100
125
150
-60 -40 -20 0 20 40 60 80 100120140160180
, Temperature ( °C )
T
, Case Temperature (°C)
T
J
C
Fig 9. Maximum Drain Current vs.
Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
3000
I
D
TOP
8.6A
12A
2500
2000
1500
1000
500
BOTTOM 75A
0
0
10
V
20
30
40
50
60
25
50
75
100
125
150
175
Starting T , Junction Temperature (°C)
J
Drain-to-Source Voltage (V)
DS,
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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4
IRFI7536GPbF
10
1
D = 0.50
0.20
0.10
0.05
0.1
0.02
0.01
0.01
0.001
0.0001
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
10
100
t
, Rectangular Pulse Duration (sec)
1
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
100
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τj = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
tav (sec)
1.0E-02
1.0E-01
1.0E+00
Fig 14. Single Avalanche Event: Pulse Current vs. Pulse Width
800
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
TOP
BOTTOM 1.0% Duty Cycle
= 75A
Single Pulse
700
600
500
400
300
200
100
0
I
D
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25
50
75
100
125
150
175
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Starting T , Junction Temperature (°C)
J
Fig 15. Maximum Avalanche Energy vs. Temperature
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October 16, 2013
IRFI7536GPbF
16
14
12
10
8
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
I = 30A
F
V
= 51V
R
T = 25°C
J
T = 125°C
J
I
I
I
= 150µA
= 1.0mA
= 1.0A
D
D
D
6
4
2
-75
-25
25
75
125
175
0
200
400
600
800
1000
di /dt (A/µs)
T
J
, Temperature ( °C )
F
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage vs. Temperature
16
500
I = 30A
I = 45A
F
F
14
12
10
8
V
= 51V
V
= 51V
R
R
400
300
200
100
0
T = 25°C
T = 25°C
J
J
T = 125°C
J
T = 125°C
J
6
4
2
0
200
400
600
800
1000
0
200
400
600
800
1000
di /dt (A/µs)
di /dt (A/µs)
F
F
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
500
I = 45A
F
V
= 51V
R
400
300
200
100
0
T = 25°C
J
T = 125°C
J
0
200
400
600
800
1000
di /dt (A/µs)
F
Fig. 20 - Typical Stored Charge vs. dif/dt
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October 16, 2013
6
IRFI7536GPbF
Driver Gate Drive
P.W.
P.W.
Period
D.U.T
Period
D =
+
*
=10V
V
GS
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D.U.T. I Waveform
SD
+
-
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
-
+
D.U.T. V Waveform
DS
Diode Recovery
dv/dt
V
DD
VDD
Re-Applied
Voltage
• dv/dt controlled by RG
RG
+
-
Body Diode
Forward Drop
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
Inductor Current
I
SD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V
(BR)DSS
15V
t
p
DRIVER
+
L
V
DS
D.U.T
AS
R
G
V
DD
-
I
A
V
2
GS
Ω
0.01
t
p
I
AS
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
V
DS
90%
VGS
D.U.T.
RG
+
VDD
-
VGS
10%
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
V
GS
t
t
r
t
t
f
d(on)
d(off)
Fig 23a. Switching Time Test Circuit
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
.2µF
12V
.3µF
+
V
DS
D.U.T.
-
Vgs(th)
V
GS
3mA
I
I
D
G
Qgs1
Qgs2
Qgd
Qgodr
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
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Fig 24b. Gate Charge Waveform
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7
IRFI7536GPbF
TO-220 Full-Pak Package Outline
Dimensions are shown in millimeters (inches)
TO-220 Full-Pak Part Marking Information
TO-220AB Full-Pak packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
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October 16, 2013
8
IRFI7536GPbF
Qualification information†
Cons umer††
(per JEDEC JESD47F ††† guidelines )
Qualification level
MS L 1
Moisture Sensitivity Level
RoHS compliant
TSOP-6
(per IP C/JE DE C J-S T D-020D†††
)
Yes
†
Qualification standards can be found at International Rectifier’s web site
http://www.irf.com/product-info/reliability
††
Higher qualification ratings may be available should the user have such requirements.
Please contact your International Rectifier sales representative for further information:
http://www.irf.com/whoto-call/salesrep/
††† Applicable version of JEDEC standard at the time of product release.
IR WORLD HEADQUARTERS: 101 N. Sepulveda Blvd., El Segundo, California 90245, USA
To contact International Rectifier, please visit http://www.irf.com/whoto-call/
9
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October 16, 2013
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